A method for deep etching in dielectric films for 3D-chip and photonics applications

In this paper, RIE of thick undoped silicate glass (USG) films for various applications is described. Though moderate etch rates (∼0.4 μm/min) were achieved for USG film, process development was quite challenging due to stringent requirements of deep USG etching (>6 μm) and vertical profile. Alternatively, etch process with higher etch rate (1.0 μm/min) was also evaluated for profile angle and results were found not comparable to low etch rate process. However, low etch rate process was found to have tool limitations and an alternate method called ‘discrete etching’ was proposed and successfully verified. Promising results were obtained with etch depth (6 μm) and vertical profile (∼89.50°) in USG as well as SiON films. Based on the results discrete etching method was found to have provided advantage of unlimited capability for deep etching.     

固化温度曲线对聚酰亚胺薄膜稳定性的影响

The effects of cure temperature history on the stability of hinged structure poly(4,4-oxydiphenylene pyromellitimide)(PMDA-ODA) polyimide were studied by dynamic mechanical analysis.The polyimide films were cured under different curing conditions and peeled off by substrate etching.It was found that a proper cure time and temperature ramp rate improves the stability in terms of higher glass transition temperature.Ninety minutes at 375℃or 200℃is a beneficial high glass transition temperature.The temperature ramp rate should be between 2℃/min and 10℃/min,which is neither too high nor too low.     

Investigations of solution variables in a contactless copper electrodeposition process for 3D packaging applications

A novel electrochemical method for contactless electrodeposition of copper onto silicon wafers has been investigated. Deposition parameters such as applied current, concentrations of deposition solution and supporting electrolyte were optimized to achieve high deposition rates as well as homogenous deposition of copper. Copper sulfate solution temperature of about 65 °C was shown to be suitable for achieving stable and high values of current density that translated to copper deposition rates of~2.4 µm/min with good deposition uniformity.     

Potential of amorphous Mo–Si–N films for nanoelectronic applications

The properties of amorphous metallic molybdenum–silicon–nitrogen (Mo–Si–N) films were characterised for use in nanoelectronic applications. The films were deposited by co-sputtering of molybdenum and silicon targets in a gas mixture of argon and nitrogen. The atomic composition, microstructure and surface roughness were studied by RBS, TEM and AFM analyses, respectively. The electrical properties were investigated in the temperature range 80 mK to 300 K. No transition into a superconductive state was observed. Nanoscale wires were fabricated using electron beam lithography with their properties measured as a function of temperature.     

超高速VLSI中多晶硅发射极晶体管串联电阻的测量

本文对目前流行的测量晶体管串联电阻的常规方法进行了理论分析和实验验证，结果表明，用常规方法测量多晶硅发射极晶体管串联电阻的误差很大。     

Research on the contact resistance,reliability, and degradation mechanisms of anisotropically conductive film interconnection for flip-chip-on-flex applications

Although there have been many years of development, the degradation of the electrical performance of anisotropically conductive adhesive or film (ACA or ACF) interconnection for flip-chip assembly is still a critical drawback despite wide application. In-depth study about the reliability and degradation mechanism of ACF interconnection is necessary. In this paper, the initial contact resistance, electrical performance after reliability tests, and degradation mechanisms of ACF interconnection for flip-chip-on-flex (FCOF) assembly were studied using very-low-height Ni and Au-coated Ni-bumped chips. The combination of ACF and very-low-height bumped chips was considered because it has potential for very low cost and ultrafine pitch interconnection. Contact resistance changes were monitored during reliability tests, such as high humidity and temperature and thermal cycling. The high, initial contact resistance resulted from a thin oxide layer on the surface of the bumps. The reliability results showed that the degradation of electrical performance was mainly related to the oxide formation on the surface of deformed particles with non-noble metal coating, the severe metal oxidation on the conductive surface of bumps, and coefficient of thermal expansion (CTE) mismatch between the ACF adhesive and the contact conductive-surface metallization. Some methods for reducing initial contact resistance and improving ACF interconnection reliability were suggested. The suggestions include the removal of the oxide layer and an increase of the Au-coating film to improve conductive-surface quality, appropriate choice of conductive particle, and further development of better polymeric adhesives with low CTE and high electrical performance.     

System level design and optimization of single-loop CT sigma-delta modulators for high resolution wideband applications

In this paper, the main resolution limitations in single-stage continuous-time sigma-delta modulators (CT ΣΔMs) are analytically estimated as the function of system level parameters for wideband applications. The analytical results are supported by simulation results. The power consumption of CT ΣΔMs is also analytically estimated as the function of system level parameters, and then, it is validated by the reported power consumption of several state-of-the-art fabricated prototypes. Based on analytical results, for a targeted resolution and bandwidth, an algorithm is proposed to design the system level parameters of CT ΣΔMs for the minimum power consumption. The estimation of power consumption and the designed parameters match well with the design of best state-of-the-art fabricated modulators.