Linearization of mixers using predistortion and envelope signal injection

This letter presents a new linearization method for mixers employing predistortion and envelope signal injection. In this technique the third order intermodulation distortion (IM3), at the output of a mixer in IF band, was cancelled by using a diode predistortor and injecting the envelope of the RF input signal to both the predistortor and the mixer. By properly adjusting the amplitude and polarity of the injected envelope signal, up to 26 dB improvement of the IM3 is obtained in a two tone test with 100 kHz separation at 1.9 GHz. This method operates very well over a wide range of output power up to the 1 dB compression point of the mixer.     

2-Gbit/s signal amplification at λ=1.53 μm in anerbium-doped single-mode fiber amplifier

The gain, saturation power, and noise of an erbium-doped single-mode traveling-wave fiber amplifier operating at a wavelength λ=1.53 μm are characterized. In continuous-wave (CW) measurements amplification at 2 Gbit/s was demonstrated with up to 17-dB gain for 1×10^-9 bit error rate at 1.531 μm and a 3-dB full bandwidth of 14 nm. From the determination of the fiber-amplifier's output signal-to-noise ratio versus input signal power during data transmission, it was concluded that, with signal levels used here, signal-spontaneous beat noise limited the receiver sensitivity improvement. With the fiber amplifier acting as an optical preamplifier of the receiver, the best sensitivity was -30 dBm, obtained after installing a polarizer at the fiber amplifier output to reject half of the applied spontaneous emission power. This sensitivity was 6 dB better than without the fiber amplifier, proving that the fiber amplifier can be used as a preamplifier     

Linearized mixer using predistortion technique

A predistortion technique has been proposed to reduce intermodulation distortion (IMD) generated from the conversion process of a mixer. In this technique, the IMD generated from a mixer in the IF band was cancelled by the controlled RF error signal, which is generated by a predistorter. The magnitude and phase of the RF error signal were properly adjusted through a vector modulator. This linearization technique has been verified by experiment of a down conversion mixer in the cellular band. A two tone test has been performed at the frequency of 836 MHz with 442 kHz separation. The results show that this method improves about 16 dB of IMD3 at -18 dBm IF output power in 10 MHz frequency band and increases about 3.5 dB of P1 dB of the mixer. Simple topology and good performance in linearization of IF signals renders this technique suitable for highly linear frequency conversion in communication systems     

A Linearization Technique for RF Receiver Front-End Using Second-Order-Intermodulation Injection

A linearization technique is proposed in which low-frequency second-order-intermodulation $({rm IM}_{2})$ is generated and injected to suppress the third-order intermodulation $({rm IM}_{3})$. The proposed linearization technique is applied to both a low-noise amplifier (LNA) and a down-conversion mixer in an RF receiver front-end (RFE) working at 900 MHz. Fabricated in a 0.18$ mu{hbox{m}}$ CMOS process and operated at 1.5 V supply with a total current of 13.1 mA, the RFE delivers 22 dB gain with 5.3 dB noise figure (NF). The linearization technique achieves around 20 dB ${rm IM}_{3}$ suppression and improves the RFE's ${rm IIP}_{3}$ from $-$ 10.4 dBm to 0.2 dBm without gain reduction and noise penalty while requiring only an extra current of 0.1 mA.      

Low-voltage 1.9-GHz front-end receiver in 0.5-μm CMOS technology

This paper describes the design of a 1.9-GHz front-end receiver. The target application of the receiver is the personal communications standard PCS1900. Powered by a 1-V supply, the receiver consists of a low noise amplifier (LNA) and a downconversion mixer. The receiver was fabricated within a 0.5-μm CMOS technology. The LNA features 15 dB of gain and a 1.8-dB noise figure. The mixer exhibits 1.5-dB conversion loss, 12-dB noise figure, and 0 dBm 1 dB-compression point     

An adaptive predistorter for a power amplifier based on adjacentchannel emissions [mobile communications]

A slowly adapting predistorter is presented. The approach is to minimize the transmitter output power in spectral regions occupied only by intermodulation (IM) products. In this way, only a spot power measurement is required. This technique relies on the principle that the power amplifier's characteristics vary slowly with time. By monitoring the out-of-band power one can obtain an estimate for the distortion introduced by the power amplifier. Adaptation is accomplished by iterative adjustment of the predistorter parameters to minimize the IM power. For a polynomial predistorter, the authors analytically demonstrate that the IM power is a quadratic function of the coefficients. A variety of algorithms therefore apply. The authors present an analog static predistortion linearization circuit that uses the envelope of the baseband signal to generate the nonlinear functional used in predistorting the input signal. The improvement obtained with an amplitude-modulated input signal was 15 dB in the third- and 5 dB in the fifth-order intermodulation products. The IM improvement could be maintained with the use of a robust direct search algorithm     

5-GHz CMOS radio transceiver front-end chipset

Incorporating the direct-conversion architecture, a 5-GHz band radio transceiver front end chipset for wireless LAN applications is implemented in a 0.25-μm CMOS technology. The 4-mm² 5.25-GHz receiver IC contains a low noise amplifier with 2.5-dB noise figure (NF) and 16-dB power gain, a receive mixer with 12.0 dB single sideband NF, 13.7-dB voltage gain, and -5 dBm input 1-dB compression point. The 2.7-mm² transmitter IC achieves an output 1-dB compression of -2.5 dBm at 5.7 GHz with 33.4-dB (image) sideband rejection by using an integrated quadrature voltage-controlled oscillator. Operating from a 3-V supply, the power consumptions for the receiver and transmitter are 114 and 120 mW, respectively     

A 850-GHz waveguide receiver employing a niobium SIS junctionfabricated on a 1-μm Si3N4 membrane

We report on a 850-GHz superconducting-insulator-superconducting (SIS) heterodyne receiver employing an RF-tuned niobium tunnel junction with a current density of 14 kA/cm², fabricated on a 1-μm Si₃N₄ supporting membrane. Since the mixer is designed to be operated well above the superconducting gap frequency of niobium (2Δ/h≈690 GHz), special care has been taken to minimize niobium transmission-line losses. Both Fourier transform spectrometer (FTS) measurements of the direct detection performance and calculations of the IF output noise with the mixer operating in heterodyne mode, indicate an absorption loss in the niobium film of about 6.8 dB at 822 GHz. These results are in reasonably good agreement with the loss predicted by the Mattis-Bardeen theory in the extreme anomalous limit. From 800 to 830 GHz, we report uncorrected receiver noise temperatures of 518 or 514 K when we use Callen and Welton's law to calculate the input load temperatures. Over the same frequency range, the mixer has a 4-dB conversion loss and 265 K±10 K noise temperature. At 890 GHz, the sensitivity of the receiver has degraded to 900 K, which is primarily the result of increased niobium film loss in the RF matching network. When the mixer was cooled from 4.2 to 1.9 K, the receiver noise temperature improved about 20% 409-K double sideband (DSB). Approximately half of the receiver noise temperature improvement can be attributed to a lower mixer conversion loss, while the remainder is due to a reduction in the niobium film absorption loss. At 982 GHz, we measured a receiver noise temperature of 1916 K     

A high IIP2 downconversion mixer using dynamic matching

This paper presents an RF downconversion mixer with improved rejection to second-order intermodulation for RF application within a direct-conversion receiver requiring high input blocking performance. The mixer, implemented in a 2.7-V 0.35-μm BiCMOS process, achieves a second-order input intercept point of at least +72 dBm for a BiCMOS design and at least +66 dBm for an all-CMOS design. The design utilizes dynamic matching to enhance the balance of a fully differential mixer through mitigation of both component and device mismatches. In addition, dynamic matching is shown to improve the mixer's 1/f noise performance. For an all-CMOS mixer design, a 30-dB improvement in the mixer's noise floor at 1 kHz has been observed compared to conventional fully differential CMOS Gilbert-cell mixer. Additionally, background is given on second-order intermodulation and on system IIP2 requirements for a direct-conversion receiver     

A low-voltage ultra-wideband down-conversion mixer with improved power conversion gain

This article presents a wideband mixer using a TSMC 0.18?µm complementary metal-oxide semiconductor technology process for ultra-wideband (UWB) system applications. The measured 3-dB radio frequency (RF) bandwidth is from 3 to 8.4?GHz with an intermediate frequency of 10?MHz. The measurement results of the proposed mixer achieve 8.1?dB average power conversion gain ?5?dBm input third-order intercept point (IIP3) at 7.4?GHz and 12.4–13.3?dB double side band noise figure. The total dc power consumption of this mixer including output buffers is 3.18?mW from a 1?V supply voltage. The output current buffer consumption is about 2.26?mW with an excellent local oscillator-RF isolation of up to 40?dB at 5?GHz. The article presents a mixer topology that is greatly suitable for low-power operation in UWB system applications.     

A direct conversion receiver with an IP2 calibrator for CDMA/PCS/GPS/AMPS applications

A second-order intercept point (IP2) calibration technique is developed using common-mode feedback (CMFB) circuitry in a direct-conversion receiver for wireless CDMA/PCS/GPS/AMPS applications. The IP2 calibrator is capable of providing different CMFB gain to tune its common-mode output impedance for each of the positive and negative mixer outputs. The CDMA mixer applying this method achieved a second-order input intercept point (IIP2) of 64 dBm, a third-order input intercept point (IIP3) of 4 dBm, a noise figure of 6.5 dB and a voltage gain of 42.2 dB. This result shows a 20 dB improvement from an uncalibrated IIP2 of 44 dBm. The receiver RFIC is implemented in a 0.5-/spl mu/m SiGe BiCMOS process, and it operates from a 2.7 to 3.1 V single power supply.     

An analytic approach for CDMA output of feedforward power amplifier

In this paper, a novel method is introduced to predict the Code-Division Multiple-Access (CDMA) output spectrum of an RF power amplifier linearized with feedforward technique based on transfer function. In this method, an RF power amplifier is modeled mathematically by nonlinear complex envelope transfer function based on AM-AM and AM-PM distortion diagrams. Using this model, analytic expressions of CDMA output spectrum of power amplifier is calculated. Having mathematical model of RF power amplifier leads to derive analytic expressions for InterModulation (IM) products in feedforward amplifier. Based on these expressions, IM products are related to nonlinear complex envelope transfer function of feedforward amplifier. Then, CDMA output spectrum of feedforward linearization technique is predicted. The loops imbalances in feedforward technique are considered in analysis. Finally, the results of derived expressions in MATLAB software are compared with ADS simulations results and good agreements were achieved. Employing this method gives insight for feedforward analysis and loops imbalances effects in feedforward amplifier for CDMA applications.     

All Solid-State Low-Noise Receivers for 210-240 GHz

Low-noise all solid-state receiver systems for room temperature and cryogenic operation between 210 and 240 GHz are described. The receivers incorporate a single-ended fixed tuned Schottky barrier diode mixer, a frequency-tripled Gunn source as local oscillator and a GaAsFET IF amplifier. Single sideband receiver noise temperatures are typically 1300 K (7.39-dB noise figure) for a room temperature system and 470 K (4.18-dB noise figure) for a cryogenically cooled receiver operating at 20 K.     

A "divide and conquer" technique for implementing wide dynamic range continuous-time filters

This paper presents a technique for implementing analog filters with wide dynamic range and low power dissipation and chip area. The desired dynamic range of the filter is divided into subranges, each covered by a different filtering path optimized specifically for this subrange. This results in small admittance levels for the individual filtering paths and correspondingly small power dissipation and chip area. The system provides undisturbed output during range switching, contrary to conventional automatic gain control (AGC)/filter arrangements that generate disturbances every time the gain of the AGC changes. We also report on a low-noise highly linear CMOS transconductor useful for high-frequency applications. A chip implementing the ideas of this paper was fabricated in a 0.25-/spl mu/m digital CMOS process. The intended application of the filter is channel selection in an 802.11a/Hiperlan2 Wireless Ethernet receiver. The chip dissipates 9 mA, occupies an area of 0.7 mm/sup 2/, and maintains a signal/(noise + IM3 distortion) ratio of at least 33 dB over a 48-dB signal range, with good blocker immunity. This performance represents at least an order of magnitude improvement over existing channel selection filters, even those that do not achieve disturbance-free operation.     

A CMOS switched transconductor mixer

A new CMOS active mixer topology can operate at low supply voltages by the use of switches exclusively connected to the supply voltages. Such switches require less voltage headroom and avoid gate-oxide reliability problems. Mixing is achieved by exploiting two transconductors with cross-coupled outputs, which are alternatingly activated by the switches. For ideal switching, the operation is equivalent to a conventional active mixer. This paper analyzes the performance of the switched transconductor mixer, in comparison with the conventional mixer, demonstrating competitive performance at a lower supply voltage. Moreover, the new mixer has a fundamental noise benefit, as noise produced by the switch-transistors and LO-port is common mode noise, which is rejected at the differential output. An experimental prototype with 12-dB conversion gain was designed and realized in standard 0.18-/spl mu/m CMOS to operate at only a 1-V supply. Experimental results show satisfactory mixer performance up to 4 GHz and confirm the fundamental noise benefit.     

A 5-GHz highly integrated receiver front-end

In this paper a radio front-end for a IEEE 802.11a and HIPERLAN2 sliding-IF receiver is presented. The circuit, implemented in a low-cost 46-GHz-f _T silicon bipolar process, includes a variable-gain low noise amplifier and a double-balanced mixer. Thanks to monolithic LC filters and on-chip single-ended-to-differential conversion of the RF signal, the proposed solution does not require the expensive image rejection filter and an external input balun. The receiver front-end exhibits a 4.3-dB noise figure and a power gain of 21 dB, providing an image rejection ratio higher than 50 dB. By using a 1-bit gain control, it achieves an input 1-dB compression point of −11 dBm, while drawing only 22 mA from a 3-V supply voltage.     

Low-Power 2.4-GHz Transceiver With Passive RX Front-End and 400-mV Supply

An ultra low power 2.4-GHz transceiver targeting wireless sensor network applications is presented. The receiver front-end is fully passive, utilizing an integrated resonant matching network to achieve voltage gain and interface directly to a passive mixer. The receiver achieves a 7-dB noise figure and -7.5-dBm IIP3 while consuming 330 muW from a 400-mV supply. The binary FSK transmitter delivers 300 muW to a balanced 50-Omega load with 30% overall efficiency and 45% power amplifier (PA) efficiency. Performance of the receiver topology is analyzed and simple expressions for the gain and noise figure of both the passive mixer and matching network are derived. An analysis of passive mixer input impedance reveals the potential to reject interferers at the mixer input with characteristics similar to an extremely high-Q parallel LC filter centered at the switching frequency     

A Fully Integrated 60GHz Four Channel CMOS Receiver with 7GHz Ultra-Wide Bandwidth for IEEE 802.11ad Standard

In this paper, a fully integrated CMOS receiver frontend for high-speed short range wireless applications centering at 60GHz millimeter wave （mmW） band is designed and implemented in 90nm CMOS technology. The 60GHz receiver is designed based on the super-heterodyne architecture consisting of a low noise amplifier （LNA） with inter-stage peaking technique, a single- balanced RF mixer, an IF amplifier, and a double-balanced I/Q down-conversion IF mixer. The proposed 60GHz receiver frontend derives from the sliding-IF structure and is designed with 7GHz ultra-wide bandwidth around 60GHz, supporting four 2.16GHz receiving channels from IEEE 802.1lad standard for next generation high speed Wi- Fi applications. Measured results show that the entire receiver achieves a peak gain of 12dB and an input 1-dB compression point of -14.SdBm, with a noise figure of lower than 7dB, while consumes a total DC current of only 60mA from a 1.2V voltage supply.     

A 35-mW 3.6-mm/sup 2/ fully integrated 0.18-/spl mu/m CMOS GPS radio

A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network and one external reference for the synthesizer. The receiver downconverts the GPS L1 signal at 1575.42 MHz to an IF of 9.45 MHz. The complete front-end and frequency synthesizer section have been integrated: low noise amplifier, image rejection mixer, IF active filter, and the full phase-locked loop synthesizer, including voltage-controlled oscillator and loop filter. The front-end measured performances are 81-dB maximum gain, 5.3-dB noise figure, and >30-dB image rejection. The synthesizer features a phase noise of -95 dBc/Hz at 1-MHz offset and a total integrated phase noise of less than 7/spl deg/ rms in the 500-Hz-1.5-MHz band. The front-end and the synthesizer draw, respectively, 11 and 9 mA from a 1.8-V supply. The architecture of the front-end and synthesizer has been geared to high level of integration and reduction of silicon area at the lowest possible power consumption. Consequently, the one reported here is the smallest and most integrated CMOS GPS receiver reported so far.     

A 0.18-$muhbox m$CMOS Selective Receiver Front-End for UWB Applications

This paper addresses the problem of 5–6-GHz WLAN interferer rejection in a direct-conversion receiver front-end for multi-band orthogonal frequency division multiplexing (OFDM) ultra-wideband (UWB) applications. The IC, realized in a 0.18-$muhbox m$CMOS technology, comprises a single-ended voltage–voltage feedback low-noise amplifier (LNA) and a quadrature mixer. The LNA employs a double-peak single-notch network in the output load, amplifying UWB groups #1 and #3, while rejecting WLAN interferes in the 5–6-GHz frequency range. The mixer, based on a merged quadrature topology, also realizes a second-order low-pass filtering. Fabricated dies have been bonded on PCB for characterization. The front-end, drawing 10 mA from 1.8 V, achieves a 1-dB gain desensitization with a$-$6.5-dBm interferer power at 5.5 GHz. Other measured performances are 5.2-dB and 7.7-dB minimum and maximum noise figure (NF),$-$3.5-dBm minimum IIP3 and$+$34.5-dBm minimum in-band IIP2 and$+$21-dBm out-of-band IIP2.