SOI MOSFET器件X射线总剂量效应研究

研究了以10keV X射线为辐照源对注氧隔离(SIMOX)SOI MOSFET器件进行辐照的总剂量效应.采用ARACOR 10keV X射线对埋氧层加固样品与未加固的对比样品在开态和传输门态两种辐照偏置下进行辐照,分析了器件的特性曲线,并计算了SOI MOS器件前栅与寄生背栅晶体管辐照前后的阈值电压的漂移.实验结果表明,加固样品的抗辐射性能优越,且不同的辐照偏置对SOI MOSFET器件的辐照效应产生不同的影响.     

半导体器件抗辐射加固现状及其发展

对六种现有器件的抗辐照水平进行了简单的介绍，其中CMOS和CMOS／SOS器件具有较好的抗辐照能力，将被军用和空间电子系统广泛采用，特别CMOS器件是空间电子系统应用最理想器件。本文详细的介绍了具有很大发展前途的二种抗辐射加固器件－SOI和GaAS器件，它们的抗辐照能力将能完全满足军用电子系统对抗辐射加固愈来愈高的要求。     

GaAs 10 bit DAC的抗辐射设计和实验

通过分析砷化镓(GaAs)器件的电离辐射剂量率辐照机理和效应,结合电路结构,描述了砷化镓10 bit数模转换器(DAC)的电离辐射剂量率辐射效应、抗辐射设计和辐照实验。在电路设计上,10 bit DAC由两个5 bit DAC组成,通过芯片内部合成10 bit DAC,有效降低了芯片面积和制造工艺难度;通过分析电路的电离辐射剂量率辐射效应,针对敏感电路进行局部电路的抗辐射设计,提高电路抗辐射能力;结合实验条件和器件引线分布,设计合理的辐照实验方案,开发辐照实验电路板,进行辐照实验,获得科学的实验结果,验证电路的抗辐射能力。实验结果表明该数模转换器能够抗3×1011rad(Si)/s剂量率的瞬时辐照。     

总剂量辐照效应模型在TDI-CCD器件中的应用

介绍了抗辐射加固设计使用的总剂量辐照效应模型,研究了它在时间延迟积分电荷耦合器件(TDI-CCD)电荷转移效率参数衰减中的应用,并通过不同剂量60Coγ辐照试验,验证了该模型在TDI-CCD器件抗辐射加固设计中的应用价值。     

6H－SiC MOS结构电特性及其辐照效应的研究

对SiC MOS结构辐照引起的电参数退化及其电特性进行了研究。结果说明:在氧化层电场较高时Fowler-Nordheim隧穿电流决定着SiC MOS结构的漏电流,当幅照栅偏压为高的正电压时,电离幅照对SiC MOS电容的影响会更明显,SiC MOS器件比Si器件具有好的抗辐照的能力,在58kGy(Si)的辐照剂量下,其平带电压漂移不超过2V。     

ONO反熔丝器件可编程特性研究

ONO(Oxide-Nitride-Oxide)反熔丝器件具有可靠性高、抗辐射、高开关比等优异特性,一直用于抗辐射可编程逻辑器件.基于0.6 μm CMOS工艺,分别采用"AF+MOS"和"MOS+AF"集成方法成功制备了ONO反熔丝器件,研究了ONO反熔丝阵列单元编程特性、导通电阻与编程电流以及编程时间之间的关系,同...     

基于LabView的SiO2抗辐射能力无损评价系统

基于MOS器件中SiO2介质材料噪声灵敏表征技术,提出了SiO2介质材料抗辐射能力无损评价方法。结合噪声测试的经验及该模型为理论分析要求,使用LabView平台开发SiO2介质材料抗辐射无损评价系统。本系统由数据采集和数据分析两个部分组成,数据采集部分主要负责噪声时间序列与频谱的采集与保存,数据分析部分的主要功能为时间序和频谱的特征值分析及SiO2介质材料抗辐射能力分析与相应器件的筛选。实验结果表明,软件性能可靠,对MOSFETT抗辐射能力的评价准确。     

先进工艺对MOS器件总剂量辐射效应的影响

器件栅氧厚度的减小、场氧工艺的改变以及衬底材料的不同等都将导致MOS器件的总剂量辐射效应发生改变.亚阈斜率、阈值电压漂移、衬底技术和场氧抗辐射能力已经成为器件按比例缩小给器件带来冲击的最主要的四个方面.综述了上述条件、高k介质/硅系统以及选择SOI材料作为衬底材料对MOS器件总剂量辐射效应的影响.     

回字形抗辐射环栅LDMOS建模与验证

介绍了一种回字形抗辐射环栅LDMOS器件。分析了该器件在版图绘制中的结构优势,并结合Sentaurus仿真结果,通过区域划分和类MOS结构拟合阈值电压,给出了该器件的等效宽长比模型和饱和电流模型。在标准商用0.18 μm BCD工艺下流片,测试结果表明,理论模型在一定栅压范围内误差可低于10%。在总剂量测试中,关态泄漏电流随剂量增加变化较小,有一定的抗辐射加固能力。     

抗辐射加固CMOS基准设计

研究了基于0.5 μm互补金属氧化物半导体(CMOS)工艺的动态阈值MOS(DTMOS)晶体管的电流-电压特性曲线。与常规CMOS工艺PNP晶体管特性对比,得到了带隙电压基准电路设计准则;采用DTMOS和抗辐射设计加固技术,完成了抗辐射加固CMOS基准设计。辐照试验结果表明,设计的抗辐射加固CMOS基准的抗总剂量能力达到了300 krad(Si)。     

Delay analysis of series-connected MOSFET circuits

In order to derive analytical delay expressions for CMOS gates in the submicrometer region, a realistic MOS model which incorporates an nth power law MOS model is developed. Closed-form delay formulas are obtained for CMOS inverters and series-connected MOSFET structures (SCMSs) that include short-channel effects. It is shown that the ratio of the delay of NAND/NOR to the delay of the inverter becomes smaller in the submicrometer region, because the V_DS and V_GS of each MOSFET in the SCMS are smaller than those of an inverter MOSFET. The smaller voltages in turn mitigate and relax the severe carrier velocity saturation in miniaturized MOSFETs. The results of the analysis for submicrometer VLSI designs show that if the maximum number of series-connected MOSFETs is considered to be five in 2-μm designs, then the number can be increased to six or seven in the submicrometer circuit design. In typical cases in VLSI designs, the delay ratio for N-SCMS is much less than N². The delay dependence on input terminal position for SCMS structures is also described     

Analytic Model for Undoped Symmetric Double-Gate MOSFETs With Small Gate-Oxide-Thickness Asymmetry

In this paper, an analytic model for undoped symmetric double-gate MOSFETs with small gate-oxide-thickness asymmetry is presented by virtue of a perturbation approach. Various effects on the MOSFET performance caused by small asymmetric departure from the nominal gate oxide thickness due to process variations and uncertainties are studied. This analytic solution can be used in compact models for IC designs.     

Implant-free high-mobility flatband MOSFET: principles of operation

Principles of operation of implant-free enhancement-mode MOSFETs (flatband MOSFET) are discussed. Epitaxial-layer structures designed for use in implant-free enhancement-mode devices and employing a high-/spl kappa/ dielectric (/spl kappa//spl cong/20) and a strained InGaAs channel layer with a thickness of 10 nm have been manufactured on GaAs substrate. Proceeding from measured electron mobility /spl mu/ as a function of the sheet-carrier concentration, enhancement-mode design considerations, saturation current I/sub Dss/, and mobility requirements are discussed using two-dimensional device simulations. For the flatband MOSFET to compete successfully with other device designs, certain minimum channel mobilities are required. For RF applications, /spl mu/ should exceed 5000 cm/sup 2//Vs while high-performance MOSFETs for digital applications may require even higher mobility for optimum operation. Finally, measured data of first 1-/spl mu/m-GaAs-flatband enhancement-mode MOSFETs are presented; the saturation velocity of the InGaAs channel layer is derived; and measured I/sub Dss/ data are compared to the results obtained by simulations.     

Scaling merged single-device-well MOSFETs for very large scale integration

Single-Device-Well (SDW) MOSFETs are high density MOSFET structures based on merging two MOSFET devices; a surface channel device and a buried channel device sharing the same device well and the same gate. SDWs offer a potential device area saving of 50%. The merits of the merged SDW MOSFETs are further enhanced in a scaled down MOSFET VLSI technology. This is the subject of this paper.     

Ultrathin channel vertical DG MOSFET fabricated by using ion-bombardment-retarded etching

A vertical ultrathin channel formation process for a vertical type double-gate (DG) MOSFET is proposed. Si wet etching using an alkaline solution has newly been found to be significantly retarded by introducing ion bombardment damage. We have also found that the ion-bombardment-retarded etching (IBRE) is independent of ion species and the implanted impurities can easily be transferred to be the dopants for source and drain regions of MOSFETs. By utilizing the IBRE, vertical type DG MOSFETs with a 12-nm-thick vertical channel were fabricated successfully. The fabricated vertical DG MOSFETs clearly exhibit the unique advantage of DG MOSFETs, i.e., high improvement of short-channel effect immunity by reducing the channel thickness. Thanks to the ultrathin channel, very low subthreshold slopes of 69.8 mV/dec. for a p-channel and 71.6 mV/dec for an n-channel vertical DG MOSFET are successfully achieved with the gate length of 100 nm.     

功率MOSFET并联驱动特性分析

并联MOSFET非常适合于在低电压、大电流下工作.基于IRFS4227PBF功率MOSFET,分析和测试了在一定散热环境下MOSFET结温的收敛特性与漏极电流的关系,说明了MOSFET的实际电流容量受散热条件制约,并以此确定在额定电流下需要并联的个数.用PSPICE电路仿真论述了外围电路Q值和功率管参数等因素对并联驱动的动态均流特性的影响.在此基础上搭建实验平台,成功实现了8个MOSFET并联在高频状态下的稳定工作.     

MOSFET器件并联实验研究

采用图腾柱的驱动方式,设计了应用于IXYS公司的功率MOSFET器件DE375-102N12的驱动电路。单个开关在多脉冲下具有良好的脉冲一致性。以该功率MOSFET器件进行的6个并联实验说明,影响并联的MOSFET的动态均流的主要参数是放电回路中的回路电感和寄生电感,电路板的布局与布线对并联的功率MOSFET有很大的影响,良好的布局可以大大提高电路的性能。     

Suppression of short channel effects by full inversion in deep sub-micron gate SOI MOSFETs

Classical modeling of fully inverted SOI MOSFET (FI MOSFET) has been performed. In FI MOSFETs, the top Si layer is thinner than the thickness of the inversion layer at the conducting state and so the depleted region in the top Si layer is completely eliminated. It was found that the gate electric field induces carriers in the channel more effectively in FI MOSFET than in the fully depleted SOI MOSFETs (FD MOSFET), so that the short channel effects can be suppressed significantly.     

SiGe-channel n-MOSFET by germanium implantation

The first n-SiGe-channel MOSFETs fabricated using high-dose germanium implantation and solid-phase epitaxy are reported. The polysilicon-gate MOSFETs were fabricated in the same chip in which conventional polysilicon-gate n-MOSFETs were made and their electrical characteristics are compared. The SiGe-channel MOSFETs show some significantly better electrical characteristics as compared to the silicon-channel MOSFETs. For example, the SiGe MOSFETs show higher drain conductance in the triode region and higher transconductance overall. The threshold voltage of the SiGe MOSFET appears to be smaller and the carrier mobility in the channel appears to be higher     

Ring oscillators for CMOS process tuning and variability control

Test structures utilizing ring oscillators to monitor MOSFET ac characteristics for digital CMOS circuit applications are described. The measurements provide information on the average behavior of sets of a few hundred MOSFETs under high speed switching conditions. The design of the ring oscillators is specifically tailored for process centering and monitoring of variability in circuit performance in the manufacturing line as well as in the product. The delay sensitivity to key MOSFET parameter variations in a variety of ring oscillator designs is studied using a compact model for partially depleted silicon on insulator(PD-SOI) technology, but the analysis is equally valid for conventional bulk Si technology. Examples of hardware data illustrating the use of this methodology are taken primarily from experimental hardware in the 90-nm CMOS technology node in PD-SOI. The design and data analysis techniques described here allow very rapid investigation of the sources of variations in circuit delays.