集成电路ESD设计验证技术

传输线脉冲(TLP)测试是当前电路设计工程师研究ESD保护器件特性和进行ESD加固设计的有力工具.分析了ESD应力作用下MOSFET的工作原理,指出精确测试保护器件或电路在ESD大电流应力下的I-V特性曲线,提取特征参数,将有利于ESD加固设计的一次成功;通过对典型TLP测试波形的分析,将TLP试验与器件的大电流响应建立联系;最后对扩散电阻和nMOSFET的TLP典型I-V特性进行了分析,并给出了实际的设计参数.     

探索用端口Ⅰ-Ⅴ特性对CMOS电路的静电放电(ESD)潜在损伤进行分析诊断

探索用端口Ⅰ一Ⅴ特性对CMOS电路的ESD潜在损伤进行分析诊断,给出受ESD潜在损伤电路端口特性变化的一些特征,对用Ⅰ－Ⅴ特性变化表征潜在损伤器件的条件和局限性进行了讨论。     

GaAs基大功率激光器静电失效现象的研究

为了判别大功率半导体激光器是否为静电损毁失效,对大功率半导体激光器进行了静电损毁机制的研究。通过测量和表征大功率半导体激光器静电损毁现象,为判别其失效提供有效判据。首先,对GaAs基980 nm大功率半导体激光器(HPLD)分别施加了-200 V,-600 V,-800 V,-1200 V以及+5000 V的静电打击(ESD),每次打击后,测量样品电学参数和光学参数。其次,对打击后的器件进行腐蚀并显微观察其打击后损伤现象。反相ESD后,半导体激光器I-V曲线有明显的软击穿现象,在反向4 V电压下反向1200 V静电打击后漏电为打击的5883854.92倍。正向5000 V静电打击后器件没有明显的软击穿现象,且功率下降很小。在反向ESD后器件腐蚀金电极后表面有明显熔毁现象,正向静电打击后则没有此现象。通过正向静电打击和反向静电打击下器件反应的不同I-V特性和损伤表征,推测正向瞬时大电压大电流下,器件的I-V特性无明显变化,而反向大电压大电流打击会导致I-V曲线出现明显软击穿,功率下降和表面熔毁现象,为判别静电损毁提出了有效判据。     

InGaP异质结双极晶体管ESD特性研究

研究了高速射频集成电路(RF IC)中InGaP异质结双极晶体管(HBT)器件的特性.测试了单指发射极和双指发射极两种结构器件的大信号DC I-V特性及抗人体模型(HBM)静电放电(ESD)能力.结果表明,双指发射极器件比单指器件能传导更高密度的电流,并能抵抗高能量的ESD;两种器件的击穿特性相似.这些结果可以用来指导RF IC ESD保护电路的设计.     

结电容对光伏器件I-V特性测试的影响

I-V特性是表征光伏器件性能的重要指标,在用电压扫描方式对一些器件进行I-V测试时,会出现零偏压电流为正向电流的现象,本文通过分析结电容对光伏器件电流电压测试的影响,对这种现象进行了解释,根据对由IOOMΩ电阻和50pF电容搭建的并联电路进行的测量,得到测试系统电压变化速率为2.14V/s,从而推算出光伏器件结电容的大小近似为0.47pF.用电路仿真软件PSpice对该测试电路进行了仿真,得到的仿真结果与实验结果相符.     

用于双极电路ESD保护的SCR结构设计失效分析

针对目前双极电路的ESD保护需求,引入SCR结构对芯片进行双极电路ESD保护。通过一次流片测试,发现加入SCR结构的电路芯片失效,SCR结构的I-V特性曲线未达到要求。从设计问题和工艺偏差两方面入手,分析了失效原因,通过模拟仿真,验证了失效是因为在版图设计时为节省版图面积,将结构P阱中NEMIT扩散区域边上用来箝位的电极开孔去掉造成的,并非工艺偏差导致的。通过二次流片测试,验证了失效原因分析的正确性,SCR器件结构抗ESD电压大于6kV,很好地满足了设计要求。     

LED受ESD冲击前后性能的变化分析

对GaN基蓝光LED施加ESD冲击,比较LED在受到ESD冲击前后I-V特性曲线、-5 V反向漏电流以及光色电特性的变化发现在I-V特性曲线和-5 V反向漏电流有明显变化的情况下,LED的光色电特性没有明显变化。选择在受到ESD冲击后反向漏电流值为不同数量级的LED作为样品进行加速老化实验,比较样品在加速老化实验前后的I-V特性曲线、光色电特性等参数的变化。通过比较样品之间的光衰减速率,发现反向漏电流大于1 mA时,样品的光衰减明显加快。     

SCR的I-V曲线中二次崩溃对ESD性能的影响

介绍几种常见的静电放电（ESD）器件,阐述SCR在几种ESD器件中的优点,提出持续改进的SCR器件,比较改进SCR器件的原因和改进之后的效果。对比它和改进前器件的ESD测试数据,集中描述了I-V的二次崩溃曲线出现的原因及其对ESD性能的影响。结果表明,SCR的二次崩溃曲线对器件的ESD性能有着非常好的效果,它可以在面积相当的情况下,大大改进器件的ESD性能。     

基于TCAD的45 nm CMOS器件温度特性模拟

基于TCAD工具,在一定温度范围内,对45 nm器件的电特性与性能稳定性是否能保持进行了建模和模拟验证。通过TCAD工具建立工具流,在300~400 K温度下,实现对45 nm CMOS器件I-V特性的模拟,以观察器件在一定温度范围内的特性曲线。通过与工艺文件对比表明,在25 ℃~127 ℃范围内,45 nm CMOS器件的电特性能够保持一定的稳定性。     

基于电加热器断路故障测控装置的设计与应用

全自动包装机、制袋机等设备均需电加热器对塑料产品的进行封装,电加热器烧断（断路）是设备使用中最常见的故障。利用电流检测电路的感应电压,来判断电加热器是否工作正常,利用光电耦合器件来判断温度控制器正常通断,实现报警输出或主机控制。电加热器断路故障测控装置能够自动识别温度升高加热器自动断电和电加热器断路故障。经在包装机上试用,该装置的各项性能参数均满足包装设备及用户使用要求,符合包装机械设备的配套需要。     

ESD与短脉冲EOS失效的微观形态分析及验证

静电放电(ESD)和过电应力(EOS)是引起芯片现场失效的最主要原因,这两种相似的失效模式使得对它们的失效机理的判断十分困难,尤其是短EOS脉冲作用时间只有几毫秒,造成的损坏与ESD损坏很相似。因此,借助扫描电子显微镜(SEM)和聚焦离子束(FIB)等成像仪器以及芯片去层处理技术分析这两种失效机理的差别非常重要。通过实例分析这两种失效的机理及微观差别,从理论角度解释ESD和EOS的失效机理,分析这两种失效在发生背景、失效位置、损坏深度和失效路径方面的差异,同时对这两种失效进行模拟验证。这种通过失效微观形态进行研究的方法,可以实现失效机理的甄别,对于提高ESD防护等级和EOS防护能力有着重要的参考作用。     

A study of the mechanisms for ESD damage to reticles

Reticles were exposed to the fringing field from an electrode biased to a high voltage. The reticles in the study included reticles designed to benchmark the electrostatic damage (ESD) hazard of photobay and production reticles of a variety of feature sizes. It was found that without any electrical contact between the reticle and the electrode, reticle damage could be done. A wide bandwidth transient-electromagnetic interference (EMI) sensing antenna revealed that the reticle sparked when a voltage as low as 2000 V was applied to the electrode. The tests showed that the ESD threshold of reticles with smaller feature sizes was lower than for reticles with larger feature sizes. Reticles were scanned under optical and atomic force microscopes for reticle damage. It was found that when the voltage was ramped to 17 kV and returned to zero, damage to the reticle was observed. When a voltage of 7.5 kV was applied once, no damage was observed but when it was applied 100 times, reticle damage was observed. This study confirms that ESD damage is done to a reticle by charged objects in the vicinity of the reticle in contrast with the prevailing belief that reticle damage is done only by charge on reticles. The study also showed that reticles can be sufficiently damaged to cause printing errors due to the accumulated damage caused by repeated low level exposure to the fringing field of a charged object in the vicinity of the reticle     

Impact of ESD-induced soft drain junction damage on CMOS product lifetime

The impact of ESD-induced soft drain junction damage on product lifetime was investigated. Several thousand input-output (IO) pads of a 0.35 pm CMOS IC were stressed by ESD (electrostatic discharge) and subsequently subjected to bakes, ESD re-stress and high temperature operating life tests. While the ESD-induced soft drain junction damage appears to be stable versus temperature stress and ESD-re-stress, it results in early failures during accelerated operating life tests. These lifetest failures are caused by breakdown of the gate oxide which was left unbroken during the ESD stress that caused the ESD-induced soft drain junction damage. Thus, ESD-induced soft drain junction damage might cause a reliability risk (latent ESD failure). Consequently, it needs to be avoided by assuring a sufficient robustness of the IC against this ESD damage mechanism. A leakage current criterion of I VA is rather large to detect this kind of damage after ESD stress.     

多晶PIN二极管及二极管串作良好工艺兼容并可移植ESD保护器件的研究

作为静电保护保护器件,多晶PIN二极管具有良好工艺兼容性及可移植的优点。文章制作并展示了多晶PIN二极管的反向击穿电压、漏电流及电容特性,同时通过正向及反向传输线脉冲电流电压特性评估了其静电保护能力。另外为了经一部降低电容并控制反向崩溃及正向开启电压对多晶PIN二极管串进行了研究。最后对器件特性进行了分析讨论,阐明了器件参数对性能的影响。     

Electrostatic discharge directly to the chip surface, caused by automatic post-wafer processing

Up to now, ESD damage is understood to be induced via device pads and to be avoided by means of appropriate protection structures located at these pads. The ESD susceptibility is classified by means of standardized stress tests. This paper shows, that with increasing importance a variety of post-wafer manufacturing and packaging processes may create a new type of evident and latent ESD damage in the device. We define this phenomenon as ESD-from-outside-to-surface (ESDFOS), as charged handlers cause discharges directly from outside into the device surface. Classical ESD tests do not cover this mechanism. The paper describes the phenomenon, its root causes, and gives practical hints for analysis and prevention.     

电子元器件静电放电模型及适用范围浅析

静电损伤在电子元器件失效中一直是一个重要的失效模式,近几十年人们对电子元器件的抗静电损伤的研究中也建立了各种模拟实际环境的静电放电模型,本文将着重介绍最基本的三种针对电子元器件的静电模型的特征及静电敏感度划分.这三种基本静电模型是:人体放电模型、带电器件放电模型、机器放电模型.     

功率VDMOS器件ESD防护结构设计研究

随着半导体工艺的不断发展,器件的特征尺寸在不断缩小,栅氧化层也越来越薄,使得器件受到静电放电破坏的概率大大增加。为此,设计了一种用于保护功率器件栅氧化层的多晶硅背靠背齐纳二极管ESD防护结构。多晶硅背靠背齐纳二极管通过在栅氧化层上的多晶硅中不同区域进行不同掺杂实现。该结构与现有功率VDMOS制造工艺完全兼容,具有很强的鲁棒性。由于多晶硅与体硅分开,消除了衬底耦合噪声和寄生效应等,从而有效减小了漏电流。经流片测试验证,该ESD防护结构的HBM防护级别达8 kV以上。     

Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices

As technology feature size is reduced, ESD becomes the dominant failure mode due to lower gate oxide breakdown voltage. In this paper, the effectiveness of new gate and substrate triggering techniques has been investigated to lower the trigger voltage of the LVTSCR and MOSFET based ESD protection circuits using 2D simulations and HBM/TLP measurements. The simulation results show that the using these techniques reduces the ESD triggering voltage by 63 and 44% for MOSFET-based and LVTSCR-based ESD structures, respectively, under 2 kV HBM ESD stress. The effectiveness of proposed gate and substrate triggering techniques is also confirmed by the HBM and TLP measurements.     

一种新的ESD防护器件的多脉冲TLP仿真方法

 提出了一种新的集成电路ESD防护器件的TLP仿真方法,该方法类似于实际的TLP测量过程,在器件结构上施加一系列电流脉冲,获得相应的电压-时间曲线。分别截取每个电流脉冲及其电压响应70%~90%部分的平均值,取得的每一对电压和电流平均值作为I-V曲线上的一点,从而得到电流-电压特性曲线。在此基础上,不仅可得到触发电压V_t1和维持电压V_h,而且可以获取二次击穿电流I_t2。对LSCR的仿真结果表明仿真结果与测试结果符合的很好。     

Investigation on SCR-based ESD protection device for biomedical integrated circuits in a 0.18-μm CMOS process

In these decades, integrated circuits for biomedical electronics applications have been designed and implemented in CMOS technologies. In order to be safely used by human, all microelectronic products must meet the reliability specifications. Therefore, electrostatic discharge (ESD) must be taken into consideration. To protect the biomedical integrated circuits in CMOS technologies from ESD damage, a dual-directional silicon-controlled rectifier (DDSCR) device was presented in this work. Experimental results show that the DDSCR has the advantages of high ESD robustness, low leakage, large swing tolerance, and good latchup immunity. The DDSCR was suitable for ESD protection in biomedical integrated circuits.