硅-硅直接键合后硅片的机械减薄过程北大核心

硅-硅直接键合硅片的机械减薄工艺对器件的性能有很大的影响。采用磨削、化学腐蚀和机械/化学抛光的方法对硅-硅直接键合硅片进行减薄加工,分析了减薄过程中各个工序键合片的平整度、弯曲度和翘曲度变化,并对减薄后硅片的厚度均匀性进行了考察。本次实验最终获得了几何参数良好、厚度满足要求且均匀的晶片。磨削过程会使弯曲度和翘曲度升高,可以通过化学腐蚀的方法降低弯曲度和翘曲度,化学腐蚀过程虽然使平整度升高,但可以通过机械/化学抛光的方法降低平整度。采用该减薄技术对直接键合硅片进行机械减薄具有可行性。     

InP单晶片翘曲度控制技术研究

InP单晶片受热场及机械损伤的作用而产生翘曲形变,这种形变在外延过程中会产生滑移线,也会影响外延层厚度均匀性,最终影响外延质量,因此必须采取措施对InP衬底的翘曲度加以控制.切割工艺是影响晶片翘曲度的关键,但受InP单晶特性及切割工艺自身的限制,InP切片的翘曲度仍保持在一个较高的水平,不能满足高质量外延的要求,需要采取措施进一步降低翘曲度.讨论了用化学腐蚀方法降低InP单晶切片翘曲度,研究了化学腐蚀液的组分、温度及腐蚀去除量对InP单晶片翘曲度的影响,综合工艺的稳定性和实际操作的便利性及晶片翘曲度的实际测试结果,确定了降低InP单晶片翘曲度的适宜工艺.     

硅片翘曲对光刻条宽均匀性的分析

本文通过对硅片翘曲情况及AZ603—14cp正性光刻胶的测试,在步进光刻机的聚焦曝光原理基础上分析了硅片翘曲对条宽均匀性的影响。从而得到了在集成电路,尤其是小尺寸集成电路的制造中硅片平整度的重要性。     

硅片翘曲对光刻条宽均匀性的分析

通过对硅片翘曲情况及AZ603-14cp正性光刻胶的测试,在步进光刻机的聚焦曝光原理基础上分析了硅片翘曲对条宽均匀性的影响.从而得到了在集成电路,尤其是小尺寸集成电路的制造中硅片平整度的重要性.     

硅片背面减薄技术研究

硅片背面磨削减薄工艺中,机械磨削使硅片背面产生损伤,导致表面粗糙,且发生翘曲变形.分别采用粗磨、精磨、精磨后抛光和精磨后湿法腐蚀等四种不同背面减薄方法对15.24cm(6英寸)硅片进行了背面减薄,采用扫描电子显微镜对减薄后的硅片表面和截面形貌进行了表征,用原子力显微镜测试了硅片表面的粗糙度,用翘曲度测试仪测试了硅片的翘曲度.结果表明,经过粗磨与精磨后的硅片存在机械损伤,表面粗糙且翘曲度大,粗糙度分别为0.15和0.016 μm,翘曲度分别为147和109 μm;经过抛光和湿法腐蚀后的样品无表面损伤,粗糙度均小于0.01 μm,硅片翘曲度低于60 μm.     

InP晶圆背面减薄工艺中翘曲度的控制与矫正

背面减薄是制备InP基光电子芯片的一道重要工艺。晶圆被减薄后失去结构支撑,会因应力作用产生剧烈形变,翘曲度大幅提高。严重的翘曲会使芯片可靠性降低甚至失效,应对晶圆的翘曲度进行控制和矫正。文章从“损伤层-翘曲度”理论出发,实验研究了晶圆厚度、粘片方式、研磨压力、磨盘转速、磨料粒径对翘曲度的影响。根据试验结果优化工艺参量,优化后晶圆的翘曲度降低了约20%;再通过湿法腐蚀去除损伤层,矫正已产生的翘曲,使晶圆的翘曲度降低约90%。优化减薄工艺降低损伤应力与湿法腐蚀去除损伤层分别是控制和矫正晶圆翘曲度的适用方法,可使翘曲度下降至之前的10%以内。     

光刻工艺对大面阵长波碲镉汞芯片性能的影响

通过分析器件工艺对大面阵长波碲镉汞芯片性能的影响,发现光刻工艺非均匀性累积进而显著影响碲镉汞芯片性能的现象.应用Matlab仿真计算,定量分析了碲镉汞材料片表面凸点对不同线宽光刻工艺非均匀性的影响,提出了降低光刻工艺非均匀性累积的方法和高质量光刻工艺对碲镉汞材料平坦度的具体要求.     

离子注入机失效检测新方法

随着器件线宽和层厚的缩小，离子注入计量设备对硅片上杂质分布均匀性进行直接监测的能力已经开始受到限制。同时，特征尺寸的缩小和参数性能的要求，使关键注入参数的工艺窗口不断变窄，而离子束电流和硅片尺寸却在不断增大。这样一来，就使得通过测量平均偏差与标准偏差（SD，或分布展宽）来量化硅片上注入掺杂均匀性的传统方法，缺乏所需的统计信息来监测离子注入工艺。     

不同生产工艺对硅片表面翘曲及机械性能的影响

单晶硅片是集成电路制造过程中最常用的衬底材料。硅片的表面质量及机械性能直接影响着器件的性能,成品率及寿命。不同加工工艺生产硅片高温弯曲强度的实验结果表明,众多因素对抗弯强度和高温弯曲度的影响规律是一致的。高温翘曲度与抗弯强度有着内在联系。抗弯强度不仅表示硅片在常温下的抗破碎能力,而且也反应了高温抗翘曲和弯曲能力。     

高温工艺中硅片的翘曲

通过硅片高温热处理实验研究了热自理工艺和表面状态对硅片高温弯曲度变化的影响，高温工艺中坚直装片引起的形变较小，研磨硅片经过适当化学腐蚀可明显降低高温翘曲。     

Across Wafer Critical Dimension Uniformity Enhancement Through Lithography and Etch Process Sequence: Concept, Approach, Modeling, and Experiment

Across-wafer gate critical dimension (CD) uniformity impacts chip-to-chip performance variation vis-a-vis speed and power. Performance specification for across-wafer CD uniformity has become increasingly stringent as linewidth decreases to 90 nm and below. This paper presents a novel approach to improve across-wafer gate CD uniformity through the lithography and etch process sequence. The proposed approach is to compensate for upstream and downstream systematic CD variation components in the litho-etch process sequence by optimizing across-wafer post exposure bake (PEB) temperature profiles. More precisely, we first construct a temperature-to-offset model that relates the PEB temperature profiles to the setpoint offsets of multi-zone PEB plates. A second model relating across-wafer CD to setpoint offsets of PEB plates is then identified from CD scanning electron microscope measurements. Post-develop and post-etch CD uniformity enhancement methodologies are then proposed based on the CD-to-offset model and temperature-to-offset models. The temperature-to-offset model is determined to be more appropriate for use in CD uniformity control due to its superior fidelity and portability as compared with the CD-to-offset model. We demonstrate that about 1-nm reduction in standard deviation of post-etch CD variation was achieved in the verification experiment, which validated the efficacy of proposed CD uniformity control approach.     

Thermal design of hot plate for 300-mm wafer heating in post-exposure bake

Temperature uniformity of a wafer during post-exposure bake (PEB) in lithography is an important factor in controlling critical dimension (CD) uniformity. In this study, a new hot plate system for the PEB of a 300-mm wafer was analyzed and designed. First, temperature deviation on the wafer caused by warpage was investigated, and the heater pattern of the multi-zone hot plate in the bake system was numerically analyzed. Then, a new heater pattern to enhance the temperature uniformity was proposed and tested experimentally. As a result, temperature uniformity within 0.087 °C on a 300-mm wafer was achieved.     

365 nm光刻照明系统中变焦系统的设计及公差分析

照明系统是投影光刻曝光光学系统的重要组成部分,它实现的功能是为掩模面提供高均匀性照明、控制曝光剂量以及不同照明模式。变焦系统作为光刻照明系统的重要组成部分,对提高整个光刻机的性能起着至关重要的作用。文中针对紫外光刻照明系统的特点,采用CODE V软件完成了波长365 nm,入瞳直径Φ33 mm,像方远心度≤10 mrad,畸变≤±2%近紫外光刻照明系统中变焦系统的设计,分析了变焦系统的误差源对系统光瞳性能的影响,结合变焦系统的设计方案和实际加工能力,给出单面厚度公差需小于20 μm,动件移动精度小于0.5 nm,各透镜偏心公差小于0.02 mm,各透镜倾斜公差控制在1′之内。制定公差合理、可行,满足了紫外光刻照明系统高均匀性、高能量利用率的要求。     

Nanoscale CMOS spacer FinFET for the terabit era

A spacer lithography process technology, which uses a sacrificial layer and spacer layer formed by chemical vapor deposition (CVD), has been developed. It has been applied to make a sub-40-nm Si-fin structure for a double-gate FinFET with conventional dry etching for the first time. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this spacer lithography technology yields better critical dimension uniformity than conventional optical or e-beam lithography and defines smaller features beyond the limit of current lithography technology. It also provides a doubling of feature density for a given lithography pitch, which increases current by a factor of two. To demonstrate this spacer lithography technology, Si-fin structures have been patterned for planar double-gate CMOS FinFET devices     

Feasible approach for processes integration of CMOS transistor gate/side-wall spacer patterning fabrication

As the gate length is scaling down, the spacer design for CMOS transistor becomes increasingly critical manufacturing process. In recent CMOS technologies, side-wall spacers play an important role in the control of short channel effects by offsetting ion implantation profiles from the edge of the gate. The present approach to overcome these fabrication limitations. The spacer patterning technology yields critical dimension variations of minimum-sized features which are much smaller than achieved by optical integrated lithography and etching processes. Generally relates to semiconductor manufacturing, and more particularly to nanotechnology fabrication feasibility for CMOS wafer process on gate spacer technology manufacture feasibility. A modified side-wall spacer patterning method was implemented for using conventional lithography and etching processing technology. Based on the systematical investigation of the effects of the various etch conditions on etching profile and their impacts on the sidewall transistor gate structure, a novel integrated process for well controlled side-wall spacer formation was developed for fabrication.     

Submicrometer CMOS device fabrication using an X-ray stepper

CMOS devices with submicrometer minimum features have been fabricated using X-ray/photo hybrid lithography. The device fabrication process utilized thirteen lithography steps, including four X-ray lithography levels, such as local oxidation of silicon (LOCOS) [1], gate, contact, and wiring, that required the most critical dimension control and alignment accuracy. A step and repeat exposure system and a SiNxmembrane mask were used for the X-ray lithography process. The SiNxmembrane mask was improved in its flatness and effective contrast by employing a stress compensating structure and a secondary electron trapping film. As a result, CMOS devices with 0.4-µm effective channel length were fabricated using a single-layer resist process.     

Reactor characterization for a process to etchSi3N4 formed on thin SiO2

A plasma etching process for patterning LPCVD (low-pressure chemical vapor deposition) Si₃N₄ which has been formed on thin thermally grown SiO₂ has been developed and characterized with an Applied Materials 8110 batch system using 100-mm-diameter silicon wafers. To fulfill the primary process objectives of minimal critical dimension (CD) loss (~0.08 μm), vertical profiles after etch, retention of some of the underlying thermal SiO₂, and batch etch uniformity, the reactor has been characterized by evaluating the effects of variation of reactor pressure (15 to 65 mTorr), O₂ concentration by flow rate (30 to 70%) of an O₂/CHF₂ mixture, and DC bias voltage (-200 to -550 V). Analysis of the resulting etch rate, etch uniformity, dimensional, and profile data suggests that satisfactory processing may be achieved at low reactor pressure (~25 mTorr), 50-60% O₂ by flow rate in O₂/CHF₃, and low DC bias (-200 to -250 V)     

Direct Transcription of Two‐Dimensional Colloidal Crystal Arrays into Three‐Dimensional Photonic Crystals

A simple protocol for the fabrication of three‐dimensional (3D) photonic crystals in silicon is presented. Surface structuring by nanosphere lithography is merged with a novel silicon etching method to fabricate ordered 3D architectures. The SPRIE method, sequential passivation reactive ion etching, is a one‐step processing protocol relying on sequential passivation and reactive ion etching reactions using C₄F₈ and SF₆ plasma chemistries. The diffusion of fresh reactants and etch product species inside the etched channels is found to play an important role affecting the structural uniformity of the designed structures and the etch rate drift is corrected by adjusting the reaction times. High quality photonic crystals are thus obtained by adding the third dimension to the two‐dimensional (2D) colloidal crystal assemblies through SPRIE. Careful adjustments of both mask design and lateral etch extent balance allow the implementation of even more complex functionalities including photonic crystal slabs and precise defect engineering. 3D photonic crystal lattices exhibiting optical stop‐bands in the infrared spectral region are demonstrated, proving the potential of SPRIE for fast, simple, and large‐scale fabrication of photonic structures.     

变温LPCVD沉积氮化硅薄膜的均匀性优化

以低压化学气相沉积(LPCVD)热壁立式炉为实验平台,由二氯硅烷和氨通过LPCVD工艺合成氮化硅薄膜,利用降温成膜提高氮化硅薄膜的膜厚均匀度.基于气体碰撞理论建立了氮化硅薄膜沉积速率与反应气体浓度的关系式.分析比较了LPCVD炉内不同升温速率沉积氮化硅薄膜的表面性能.发现在变温沉积阶段,选择合适的降温速率是实现薄膜沉积...     

变像管扫描相机扫描速度及非线性的标定技术

变像管扫描相机在超快物理过程的研究中具有广泛的应用。扫描速度及其非线性作为相机的主要技术指标之一,其准确度对实验结果有着重要影响。为了准确获取数据,确保实验结果的可靠性,采用皮秒光脉冲源、标准具及精密延时器,对高速变象管相机扫描速度和扫描速度非线性进行了实验标定,取得了较好的扫描速度非线性实验数据。结果表明,标定的变像管扫描相机最大扫描速度非线性为±3.52%;标定结果最大相对误差为±1.4%。这一结果对有效提高实验数据处理和物理分析的可靠性是有很大帮助的。