牵引用3 300 V平面栅IGBT栅极台面结构研究

针对机车牵引用3 300 V/1 500 A IGBT功率模块,采用TCAD仿真工具研究了不同栅极结构对器件静态和动态参数的影响。当平面栅IGBT采用栅极台面结构且台面厚度逐渐降低时,器件的静态阻断电压提高,开关损耗降低,但是器件的开关时间增加;此外,关断时过快的dv/dt会引起栅极电压振荡,开启时过快的di/dt会引起很大的电流过冲,导致器件应用的可靠性降低。在机车牵引的应用环境下,IGBT的栅极结构参数需要从电学参数和可靠性两个方面进行折中设计。     

Active Voltage control of IGBTs for high power applications

The operation of an insulated gate bipolar transistor (IGBT) in its active region is a well established technique for withstanding short circuits and also for dv/dt control. In this paper, we exploit the active behavior of the IGBT, applying a voltage feedback loop to the IGBT to control its switching. It is shown that adding a bias to the demand reference waveform shifts the IGBT into the active region and permits wide bandwidth operation over most of the switching transient. The operation of the IGBT is reported in detail, making reference to a selection of experimental waveforms for 400-A, 1700-V capsule IGBTs. The implementation required for control of such large IGBT modules and capsule devices for high power applications is described and discussed. It is concluded that the active voltage control method allows the operation of high power IGBT circuits to be closely defined.     

Characterization of power electronics system interconnectparasitics using time domain reflectometry

The significance of interconnect parasitics of power electronics systems is their effects on power converters' electromagnetic interference (EMI)-related performances, such as voltage/current spikes, dv/dt, di/dt, conducted/radiated EMI noise, etc. In this paper, a time domain reflectometry (TDR) measurement-based modeling technique is described for characterizing interconnect parasitics in switching power converters. Experiments are conducted on power components of a prototype high-power inverter, including insulated gate bipolar transistor (IGBT) modules, busbar and bulk capacitors. It is shown that the interconnect inductance of the IGBT module can be extracted completely using TDR. It is also shown that the busbar equivalent circuit can be modeled as transmission line segments or L-C filter sections, and the bulk capacitor contains a significant equivalent series interconnect inductance     

Field-Line-Circuit Coupling Based Method for Predicting Radiated Electromagnetic Emission of IGBT-PMSM Drive System

Electric drive system with Insulated gate bipolar transistor (IGBT) power device is widely used in Electric vehicle (EV), which consists of inverter, cables and Permanent magnet synchronous motor (PMSM). Due to the fast switching in di/dt and dv/dt of IGBT device, the system produces serious radiated Electromagnetic interference (EMI) through the interconnection cables. Thus, modeling of EMI source, propagation path and load PMSM is the key to accurately evaluate the system's radiation level. In addition, the system's radiated EMI involves the integrated calculation of circuit, cable and electromagnetic field, which cannot be solved by using a single circuit or electromagnetic calculation method. Therefore, this paper develops an effective field-linecircuit coupling based method to investigate the radiated EMI problems for IGBT-PMSM drive system, which is validated by experimental measurement. Besides, the impact of power cable parameters on radiated EMI is discussed. The proposed approach has guiding significance for electromagnetic compatibility design of EV.     

Active gate voltage control of turn-on di/dt and turn-off dv/dt in insulated gate transistors

As the characteristics of insulated gate transistors [like metal-oxide-semiconductor field-effect transistors and insulated gate bipolar transistors (IGBTs)] have been constantly improving, their utilization in power converters operating at higher and higher frequencies has become more common. However, this, in turn, leads to fast current and voltage transitions that generate large amounts of electromagnetic interferences over wide frequency ranges. In this paper, a new active gate voltage control (AGVC) method is presented. It allows us to control the values of di/dt at turn-on and dv/dt at turn-off for insulated gate power transistors, by acting directly on the input gate voltage shape. In an elementary switching cell, it enables us to strongly reduce over-current generated by the reverse recovery of the free-wheeling diode at turn-on, and oscillations of the output voltage across the transistor at turn-off. In the following sections, the AGVC in open and closed-loop for IGBT is presented, and its performance is compared with that of a more conventional method, i.e., increasing the gate resistance. Robustness of the AGVC is estimated under variations of dc-voltage supply and transistor switched current.     

Multiple Slope Switching Waveform Approximation to Improve Conducted EMI Spectral Analysis of Power Converters

An improved and simplified electromagnetic interference (EMI) modeling method based on multiple slope approximation of device-switching transitions for EMI analysis of power converters is presented. The traditional noise source modeling method, which uses single slope for rise and fall transition, is studied, and the criteria for reasonable modeling in the frequency range is analyzed. The turn-on and turn-off dynamics are investigated by dividing the nonlinear transitions into several stages based on an insulated gate bipolar transistor (IGBT) behavior circuit model. Real device-switching voltage and current waveforms are approximated by piece-wise linear lines and modeled by multiple dv/dt and di/dt slopes. The predicted EMI spectra suggest that high-frequency EMI noise is modeled with an acceptable accuracy. The proposed method was verified experimentally for a dc-dc buck converter     

Experimental and numerical study of the emitter turn-off thyristor(ETO)

The emitter turn-off thyristor (ETO) is a new family of high power semiconductor devices that is suitable for megawatt power electronics application. ETOs with voltage and current ratings of 4-6 kV and 1-4 kA, have been developed and demonstrated. And those power levels are the highest in silicon power devices and are comparable to those of the gate turn-off thyristor (GTO). Compared to the conventional GTO, the ETO has much shorter storage time, voltage controlled turn-off capability, and much larger reverse biased safe operation area (RBSOA). Furthermore, ETOs have a forward-biased safe operation area (FBSOA) that enables it to control the turn-on di/dt similar to an insulated gate bipolar transistor (IGBT). These combined advantages make the ETO based power system simpler in terms of dv/dt snubber, di/dt snubber, overcurrent protection, resulting in significant savings in the system cost. This paper presents experimental and numerical results that demonstrate the advantages of the ETO     

Failures-tolerance and remedial strategies of a PWM multicell inverter

The aim of this paper is to explain the intrinsic short-circuit tolerance of an IGBT multicell inverter when a commutation failure occurs. Such a failure may either be a wrong gate voltage (malfunctioning of the driver board, auxiliary power supply failure, dv/dt disturbance) or an intrinsic IGBT failure (over-voltage/avalanche stress, temperature overshoot). IGBT stresses are studied and show that no opening of the bonding can appear and consequently no risk of explosion. That is why, owing to the imbricated cells structure, an IGBT short-circuit failure may be withstood for a few switching periods, with nevertheless nonoptimized output waveforms. The design, the lab-test of a sensor able to perform monitoring as well as the failure diagnosis are also presented. This real-time diagnosis allows either a safe stop or a remedial control strategy based on the reconfiguration of the PWM modulator. The reconfiguration strategy enables decrease of internal stresses and optimization of the output shape. A fail-safe operating may be gained for high power applications.     

DV/DT related spurious gate turn-on of bidirectional switches in a high-frequency cycloconverter

We identified a failure mode in a two stage dc/ac converter, comprising a high-frequency dc/ac inverter followed by an ac/ac cycloconverter, both operating at the same switching frequency. The failure-mode is a short-circuit condition, which is a combined effect of the reverse recovery of the MOSFET body diode and simultaneous spurious turn-on of the bidirectional switches of the cycloconverter, owing to a significantly high dv/dt (>2/spl times/10/sup 8/V/ns). A high dv/dt causes appreciable current to flow through the gate-to-drain (Miller) capacitance, thereby producing a significant amount of voltage drop across the external gate resistance. Consequently, the gate-to-source voltage of the power MOSFET may exceed the threshold voltage of the device, which turns the device on. We explain the mechanism for the dv/dt-related gate turn-on and present experimental results to validate the explanation. We also demonstrate, how a two-fold increase in the value of external gate resistance of the inverter switches (to reduce the dv/dt applied to the cycloconverter) reduces the periodicity of the short-circuit condition.     

dv/dt Noise canceling circuit in ultra-high-voltage MOS gate drivers

A novel small-sized voltage mode noise canceling circuit is introduced in order to remove the dv/dt noise in the ultra-high-voltage MOS gate drive IC more efficiently, accurately and steadily. The dv/dt noise is removed completely by the mutual controlling of the high-side voltage signal, which improves the incapability of the full removal of dv/dt noise by conventional noise remove circuit due to the mismatch in the high-side circuit. In addition, no additional circuit is introduced to the noise canceling circuit. Fabricated in 700 V 0.5 μm BCD with simulation tool HspiceD, the circuit shows good performances of a quiescent current less than 50 μA, and a full removal of 70 V/ns dv/dt noise by the noise elimination function block. Moreover, a mismatch rate ranging within ±100 % can also be fully eliminated, thus ensuring the stability and reliability of the ultra-high-voltage gate driver’s performance.     

An optically-coupled crosspoint array with high dv/dt capability and high gate sensitivity

A 2/spl times/4 optically-coupled economical crosspoint array for the telephone speech path with a high breakover voltage (>450 V), high dv/dt capability (>200 V/0.1 /spl mu/s), and high gate sensitivity (<5 mA) is described. This has been achieved by a new device structure with a double-gate MOSFET and RC discharge circuitry formed on a p-n-p-n element. This MOS associated circuitry for dv/dt improvement is referred to as `MAC' p-n-p-n elements with MAC can be separated from each other with a new simple isolation technique called `canal isolation' which facilitates low manufacturing cost. Both p-n-p-n elements and LEDs are bonded face-down on a 44 pin chip carrier ceramic package with bump electrodes which again allows low manufacturing cost. The MAC enables independent control of the dv/dt capability and the gate sensitivity. The authors show the MAC performance in dv/dt improvement and various evaluations of MAC, including computer simulation. High breakover voltage technology and some processes for forming the gate-to-cathode resistor R/SUB GK/ for devices with MAC are discussed. This new optically-coupled crosspoint array with MAC makes possible a high-performance direct interface with conventional telephone sets.     

Low-loss high-speed switching devices, 2300-V 150-A static induction thyristor

Focussing attention to the performance of high-speed high off-state voltage and large current provided in the buried-gate-type static induction (SI) thyristor, a 2300-V 150-A low-voltage-drop high-speed medium-power SI thyristor was developed. Irrespective of the magnitude of switching current, the SI thyristor has the characteristics of fast turn-on time and less on-gate current compared to that of the GTO thyristor. The characteristics of this SI thyristor obtained as the result of manufacturing this prototype were such that the forward blocking voltage was 2300 V at a gate reverse voltage of -5 V, the reverse blocking voltage was 2350 V, and the forward voltage drop was 1.4 V at an anode current of 150 A and 2.2 V at an anode current of 450 A. The switching characteristics were such that the turn-on time was 1.5 µs when an anode current IAof 150 A becomes ON, turnoff time was 2.5 µs at IA= 100 A and 3.6 µs at IA= 200 A. This SI thyristor is able to break the anode current of 1000 A at a gate current of 95 A. Performance exceeding 1100 A/µs was confirmed for the di/dt capability and even for dv/dt, and these normally can be operatable even at 100 times higher current compared with maximum average current.     

Progress in light activated power thyristors

Light activated power thyristors would have considerable advantages in intermediate- and high-voltage circuits, as power and trigger circuits could be electrically separated by use of glass fiber cables. Besides high-voltage capability, such devices must have turn-on delay times, dv/dt capabilities, and di/dt stabilities which are comparable to conventionally fired thyristors. The necessary trigger power, however, has to be kept low enough to enable firing with GaAs light emitters, which are available now or will be in the near future. The dv/dt sensitivity is an essential limitation for the reduction of the minimum necessary trigger power. Optimizing of the thyristor emitter shunts results in an already acceptable compromise, but much better results can be obtained by a gate structure which actively compensates dv/dt fault triggering. Our test devices show good turn-on behavior. A short survey on different GaAs-light sources and the coupling problem is given.     

Multilevel inverter by cascading industrial VSI

In this paper, the modularity concept applied to medium-voltage adjustable speed drives is addressed. First, the single-phase cascaded voltage-source inverter that uses series connection of insulated gate bipolar transistor (IGBT) H-bridge modules with isolated DC buses is presented. Next, a novel three-phase cascaded voltage-source inverter that uses three IGBT triphase inverter modules along with an output transformer to obtain a 3-p.u. multilevel output voltage is introduced. The system yields in high-quality multistep voltage with up to four levels and low dv/dt, balanced operation of the inverter modules, each supplying a third of the motor rated kVA. The concept of using cascaded inverters is further extended to a new modular motor-modular inverter system where the motor winding connections are reconnected into several three-phase groups, either six-lead or 12-lead connection according to the voltage level, each powered by a standard triphase IGBT inverter module. Thus, a high fault tolerance is being achieved and the output transformer requirement is eliminated. A staggered space-vector modulation technique applicable to three-phase cascaded voltage-source inverter topologies is also demonstrated. Both computer simulations and experimental tests demonstrate the feasibility of the systems.     

Power Converter EMI Analysis Including IGBT Nonlinear Switching Transient Model

It is well known that very high dv/dt and di/dt during the switching instant is the major high-frequency electromagnetic interference (EMI) source. This paper proposes an improved and simplified EMI-modeling method considering the insulated gate bipolar transistor switching-behavior model. The device turn-on and turn-off dynamics are investigated by dividing the nonlinear transition by several stages. The real device switching voltage and current are approximated by piecewise linear lines and expressed using multiple dv/dt and di/dt superposition. The derived EMI spectra suggest that the high-frequency noise is modeled with an acceptable accuracy. The proposed methodology is verified by experimental results using a dc-dc buck converter     

The di/dt capability of thyristors

This paper describes an experimental investigation of the di/dt failure mechanism of thyristors. The location of the initial turn-on region and the spread of the "on" region were observed on a specially designed thyristor having many monitoring electrodes. The turn-on process was studied for triggering by gate, by breakover, and by dv/dt. In many cases it was found that turn-on occurred at almost the same region, whether it was triggered by breakover or by dv/dt. This area coincided with the final holding position in the turn-off process. The di/dt capability of the thyristor was measured. It was found that the capabilities were almost the same for the three triggering methods. The destruction temperature in the di/dt test was estimated from the area of the burn-out spots and the energy dissipation.     

Leakage current variation during two different modes of electrical stressing in undoped hydrogenated n-channel polysilicon thin film transistors (TFTs)

Leakage current evolution during two different modes of electrical stressing in hydrogenated-undoped n-channel polysilicon thin film transistors (TFTs) is studied in this work. On-state bias stress (high drain bias and positive gate bias) and off-state bias stress (high drain bias and negative gate bias) were performed in order to study the degradation of the leakage current. It is found that during off-state bias stress the gate oxide is more severely damaged than the SiO₂-polySi interface. In contrast, during on-state bias stress, two different degradation mechanisms were detected which are analyzed.     

级联式Buck-Boost校正电路在高压电子镇流器中的应用

本文提出了一种带有无源无损缓冲结构的级联式buck-boost校正电路,并成功地应用在高压式电子镇流器中.缓冲电路通过抑制反向恢复电流所引起的di/dt和漏源极电压的dv/dt,有效地减少了开关损耗和EMI噪音.Buck电路中的IGBT实现零电流开通和零电压关断,同时续流二极管也工作在零电压状态.研制的380 V交流输入,400 V直流输出,额定功率600W的实验样机,其功率因数达0.98,THD小于11%.     

Decrease in on-state gate current of AlGaN/GaN HEMTs by recombination-enhanced defect reaction of generated hot carriers investigated by TCAD simulation

Changes in the on-state gate current of AlGaN/GaN high-electron-mobility transistors (HEMTs) under various electrical and thermal stress conditions have been analyzed by technology computer-aided design (TCAD) simulation. A larger gate current is observed under on-state bias condition than that under off-state bias condition. The TCAD simulation indicates that on-state gate current flows from the heated gate electrode to the AlGaN layer by tunneling or hopping through the gate depletion layer when we apply some deep-donor-type traps under the gate in the AlGaN barrier layer. The gate current is caused by electrons that flow and is pulled away by the applied gate-to-drain voltage under a high channel temperature condition. The deep traps benefit both the on- and off-state gate current behavior. We found that the on-state gate current is effectively decreased by electrical stress under the on-state condition. Electroluminescence measurement indicates that a large number of hot carriers are generated under this condition. The results suggest that the process-induced crystal defects are annealed out by non-radiative recombination of the generated hot carriers by a recombination-enhanced defect reaction mechanism. The change in the on-state gate current in the TCAD simulation can be successfully explained by the decrease in the donor traps.     

Noise Reduction in CMOS Circuits Through Switched Gate and Forward Substrate Bias

A new concept of noise reduction in CMOS circuits is presented taking advantage of a strong reduction of MOSFET low-frequency noise occurring under switched gate bias conditions and forward substrate bias. The effect of forward substrate bias on noise reduction is significantly larger in switched compared to constant gate bias conditions. Experimental results reveal that forward substrate bias is most effective when applied during the off-state of the transistor. A bias scheme adopting forward substrate bias only during the transistor off-state is suggested by the measurement results of transconductance efficiency ${rm gm}/{rm Id}$ and intrinsic voltage gain ${rm gm}/{rm gds}$ showing that these figures of merit are degraded when a forward substrate bias is applied during the on-state. As a first example exploiting the found noise reduction on circuit level, a 14 GHz pMOS VCO is presented. Our results show a significant reduction of close to carrier phase noise when a forward substrate bias is applied to the MOSFETs providing the negative conductance stage for the oscillation of the VCO. The outlined principles can be extended to other circuits and motivate new topologies and biasing schemes for analog and radio frequency CMOS circuits.