Study of unipolar pulsed ramp and combined ramped/constant voltage stress on mos gate oxides

MOS gate oxide capacitors over a wide range of oxide thicknesses (10.9–28 nm) were stressed using a unipolar pulsed voltage ramp and combined ramped/constant voltage stress measurements. The reliability measurements were performed with several different bias conditions in order to assess the effects of the measurement conditions on times to breakdown and breakdown fields. In the first part it was verified that the unipolar pulsed ramp yields breakdown distributions which are identical to those of a widely used staircase ramp. In the second part the unipolar pulsed ramp was used for pre-stress prior to a constant stress and measurement results were compared to those of a ramped/constant stress with a staircase ramp. In several cases a ramp prior to a constant stress increases time to breakdown. The observations made in this study imply that the time to breakdown of a constant stress in the Fowler-Nordheim tunneling regime is strongly dependent on charge trapping and, therefore, on the stressing history of the oxide. Finally, it is shown that the combined ramped/constant voltage stress is a valuable tool for monitoring extrinsic and intrinsic breakdown properties when applying stress parameters in the correct way.     

A new technique for determining long-term TDDB accelerationparameters of thin gate oxides

A new technique, the dual voltage versus time curve (V-t) integration technique, is presented as a much faster method to obtain time-dependent dielectric breakdown (TDDB) acceleration parameters (α and τ) of ultrathin gate oxides compared to conventional long-term constant voltage stress tests. The technique uses V-t curves measured during highly accelerated constant or ramped current injection breakdown tests. It is demonstrated that the technique yields acceleration parameters that are statistically identical to values obtained from long-term constant voltage TDDB tests. In contrast to traditional TDDB tests, the proposed technique requires over an order of magnitude less testing time, a smaller sample size, and can be used during production monitoring     

Ramped current stress for fast and reliable wafer level reliability monitoring of thin gate oxide reliability

A ramped dielectric stress measurement, suitable for fast wafer level reliability (fWLR) monitoring, is assessed for thin gate oxide thicknesses down to 2.2 nm. Severe difficulties usually occur for the reliable detection of soft/hard breakdown in a short time interval and due to high direct tunneling currents. These are discussed and an exponentially ramped current stress is introduced tackling the problems. Early oxide fails were covered by a fast voltage ramp carried out before the current ramp. The advantages of the method are highlighted which has already been implemented for fWLR monitoring in high volume production on scribe line structures.     

Series resistance effects in thin oxide capacitor evaluation

The effects of undesired series resistance in thin oxide capacitors are studied. Thin dielectric reliability is usually evaluated by means of accelerated tests (ramped or constant voltage or current stress). It is shown that the breakdown electric field can be highly overestimated due to the series resistance associated with the test structure: the larger the resistance, the bigger the error. Moreover, breakdown detection criteria in automatic test routines become more critical. It is also demonstrated that a nonuniform stress is applied to the dielectric whenever the series resistance is position-dependent, as it usually is. Erroneous breakdown-related defect distributions could be inferred as a consequence of neglecting the series resistance effect. It is therefore suggested that workers pay much attention to the test structure layout definition in order to minimize these problems     

Implications of a localised defect model for wafer level reliability measurements of thin dielectrics

In this paper a simple model of an oxide defect as a region of localised oxide thinning is used to explore the relationship between the most commonly used measurements of dielectric reliability. For each measurement it shows how the measured parameters depend on the area and effective thickness of the defect. The work shows that in constant voltage and ramped voltage stress the area and thickness of the defect may be easily separated in the measured parameters. However, in constant current and ramped current measurements all measured parameters are dependent on both area and thickness which makes the extraction of area and thickness more difficult. It is shown that, in order to be able to project from one measurement to any other, the defect area and thickness must be determined. In particular, if projections of charge to breakdown are required then the use of a model which only includes defect thinning as proposed by Lee et al, [1], is not sufficient.     

Tunnel barrier properties of stressed ferromagnetic tunneljunctions

The oxide breakdown properties of ultra-thin (-1 nm) naturally oxidised Al₂O₃ tunnel barriers in magnetic tunnel junctions were studied using ramped and constant stress experiments. During stress measurements at 1.35 V, a fast breakdown of the junction was observed. The time-to-breakdown is evaluated using Weibull statistics, as commonly utilised in SiO₂ reliability studies     

Hot carrier induced bipolar transistor degradation due to basedopant compensation by hydrogen: theory and experiment

New experimental and analytical results are presented which show that extrinsic and intrinsic base dopant compensation by hydrogen is responsible for large changes in the bipolar transistor parameters of emitter-base breakdown voltage (V_ebo), forward collector current (I_c) and series base resistance (R_bx) when such transistors are operated under avalanche and inverted mode stress conditions. A new physical model has been developed to explain the observed changes in V_ebo and I_c as a function of stress time, and the analytical results are shown to be well correlated with the experimental data. Lastly, the effects of degradation on transistor voltage gain bandwidth (f_max) and emitter coupled bipolar comparator delay (τ_delay) are assessed and discussed in terms of circuit performance degradation     

Dielectric breakdown distributions for void containing silicon substrates

Distributions of gate oxide failure in various types of silicon substrate materials have been investigated for a wide range of oxide thicknesses. Silicon substrates containing various well-characterized void distributions along with defect-free materials were tested using special low-series resistance capacitor structures. Results of both ramped field tests of variable ramp rate and constant field tests were performed and analyzed within the framework of Weibull statistics. Ramped field tests are not “time zero dielectric breakdown” tests as is commonly asserted. They can in fact be very useful in extrapolating time dependent failure. The same set of Weibull parameters can be used to describe both ramped field and constant field wearout tests if an appropriate model for the time dependent damage accumulation during the field ramp is used. There are implications for reliability predication and the burn-in screening of device populations containing such defects.     

Recess dependent breakdown behavior of GaAs-HFETs

GaAs based HEMT devices were fabricated with a constant recess towards the source, whereas the recess width towards the drain was varied. While the off-state breakdown voltage has been improved by the use of a wide recess towards the drain, no dependence of the on-state breakdown on the recess configuration was observed. The constant breakdown voltage in the on-state is analysed by the feedback parameters obtained from an extraction of the small signal equivalent circuit. Although the extrinsic gate drain capacitance could be reduced by the use of a wider recess configuration, it is assumed that the intrinsic drift region is independent of the recess configuration     

Dielectric thinning model applied to metal insulator metal capacitors with Al2O3 dielectric

The extrinsic fails of metal insulator metal capacitors (MIMCAPs) with Al₂O₃ dielectric are modeled by a thinning model that is based on the intrinsic reliability model and the assumption that the extrinsic fails behave like an intrinsic dielectric with a reduced thickness. The intrinsic reliability model is developed from voltage acceleration experiments at four temperatures and four dielectric thicknesses. Voltage and thickness dependence of the logarithm of the intrinsic lifetime scales with the electric field and the temperature dependence is described by an Arrhenius factor. The voltage acceleration is not temperature dependent. The thinning model is shown to consistently describe acceleration experiments with random extrinsic fails of unknown root cause at low defect density (0.1 cm⁻²) as well as a systematic extrinsic failure mechanism caused by process induced plasma damage. It is also shown that the random extrinsic fails that were investigated on large area teststructures can be extrapolated to much smaller product typical capacitors. A criteria based on the stored energy is derived that allows to decide, whether an extrinsic fail will cause product failure. These results allow a quantitative prediction of early product fails due to the MIMCAP.     

Low Weibull slope of breakdown distributions in high-k layers

The reliability of various Al₂O₃, ZrO₂ and Al₂O₃/ZrO₂ double layers with a physical oxide thickness from 3 nm to 15 nm and TiN gate electrodes was studied by measuring time-to-breakdown using gate injection and constant voltage stress. The extracted Weibull slope β of the breakdown distribution is found to be below 2 and shows no obvious thickness dependence. These findings deviate from previous results on intrinsic breakdown in SiO₂, where a strong thickness dependence was explained by the percolation model. Although promising performance on devices with high-k layers as dielectric can be obtained, it is argued that gate oxide reliability is likely limited by extrinsic factors     

Pre-breakdown noise in electrically stressed thin SiO2 layers of MOS devices observed with C-AFM

A conductive atomic force microscope (C-AFM) has been used to analyse the degradation stage (before breakdown, BD) of ultrathin (<6 nm) films of SiO₂ at a nanometer scale. Working on bare gate oxides, the conductive tip of the C-AFM allows the electrical characterization of nanometric areas. Due to the extremely small size of the analysed areas, several features, which can be masked by the current that flows through the overall test structure during standard electrical tests, are observed. In particular, switching between different conduction states and sudden changes of conductivity have been measured during ramped voltage tests, which have been related to the trapping and detrapping of single electronic charges in the defects generated during the electrical stress. This phenomenon, which has been observed during constant voltage stresses in the form of random telegraph signals, has been associated to the pre-breakdown noise measured in poly-gated structures. The C-AFM has also allowed to directly measure the I–V characteristics of the fluctuating spot.     

Estimating effective dielectric thickness for capacitors with extrinsic defects by a statistical method

Simulated capacitor breakdown voltage data are fit to a mixture of two Weibull distributions using the method of maximum likelihood. The dielectric thickness of extrinsic capacitors is estimated as a part of a mixture distribution, allowing simultaneous prediction of failure times using both intrinsic and extrinsic failures. Confidence intervals on the reliability parameters and the 10 year FIT rate at 5 V are successfully estimated using the delta method. The same approach is applied to a real data set with similar results.     

Statistical nature of hard breakdown recovery in high-κ dielectric stacks studied using ramped voltage stress

In replacing the conventional SiO₂ gate dielectric with high-κ materials, new challenges emerge on understanding the kinetics of dielectric breakdown due to the different properties of the new bulk oxide and the interfacial layers at the substrate and gate electrode interface as well. Among several complexities, dielectric relaxation and recovery have received a lot of attention due to their promising applications in resistive random access memory (RRAM). In this study, we explore the stochastic nature of hard breakdown recovery in HfO₂, taking advantage of ramped voltage stress (RVS) measurements, which are theoretically equivalent to the widely used constant voltage stress (CVS), while being significantly less time-consuming. We found that the possibility of recovery is largely dependent on the ramp rate during RVS as the dielectric needs adequate time and sufficient thermal budget to recover. The clustering model is found to be a good fit to the RVS data sets for post-recovery subsequent breakdown events and the extent of defect clustering is found to be more intense after increasing number of recovery events. The breakdown mechanism in the stack is confirmed by measuring the resistance change trends with temperature.     

An introduction to fast wafer level reliability monitoring for integrated circuit mass production

The continuous verification of process reliability is essential to semiconductor manufacturing. The tool that accomplishes this task in the required short time is the fast wafer level reliability monitoring (fWLR). The basic approaches for this task are described in this introductory overview. It summarizes sampling plans, discusses the feasibility of using fWLR for screening and describes the data assessment and application of control cards. Beyond these general topics many of the fWLR stress methods are described in detail: Dielectric stressing by means of an exponential current ramp is compared to ramped voltage stress. Especially for thin oxides the methods differ regarding the soft breakdown detection and the time they consume. Another task of fWLR is the detection of plasma induced damage, which can be achieved by applying a revealing stress to MOSFETs with antenna. The design challenges of the structures and the test method as well as the data assessment are described in detail. An important section deals with fWLR for interconnects. In this section the appropriate test structures (including thermal simulations) are illustrated and fast electromigration stresses are discussed and the details of standard wafer level electromigration accelerated test (SWEAT) are included. For contacts and vias a simple method to check reliability is presented. Finally the monitoring of device reliability is treated. It is shown that using indirect parameters that correlate well to standard parameters such as the drain current can be beneficial for fWLR. For both, the interconnects and the devices, it is essential to have locally heated test structures in order to keep the stress time low. The detection and verification of mobile ions can also be performed with such a self-heated structure. For the described methods examples are given to illustrate the usefulness.     

A new and flexible scheme for hot-electron programming ofnonvolatile memory cells

A new hot electron writing scheme for flash EEPROMs is proposed that combines a positive source to bulk voltage and a ramped voltage on the control gate. The scheme exploits the equilibrium between hot electron injection and displacement current at the floating gate electrode in order to achieve a transient regime where the drain current of the cell is virtually constant. The new method allows one to accurately control the threshold voltage and the programming drain current that is essentially determined by the slope of the control gate ramp and can thus be traded off with programming time over a wide range of values. The main features of the new scheme are experimentally demonstrated on up-to-date 0.6 μm stacked gate flash EEPROM devices     

Reliability of erasing operation in NOR-Flash memories

The erase operation in NOR-Flash memories intrinsically gives rise to a wide threshold voltage distribution causing various reliability issues: read margin reduction; increase of total bitline leakage current and electrical stress during reading and programming. This paper will address and review the erasing operation by analyzing the causes, the reliability issues and the possible solutions of the erased threshold voltage distribution width, the presence of ultrafast bits, the erratic erase phenomenon, the presence of a significant tail (extrinsic behavior) in the erased distribution and the intrinsic oxide degradation during cycling (oxide aging).     

Electrical reliability aspects of through the gate implanted MOS structures with thin oxides

The effect of through the gate implantation (TGI) on MOS devices with oxide thicknesses of 3.3, 4.0, and 20 nm is studied, utilizing constant voltage stress tests and a substrate hot electron (SHE) injection technique. For 3.3 and 4.0 nm thick oxides, a dependence of time to breakdown on TGI dose is detected which, for 3.3 nm samples, diminishes with increasing test voltage. SHE injection measurements show a TGI induced increase in intrinsic electron trap density and also an increase in trap generation rate during sample stressing. A change of electron trap generation dynamics seems to be the main cause for oxide weakening due to TGI.     

Power factor preregulators with improved dynamic response

An improved control strategy of standard power factor preregulators (PFPs) is proposed which allows fast output voltage response while maintaining a high power factor. This is obtained by compensating for the intrinsic low-frequency output voltage ripple, thus allowing a higher bandwidth of the output voltage control loop. This method does not require additional sensing, but only a multiplier and simple analog circuitry, and works well with a universal input voltage range. Experimental tests on a boost power converter with average current control confirm the validity of the approach     

A new gate current extraction technique for measurement of on-statebreakdown voltage in HEMTs

We present a new simple three-terminal technique for measuring the on-state breakdown voltage in HEMTs. The gate current extraction technique involves grounding the source, and extracting a constant current from the gate. The drain current is then ramped from the off-state to the on-state, and the locus of drain voltage is measured. This locus of drain current versus drain voltage provides a simple, unambiguous definition of the on-state breakdown voltage which is consistent with the accepted definition of off-state breakdown. The technique is relatively safe and repeatable so that temperature dependent measurements of on-state breakdown can be carried out. This helps illuminate the physics of both off-state and on-state breakdown