Newly structured expandable 52-Mbit/s, 48-channel time-division switching LSI with 2.4 Gbit/s throughput

An expandable Si bipolar 2.4 Gbit/s throughput, 52 Mbit/s 48-channel time-division switching LSI system is described. A high-throughput of 2.4 Gbit/s and a power-dissipation of 5.3 W are achieved by adopting a low-voltage swing four-serial-gated differential bipolar circuit design and super self-aligned process (SST-1A) logic-in-memory LSI technology. This LSI is applicable to the digital video time-division switching and digital crossconnect systems of future B-ISDN.<>     

Silicon bipolar 1:16-demultiplexer for 10 Gbit/s fibre opticcommunication system

A 1:16-demultiplexer based on silicon bipolar 1:4-demultiplexer ICs, which include all requirements for system applications, has been designed and tested. The authors report the design of the 1:4-demultiplexer, which operates up to 14 Gbit/s, and experimental results for the 1:16-demultiplexer at 10 Gbit/s     

Scalable 10 Gbit/s 4×20.25 μm CMOS/SIMOX ATM switch LSIcircuit based on distributed contention control

A scalable 10 Gbit/s 4×2 ATM switch LSI circuit has been fabricated. It employs a new distributed contention control technique that makes the LSI circuit expandable. To increase the LSI circuit throughput, 0.2 μm CMOS/SIMOX (separation by implanted oxygen) technology is used. It allows the LSI circuit to offer 221 I/O pins, an operating speed of 1.25 Gbit/s and 7 W power consumption     

High-speed, low-power, bipolar standard cell design methodology forGbit/s signal processing

A low-power Si bipolar standard cell LSI design methodology for gigabit/second signal processing is described. To obtain high-speed operation, it features a pair of differential clock channels inside cells, differential clock distribution with the placement of differential wires of equal length and load, a performance-driven layout, and a highly accurate static timing analysis. A computer-aided-design-based optimization technology for power dissipation makes cell currents minimum while maintaining the circuit speed. A 5.6-K gate synchronous digital hierarchy signal-processing LSI operating at 1.6 Gbit/s with only 3.9 W power consumption demonstrates the effectiveness of this design method     

Over 40 Gbit/s 16:1 multiplexer IC using InP/InGaAs HBT technology

A low-power 16:1 multiplexer (MUX) IC using undoped-emitter InP/InGaAs heterojunction bipolar transistors (HBTs) has been successfully designed and fabricated. To minimise power consumption, the collector current density of each HBT was optimised taking into account the required operating speed and the number of fan-outs. Up to 47 Gbit/s error-free operation was confirmed with low power consumption of about 3.2 W. These results demonstrate that InP/InGaAs HBT technology is attractive for fabricating over 40 Gbit/s, low-power medium-scale-integration (MSI) circuits.     

16 Gbit/s multiplexer IC using double mesa Si/SiGe heterojunction bipolar transistors

A double mesa Si/SiGe heterojunction bipolar transistor (HBT) was developed for application in integrated circuits. The HBT is characterised by an emitter base heterojunction and consequently by a high base doping concentration. By using these transistors an integrated digital circuit, a multiplexer, was implemented. The measured bit rate of this first Si/SiGe HBT circuit was 16 Gbit/s.<>     

A 4 Gbits/s GaAs 16:1 multiplexer/1:16 demultiplexer LSI chip

A GaAs 16:1 multiplexer (MUX)/1:16 demultiplexer (DMUX) LSI chip, which operates at data rates from 50 Mb/s up to 4 Gb/s in a multilayer ceramic package, is described. The LSI chip incorporates trees of 2:1 MUX and 1:2 DMUX. The 2:1 MUX is composed of a master-slave D-flip-flop (DFF) joined with a 2-1 selector. The 1:2 DMUX consists of DFFs which are either a master-slave or the tristage type. The package has 76 pins and consists of five layers, including four power layers, and is applicable up to 7.7 GHz operation. The LSI chip is fabricated using a flat-gate self-aligned implantation for n⁺-layer technology (FG-SAINT process)     

A 2 Gb/s expandable space-division switching LSI and networkarchitecture for gigabit-rate broad-band circuit switching

An expandable space-division (SD) switch architecture and a bipolar circuit design for gigabit-per-second crosspoint-switch LSIs are described. An expandable 2-Gb/s 16×16 crosspoint switch LSI which employs a novel switch structure, a novel circuit design, and a super self-aligned process (SST-1A) is developed. A switching module and partial 1:n nonblock, full 1:1 nonblock switching network architecture are also presented. Using the LSI and the switching network architecture, an experimental 620-Mb/s network system is demonstrated     

Fully transparent multiplexing and transport of 10 GbE-LANPHY signals for 44.6 Gbit/s-based RZ-DQPSK WDM transmission

Transparent 10 GbE-LANPHY transport for 44.6 Gbit/s RZ-DQPSK WDM transmission is demonstrated for the first time. A single-chip 43/44 Gbit/s OTN framer LSI that supports fully transparent STM-64/10 GbE multiplexing and DQPSK precoding is adopted.     

16 Gbit/s multiplexer experiment

A multiplexer experiment was performed that provided an n.r.z.-format serial-output pulse stream of 16 Gbit/s bit rate and 2 V across a load of 50 ?. The bit rate of the input tributaries was 1.12 Gbit/s. The multiplexer circuit essentially employed ultrabroadband hybrid tees, fast step-recovery diodes, and fast GaAs Schottky-barrier diodes.     

Silicon bipolar decision circuit handling bit rates up to 5 Gbit/s

A high-speed silicon bipolar decision circuit is presented which operates up to 5 Gbit/s. It may serve as a subcomponent for integration in a regenerator/repeater circuit for multi-gigabit fiber-optic trunk lines. The circuit was implemented in a standard bipolar silicon technology featuring oxide-wall isolation, 2-μm emitter stripe widths, and a transit frequency of 9 GHZ atV_{CE} = 1V. The measured clock-phase-margin of the decision circuit at 4 Gbit/s corresponds to two thirds of a bit slot and to half a bit slot at 5 Gbit/s. The minimum input sensitivity at 4 Gbit/s is less than 150 mV.     

80 Gbit/s ATM switch MCM based on multilayer ceramic technology

An 80 Gbit/s asynchronous transfer mode (ATM) switch multichip module (MCM) of dimensions 114×160×6.5 mm has been fabricated. This MCM can support high-density mounting and high-speed interconnection among large-scale-integrated (LSI) chips. Using LSI, ceramic-substrate, high-speed/high-power connector, and compact liquid-cooling technologies, an 80 Gbit/s ATM switching module has been built     

A Si bipolar 1.4-GHz time space switch LSI for B-ISDN

A 155-MB/s 32×32 Si bipolar switch LSI designed for wide application in the broadband ISDN was implemented. The operating speed is 1.4 GHz using an A-BSA Si bipolar process. Its throughput is 5.0 Gb/s by handling four 1.4-GHz interfaces, each of which supports an eight-channel multiplexed data stream. To realize a highly integrated high-speed bipolar LSI, power consumption and chip area should be reduced. Two technologies were developed for the LSI: (1) an active pull-down circuit with an embedded bias circuit in each gate, and (2) a modified standard cell with overlapped cell-channel structure. Using these technologies, total power consumption and chip area were reduced to 60% and 70%, respectively, of what is expected when conventional emitter-coupled logic (ECL) technologies and standard cell structures are used. The LSI evaluation results show that the developed LSI has sufficient performance to realize a large-scale B-ISDN switching system     

A time division multiplexer IC for bit rates up to about 2 Gbits/s

A bipolar 4:1 time-division multiplexer IC developed for a planned 1.12 Gbit/s optical communication system is presented. Without resorting to sophisticated technology, the high speed was achieved by modification of well-known circuit concepts and by careful circuit optimization. With a current-switch output, reliable operation was measured to over 2 Gbit/s compared to over 1.5 Gbit/s if emitter-follower outputs are used. The experimental results agree very well with the simulation predictions.     

16 Gbit/s fibre transmission experiment using optical time-division multiplexing

An experimental four-channel optical time-division multiplexed transmission system is described, and the first demonstration of fibre transmission at a bit rate of 16Gbit/s is reported. In this experiment, data at 16Gbit/s have been transmitted over 8 km of fibre with a bit error rate below 10-9.     

25 Gbit/s decision circuit, 34 Gbit/s multiplexer, and 40 Gbit/s demultiplexer IC in selective epitaxial Si bipolar technology

A 25 Gbit/s decision circuit, a 34 Gbit/s multiplexer, and a 40 Gbit/s demultiplexer IC have been realised with selective epitaxial silicon bipolar technology using 0.8 mu m lithography. The data rates achieved are the highest values reported for these types of circuit in any IC technology.<>     

A 16-bit LSI minicomputer

A 16-bit LSI minicomputer, using n-channel MOS technology, has been developed. The instruction set contains 126 instructions including floating-point arithmetic and is fully compatible with commercially available minicomputers such as the TOSBAC-40 and the Interdata 70. An execution speed of 2 /spl mu/s is obtained for register to register (RR) instructions. All the central processing unit (CPU) functions are implemented on a single board. An external microprogram ROM and short-single address microinstructions are used to realize high-system performance and reduce the chip area and the package pin numbers. Two LSI chips for the system, a single-chip processor, and a bit-sliced bus controller, are fabricated by a new n-channel MOS technology named the gate oxidation method (GOM) which provides a high-packing density, high speed, and a simplified process.     

1 Gbit/s, 32*32 high-speed space-division switching module for broadband ISDN using SST LSIs

A high-speed 32*32 space-division switching module for high-definition TV broadcasting and switching systems is described. It employs a newly developed Si-bipolar SST 8*8 switch LSI, high-speed peripheral ICs and a high-speed impedance-controlled board. The module is capable of a 1.0 Gbit/s signal speed using 1:1 and 1:n connections.<>     

Integrated bipolar master/slave D-flip-flop with multiplexing capability for Gbit/s operation

A versatile integrated bipolar circuit developed for a broadband communication system is described. It consists of a master/slave D-flip-flop with a 2:1 time-division multiplexer at the input and a powerful buffer stage at the output. Despite realisation in a relatively simple bipolar technology, bit rates up to 1.5 Gbit/s (NRZ) were measured.