25 Gbit/s decision circuit, 34 Gbit/s multiplexer, and 40 Gbit/s demultiplexer IC in selective epitaxial Si bipolar technology

A 25 Gbit/s decision circuit, a 34 Gbit/s multiplexer, and a 40 Gbit/s demultiplexer IC have been realised with selective epitaxial silicon bipolar technology using 0.8 mu m lithography. The data rates achieved are the highest values reported for these types of circuit in any IC technology.<>     

24 Gbit/s regenerating demultiplexer IC in silicon bipolar technology

A 1:2 regenerating demultiplexer IC has been realised in an advanced self-aligned silicon bipolar technology using 0.8 mu m lithography. The circuit can be operated up to 24 Gbit/s at 5 V supply voltage. This is by far the highest data rate reported for a demultiplexer in any IC technology.<>     

16 Gbit/s multiplexer IC using double mesa Si/SiGe heterojunction bipolar transistors

A double mesa Si/SiGe heterojunction bipolar transistor (HBT) was developed for application in integrated circuits. The HBT is characterised by an emitter base heterojunction and consequently by a high base doping concentration. By using these transistors an integrated digital circuit, a multiplexer, was implemented. The measured bit rate of this first Si/SiGe HBT circuit was 16 Gbit/s.<>     

40 Gbit/s differential distributed modulator driver realised in 80 GHz SiGe HBT process

A 40 Gbit/s, fully differential distributed SiGe HBT driver is presented. The IC is realised in a low-cost 80 GHz production process, and is intended to operate as a modulator driver in a 40 Gbit/s fibre-optic communication system. Resulting from the differential chip architecture, no off-chip low-frequency transmission line termination networks are required, which significantly alleviates the chip mounting process. Mounted in a coaxial test fixture, an eye opening of 2 1.25 V_pp at 40 Gbit/s operation is measured.     

Over 40 Gbit/s 16:1 multiplexer IC using InP/InGaAs HBT technology

A low-power 16:1 multiplexer (MUX) IC using undoped-emitter InP/InGaAs heterojunction bipolar transistors (HBTs) has been successfully designed and fabricated. To minimise power consumption, the collector current density of each HBT was optimised taking into account the required operating speed and the number of fan-outs. Up to 47 Gbit/s error-free operation was confirmed with low power consumption of about 3.2 W. These results demonstrate that InP/InGaAs HBT technology is attractive for fabricating over 40 Gbit/s, low-power medium-scale-integration (MSI) circuits.     

15 Gbit/s silicon bipolar amplifier IC using a novel mountingtechnique

A DC-coupled silicon bipolar amplifier IC, for operation in future multigigabit optical communication systems, has been fabricated using ⩾30 GHz double-polysilicon transistors. Using a novel HF connection technique for reducing the bondwire inductance, we have succeeded in the fabrication of a 14 dB gain amplifier IC, with a flatness better than ±0.5 dB, combined with a -3 dB bandwidth of 12.8 GHz. This is the highest bandwidth ever reported for a bonded amplifier circuit in any semiconductor technology     

Voltage-controlled oscillators up to 98 GHz in SiGe bipolar technology

In this paper, two fully integrated voltage-controlled oscillators (VCOs) in a 200-GHz f/sub T/ SiGe bipolar technology are presented. The oscillators use on-chip transmission lines at the output for impedance transformation. One oscillator operates up to 98 GHz and achieves a phase noise of -85dBc/Hz at an offset frequency of 1 MHz. It can be tuned from 95.2 to 98.4 GHz and it consumes 12 mA from a single -5-V supply. The second oscillator operates from 80.5 GHz up to 84.8 GHz with a phase noise of -87dBc/Hz at 1-MHz offset frequency. The output power of both circuits is about -6dBm.     

15 GHz static frequency-divider IC in silicon bipolar technology

A static 16:1 frequency-divider IC operating at up to 15 GHz has been realised with 1 mu m lithography. This is the highest operating frequency ever reported for static silicon dividers.<>     

40 GHz 7.9 mW low-power frequency divider IC using self-alignedselective-epitaxial-growth SiGe HBTs

A low-power current-mode-logic frequency divider integrated circuit (IC) that operated at 40 GHz with a power consumption of 7.9 mW per master-slave flip-flop was fabricated using 0.2 μm self-aligned selective-epitaxial-growth SiGe heterojunction bipolar transistors. This IC also operated at 35 GHz from a supply voltage of -2.2 V. To the authors' knowledge this IC consumes the least power of any for operation in the millimetre-waveband that have appeared to date     

11.4 Gbit/s silicon bipolar multiplexer IC employing 2 mu m lithography transistors

A very high-speed 2:1 multiplexer IC operating up to 11.4 Gbit/s has been implemented. The circuit was fabricated using a 12 GHz non-polysilicon-emitter self-aligning bipolar process with 2 mu m lithography. Despite realisation in a relatively simple technology, this is the highest operating speed yet achieved with any technology.<>     

5 Gbit/s laser-driver GaAs IC

A design of a 5 Gbit/s laser-driver GaAs IC employing a novel 50 Ω impedance matched output driver is presented. Eye diagrams with good eye openings, clean waveforms and output reflection coefficients of less than -8 dB for frequencies up to 10 GHz are demonstrated over a 10-36 mA output current tuning range     

40Gbit/s master-slave D-type flip-flop in InP DHBT technology

A D-type flip-flop (MS D-FF) fabricated in a self-aligned InP DHBT technology is presented. 40 Gbit/s on-wafer measurements (limited by measurement setup) show good rise/fall times, low time jitter, as well as important regenerating capabilities. Some important design aspects are highlighted     

40 Gbit/s fully monolithic clock recovery IC usingInAlAs/InGaAs/InP HEMTs

The authors describe a 40 Gbit/s fully monolithic clock recovery integrated circuit (IC) fabricated using 0.1 μm InAlAs/InGaAs/InP HEMTs. The IC utilises injection locking, and consists of a half bit delay, an exclusive OR gate and a T-type flip-flop. The IC extracts a half-rate clock signal from a 39.81312 Gbit/s 2³¹-1 pseudo-random bit sequence signal without any other external components     

40 Gbit/s monolithic integrated modulator driver in InP SHBT technology

A high-speed and high-gain modulator driver circuit is presented using 4-inch InP SHBT technology. The IC was developed for driving EAM modulators in 40 Gbit/s optical fibre systems. The monolithic integrated circuit features output amplitude control and output crossing point control. Measured results show the circuit operates at 40 Gbit/s with a swing of 2.5 V/sub p-p/ at each output and 9/8 ps rise/fall times. The power dissipation is 1.5 W with a standard power supply of -5.2 V.     

Silicon bipolar IC for PRBS testing generates adjustable bit ratesup to 25 Gbit/s

For the first time, a completely integrated pseudo-random pattern generator providing adjustable bit rates up to at least 25 Gbit/s without additional external multiplexing is presented. The sequence length is 2ⁿ-1. The application of the monolithic Si bipolar IC serves as a single chip measurement instrument for pseudo-random binary sequence (PRBS) generation required for the characterisation and development of high-speed components used in future optical fibre communication systems. Only three external microwave components are needed for operation: a clock generator, a power divider and a phase shifter. The chip is realised in an advanced implanted base silicon bipolar technology     

4 Gbit/s GaAs MESFET laser-driver IC

A high-speed laser-driver IC has been fabricated using etched-gate enhancement/depletion-mode MESFET technology. It has been demonstrated that the device is capable of driving 25? load with 80 mA modulation current at up to 4 Gbit/s NRZ data rate.     

A 30-Gbit/s demultiplexer IC based on Si/SiGe emitter baseheterojunction bipolar transistors

A 30-Gbit/s demultiplexer IC has been fabricated and tested using an improved double mesa Si/SiGe heterojunction bipolar transistor process. This is-to our knowledge-the highest ever reported bit rate for “real” (as opposed to drift transistor) Si/SiGe HBT circuits. The result was mainly reached by scaling down the transistor sizes to reduce parasitics. The minimum emitter mesa width was 1 μm     

40GWDM关键指标及技术解决方案

结合40G WDM技术在省际干线上应用情况,简要分析了YD/T1991-2009标准中的OSNR及BER等主要技术指标,提出并分析了阿尔卡特朗讯在40G WDM方面的主要技术解决方案