抗单粒子翻转的双端口SRAM定时刷新机制研究

在空间辐射环境下,存储单元对单粒子翻转的敏感性日益增强。通过比较SRAM的单粒子翻转效应相关加固技术,在传统EDAC技术的基础上,增加少量硬件模块,有效利用双端口SRAM的端口资源,提出了一种新的周期可控定时刷新机制,实现了对存储单元数据的周期性纠错检错。对加固SRAM单元进行分析和仿真,结果表明,在保证存储单元数据被正常存取的前提下,定时刷新机制的引入很大程度地降低了单粒子翻转引起的错误累积效应,有效降低了SRAM出现软错误的概率。     

基于SRL结构的抗辐射SRAM单元设计

在空间辐射环境中,单粒子翻转(SEU)效应严重影响了SRAM的可靠性,对航天设备的正常运行构成极大的威胁。提出了一种基于自恢复逻辑(SRL)结构的新型抗辐射SRAM单元,该单元的存储结构由3个Muller C单元和2个反相器构成,并采用读写线路分开设计。单粒子效应模拟实验结果表明,该单元不仅在静态存储状态下对SEU效应具有免疫能力,在读写过程中对SEU效应同样具有免疫能力。     

Novel SEU hardened PD SOI SRAM cell

A novel SEU hardened 10T PD SOI SRAM cell is proposed.By dividing each pull-up and pull-down transistor in the cross-coupled inverters into two cascaded transistors,this cell suppresses the parasitic BJT and source-drain penetration charge collection effect in PD SOI transistor which causes the SEU in PD SOI SRAM. Mixed-mode simulation shows that this novel cell completely solves the SEU,where the ion affects the single transistor.Through analysis of the upset mechanism of this novel cell,SEU performance is roughly equal to the multiple-cell upset performance of a normal 6T SOI SRAM and it is thought that the SEU performance is 17 times greater than traditional 6T SRAM in 45nm PD SOI technology node based on the tested data of the references.To achieve this,the new cell adds four transistors and has a 43.4%area overhead and performance penalty.     

一种新式SEU加固PD SOI SRAM单元

本文提出了一种新式SEU加固的10管PD SOI静态存储单元。通过将互锁反相器中的上拉和下拉管分割成两个串联的晶体管,该单元可有效抑制PD SOI晶体管中的寄生BJT和源漏穿通电荷收集效应,这两种电荷收集效应是引起PD SOISRAM翻转的主要原因。通过混合仿真发现,与穿通的浮体6T单元相比,该单元可完全解决粒子入射单个晶体管引起的单粒子翻转。通过分析该新式单元的翻转机制,认为其SEU性能近似与6T SOI SRAM的单粒子多位翻转性能相等。根据参考文献的测试数据,粗略估计该新式单元的SEU性能比普通45nm 6T SOI SRAM单元提升了17倍。由于新增加了四个晶体管,该单元在面积上增加了43.4%的开销,性能方面有所降低。     

Single Event Upset rate determination for 65 nm SRAM bit-cell in LEO radiation environments

The degradation of SRAM bit-cells designed in a 65 nm bulk CMOS technology in a Sun-Synchronous Low Earth Orbit (LEO) ionizing radiation environment is analyzed. We propose an inflight SEU rate estimation approach based on a modeled heavy ion cross section as opposed to the standard experimental characterization. Effects of irradiation with estimated LET spectrum in SRAM bit cell, i.e. the location of sensitive regions, its tendency to cause upset, magnitude and duration of transient current as well as voltage pulses were determined. It was found with SEU map that 65 nm SRAM bit-cell can flip even if high LET particle strikes in close proximity of bit-cell outside the SRAM bit-cell area. The SEU sensitive parameters required to predict SEU rate of on-board target device, i.e., 65 nm SRAM were calculated with typical aluminum spot shielding using fully physical mechanism simulation. In order to characterize the robustness of scaled CMOS devices, state of the art simulation tools such as Visual TCAD/Genius, GSEAT/Visual Particle, runSEU, were utilized whereas LEO radiation environment assessment, upset rate prediction was accomplished with the help of OMERE-TRAD software.     

北京正负电子对撞机次级束质子单粒子翻转计算和试验研究

北京正负电子对撞机(BEPC)电子直线加速器试验束打靶产生的次级束中包含质子,其中能量约为50MeV~100MeV的质子占有很大比例,这弥补了国内高能质子源的空白。本工作计算得到次级束中的质子能谱,建立质子单粒子翻转截面计算方法,在北京正负电子对撞机次级束质子辐射环境中,计算静态随机存取存储器的质子单粒子翻转截面,设计了SRAM质子单粒子翻转截面测试试验,发现SRAM单粒子翻转和注量有良好的线性,这是SRAM发生单粒子翻转的证据。统计得到不同特征尺寸下SRAM单粒子翻转截面,试验数据与计算结果相符,计算和试验结果表明随着器件特征尺寸的减小器件位单粒子翻转截面减小,但器件容量的增大,翻转截面依然增大,BEPC次级束中的质子束可以开展中高能质子单粒子效应测试。     

一种超低功耗、容错的静态随机存储器设计

为了减轻辐射环境中静态随机存储器（SRAM）受单粒子翻转（SEU）的影响以及解决低功耗和稳定性的问题,采用TSMC 90nm工艺,设计了一款可应用于辐射环境中的超低功耗容错静态随机存储器。该SRAM基于双互锁存储单元（DICE）结构,以同步逻辑实现并具有1KB（1K×8b）的容量,每根位线上有128个标准存储单元,同时具有抗SEU特性,提高并保持了SRAM在亚阈值状态下的低功耗以及工作的稳定性。介绍了这种SRAM存储单元的电路设计及其功能仿真,当电源电压VDD为0.3V时,该SRAM工作频率最大可达到2.7MHz,此时功耗仅为0.35μW;而当VDD为1V时,最大工作频率为58.2MHz,功耗为83.22μW。     

5管SRAM单元的抗辐射性能研究

利用3D TCAD仿真,在45 nm 体硅工艺下,对5管SRAM单元和传统6管SRAM单元的抗辐射性能进行了对比研究。结果表明,5管SRAM单元的敏感面积更小,由该单元构成的SRAM阵列更难发生多位翻转。提出了一种带额外保护环的5管SRAM单元抗辐射加固策略,这种加固策略没有面积开销,模拟结果证实了该加固策略的有效性。     

Practical considerations in the design of SRAM cells on SOI

This paper presents the practical issues encountered in designing SRAM cell design on partially depleted SOI, including the effects of floating-body potential and parasitic bipolar. It also discusses the characteristics of single-event upsets (SEU) harden and total-dose radiation harden of SOI SRAM. A fully integrated solution, using a new type memory cell SRAM described.     

CMOS SRAM单粒子翻转效应的解析分析

分析了影响ＣＭＯＳＳＲＡＭ单粒子翻转效应的时间因素,指出不能仅根据临界电荷来判断发生单粒子翻转效应与否,必须考虑器件的恢复时间、反馈时间和电荷收集过程．给出了恢复时间和反馈时间的计算方法,提出了器件抗单粒子翻转的加固措施．对电荷收集过程中截止管漏极电位的变化进行了分析,提出了临界电荷新定义,并给出了判断带电粒子入射能否导致器件发生单粒子翻转效应的方法     

A proposed new structure for SEU immunity in SRAM employing drain resistance

A novel static random access memory (SRAM) cell is proposed (LRAM) in which resistors are used to delay ion-induced transients conventionally, and to divide down voltage transients at the information node. The voltage divider is a new concept in SEU hardening and has practical value for technologies where the voltage transient duration is significantly different for responses to ion strikes at p- and n-channel drains. In combination, the two pairs of resistors allow much reduced resistor values with the advantage of faster access times, better temperature stability, and better scalability. Advanced simulations in which transport and circuit effects are modeled simultaneously are used to project the viability of the LRAM concept and data from single-cell test structures and support the analysis.     

驱动能力对SOI SRAM单元单粒子效应的影响仿真

采用silvaco软件对抗辐射不同沟道宽度的PD SOI NMOS器件单元进行了三维SEU仿真,将瞬态电流代入电路模拟软件HSPICE中进行SRAM存储单元单粒子翻转效应的电路模拟。通过这种电路模拟的方法,可以得到SRAM存储单元的LET阈值。通过对比LET阈值的实际测量值,验证了这种方法的实用性,并对不同驱动能力的SRAM单元进行了翻转效应的对比。在NMOS和PMOS驱动比相同的情况下,沟道宽度越大,SRAM的翻转LET阈值反而越高。     

基于FPGA定时刷新控制单元的应用技术研究

SRAM型FPGA在航天领域有着广泛的应用,为解决FPGA在宇宙环境中单粒子翻转的问题,适应空间应用需求,给出了一种低成本抗辐照解决方案,对耐辐射FPGA器件进行抗单粒子翻转加固设计。该方案兼容多种型号FPGA芯片,从3片SPI FLASH中读取配置数据,通过串行接口配置FPGA,并在配置完成后按照设定时间周期性刷新芯片,可以满足航天领域对抗辐照型FPGA的使用需求。     

SRAM single event upset calculation and test using protons in the secondary beam in the BEPC

The protons in the secondary beam in the Beijing Electron Positron Collider(BEPC) are first analyzed and a large proportion at the energy of 50-100 MeV supply a source gap of high energy protons.In this study, the proton energy spectrum of the secondary beam was obtained and a model for calculating the proton single event upset(SEU) cross section of a static random access memory(SRAM) cell has been presented in the BEPC secondary beam proton radiation environment.The proton SEU cross section for different characteristic dimensions has been calculated.The test of SRAM SEU cross sections has been designed,and a good linear relation between SEUs in SRAM and the fluence was found,which is evidence that an SEU has taken place in the SRAM.The SEU cross sections were measured in SRAM with different dimensions.The test result shows that the SEU cross section per bit will decrease with the decrease of the characteristic dimensions of the device,while the total SEU cross section still increases upon the increase of device capacity.The test data accords with the calculation results,so the high-energy proton SEU test on the proton beam in the BEPC secondary beam could be conducted.     

Single event soft error in advanced integrated circuit

As technology feature sizes decrease, single event upset (SEU), and single event transient (SET) dominate the radiation response of microcircuits. Multiple bit upset (MBU) (or multi cell upset) effects, digital single event transient (DSET) and analogue single event transient (ASET) caused serious problems for advanced integrated circuits (ICs) applied in a radiation environment and have become a pressing issue. To face this challenge, a lot of work has been put into the single event soft error mechanism and mitigation schemes. This paper presents a review of SEU and SET, including: a brief historical overview, which summarizes the historical development of the SEU and SET study since their first observation in the 1970's; effects prominent in advanced technology, which reviews the effects such as MBU, MSET as well as SET broadening and quenching with the influence of temperature, device structure etc.; the present understanding of single event soft error mechanisms, which review the basic mechanism of single event generation including various component of charge collection; and a discussion of various SEU and SET mitigation schemes divided as circuit hardening and layout hardening that could help the designer meet his goals.     

基于25 nm FinFET结构的SRAM单粒子效应研究

对基于25 nm FinFET结构的SRAM单粒子效应进行研究。使用Synopsys Sentaurus TCAD仿真软件进行器件工艺校准,并对独立3D FinFET器件以及包含FinFET器件和HSpice模型的混合电路(如6管SRAM单元)进行单粒子瞬态仿真。通过改变重粒子入射条件,分析影响瞬态电流峰值、脉宽、漏极翻转阈值等参数的因素。研究发现,混合模型中,FinFET结构器件的漏极翻转阈值为0.023 MeV·cm²/mg,对未来基于FinFET结构的器件及电路结构的加固提出了更高的要求。     

用SOI技术提高CMOS SRAM的抗单粒子翻转能力

提高静态随机存储器（SRAM）的抗单粒子能力是当前电子元器件抗辐射加固领域的研究重点之一。体硅CMOS SRAM不作电路设计加固则难以达到较好抗单粒子能力,作电路设计加固则要在芯片面积和功耗方面做出很大牺牲。为了研究绝缘体上硅（SOI）基SRAM芯片的抗单粒子翻转能力,突破了SOI CMOS加固工艺和128kb SRAM电路设计等关键技术,研制成功国产128kb SOI SRAM芯片。对电路样品的抗单粒子摸底实验表明,其抗单粒子翻转线性传输能量阈值大于61．8MeV／（mg／cm^2）,优于未做加固设计的体硅CMOS SRAM。结论表明,基于SOI技术,仅需进行器件结构和存储单元的适当考虑,即可达到较好的抗单粒子翻转能力。     

A proposed DG-FinFET based SRAM cell design with RadHard capabilities

The radiation induced soft errors have become one of the most important and challenging failure mechanisms in modern electronic devices. This paper proposes a new circuit level hardening technique for reduction of soft error failure rate in DG-FinFET (double gate FinFET) based static random access memory (SRAM). Analysis for 32 nm and 45 nm technology nodes is carried out. It is inferred from the paper that the proposed SRAM cell outperforms over DICE latch in terms of fault tolerance of external data and control lines, power dissipation and fast recovery when exposed to radiation for both the technology nodes. This is primarily due to the addition of extra transistors used to neutralize the effect of single event upset without affecting normal operations. Transistor count increase the area and write delay by 7% and 20% respectively over that of DICE latch. While read delay decreases by 14% for the proposed SRAM cell.     

Optimization of SEU Simulations for SRAM Cells Reliability under Radiation

A simplified RC circuit is used to simulate effects of ionizing particles in a 90?nm SRAM. The main characteristics of the memory cell bit flip are discussed and a SEU criterion is presented. The effect of the surrounded circuit on the struck transistor is also discussed in order to extract parameters characteristic of the SEU occurrence.     

SOI CMOS SRAM单元单粒子翻转效应的模拟

为简单快速模拟静态随机存储器(SRAM)的单粒子效应,在二维器件数值模拟的基础上,以经典的双指数模型为原型,通过数值拟合得到了单粒子效应瞬态电流脉冲的表达式,考虑晶体管偏压对瞬态电流的影响,得到修正的瞬态电流表达式,将其带入电路模拟软件HSPICE中进行SRAM存储单元单粒子翻转效应的电路模拟,通过与实际单粒子实验结果的对比,验证了这种模拟方法的实用性。