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1.
Software-implemented EDAC protection against SEUs 总被引:1,自引:0,他引:1
In many computer systems, the contents of memory are protected by an error detection and correction (EDAC) code. Bit-flips caused by single event upsets (SEU) are a well-known problem in memory chips; EDAC codes have been an effective solution to this problem. These codes are usually implemented in hardware using extra memory bits and encoding/decoding circuitry. In systems where EDAC hardware is not available, the reliability of the system can be improved by providing protection through software. Codes and techniques that can be used for software implementation of EDAC are discussed and compared. The implementation requirements and issues are discussed, and some solutions are presented. The paper discusses in detail how system-level and chip-level structures relate to multiple error correction. A simple solution is presented to make the EDAC scheme independent of these structures. The technique in this paper was implemented and used effectively in an actual space experiment. We have observed that SEU corrupt the operating system or programs of a computer system that does not have any EDAC for memory, forcing the system to be reset frequently. Protecting the entire memory (code and data) might not be practical in software. However this paper demonstrates that software-implemented EDAC is a low-cost solution that provides protection for code segments and can appreciably enhance the system availability in a low-radiation space environment 相似文献
2.
A method for design of built-in testable (BIT) error detection and correction (EDAC) circuits is presented that uses up to 65% less test hardware than customary BIT implementations. A 1-μm CMOS, 16-bit EDAC designed and fabricated with this technique exhibits >99% fault coverage in 10 μs at 25 MHz. Built-in test impacts the speed performance by only one gate delay regardless of the size of the EDAC. Various faults are injected into the chip to verify the effectiveness of built-in test 相似文献
3.
Felipe Silva Jardel Silveira Jarbas Silveira César Marcon Fabian Vargas Otávio LimaJr 《Journal of Electronic Testing》2018,34(4):417-433
As the microelectronics technology continuously advances to deep submicron scales, the occurrence of Multiple Cell Upset (MCU) induced by radiation in memory devices becomes more likely to happen. The implementation of a robust Error Correction Code (ECC) is a suitable solution. However, the more complex an ECC, the more delay, area usage and energy consumption. An ECC with an appropriate balance between error coverage and computational cost is essential for applications where fault tolerance is heavily needed, and the energy resources are scarce. This paper describes the conception, implementation, and evaluation of Column-Line-Code (CLC), a novel algorithm for the detection and correction of MCU in memory devices, which combines extended Hamming code and parity bits. Besides, this paper evaluates the variation of the 2D CLC schemes and proposes an additional operation to correct more MCU patterns called extended mode. We compared the implementation cost, reliability level, detection/correction rate and the mean time to failure among the CLC versions and other correction codes, proving the CLCs have high MCU correction efficacy with reduced area, power and delay costs. 相似文献
4.
Mostafa Kishani Hamid R. Zarandi Hossein Pedram Alireza Tajary Mohsen Raji Behnam Ghavami 《Design Automation for Embedded Systems》2011,15(3-4):289-310
This paper presents a high level error detection and correction method called HVD code to tolerate multiple bit upsets (MBUs) occurred in memory cells. The proposed method uses parity codes in four directions in a data part to assure the reliability of memories. The proposed method is very powerful in error detection while its error correction coverage is also acceptable considering its low computing latency. HVD code is useful for applications whose high error detection coverage is very important such as memory systems. Of course, this code can be used in combination with other protection codes which have high correction coverage and low detection coverage. The proposed method is evaluated using more than one billion multiple fault injection experiments. Multiple bit flips were randomly injected in different segments of a memory system and the fault detection and correction coverages are calculated. Results show that 100% of the injected faults can be detected. We proved that, this method can correct up to three bit upsets. Some hardware implementation issues are investigated to show tradeoffs between different implementation parameters of HVD method. 相似文献
5.
基于FPGA的LDPC码编译码器联合设计 总被引:1,自引:0,他引:1
该文通过对低密度校验(LDPC)码的编译码过程进行分析,提出了一种基于FPGA的LDPC码编译码器联合设计方法,该方法使编码器和译码器共用同一校验计算电路和复用相同的RAM存储块,有效减少了硬件资源的消耗量。该方法适合于采用校验矩阵进行编码和译码的情况,不仅适用于全并行的编译码器结构,同时也适用于目前广泛采用的部分并行结构,且能够使用和积、最小和等多种译码算法。采用该方法对两组不同的LDPC码进行部分并行结构的编译码器联合设计,在Xilinx XC4VLX80 FPGA上的实现结果表明,设计得到的编码器和译码器可并行工作,且仅占用略多于单个译码器的硬件资源,提出的设计方法能够在不降低吞吐量的同时有效减少系统对硬件资源的需求。 相似文献
6.
The problem of concurrent error detection and fault tolerance is studied. These checksums of time-varying functions are possible because the function of a linear analog circuit can be represented mathematically by a set of matrices to which checksum codes can be applied. For the purpose of error detection, it is assumed that a fault can cause the value of a passive circuit component to deviate from its normal value, result in a line short or open, or change the operating characteristics of the active components (operational amplifiers). If the specifying parameters of a linear analog circuit change due to a fault and the failed circuit behaves as a linear system, then error correction is performed by compensating for the changed parameter values. Otherwise, partical correction is possible. Error detection and correction are performed by a small amount of hardware added to the linear analog circuit. The hardware overhead is virtually constant irrespective of the circuit size, and the sensitivity of the error detection circuit to failures can be easily calibrated 相似文献
7.
Turbo乘积码是一种性能卓越的前向纠错码,具有译码复杂度低,且在低信噪比时可以获得近似最优的性能。介绍基于Chase算法的Turbo乘积码软入软出(SISO)迭代译码算法,提出基于VHDL硬件描述语言的TPC译码器设计方案,并在FPGA芯片上进行了仿真和验证。仿真结果证明该译码器有很大的实用性和灵活性。 相似文献
8.
A novel 16-level current-mode DRAM based on the continuous valued number system (CVNS) representation is introduced. The refreshing circuitry of this DRAM is designed using analogue to digital converter (ADC) and digital to analogue converter modules. Each ADC generates two bits of the output simultaneously which decreases the delay time of the ADC module. Error correction codes are used to increase the noise margin by a factor of two. The proposed memory can be used in hardware implementation of CVNS based systems. 相似文献
9.
设计了一种以单片机和光纤传感器为基础构成的表面粗糙度测量系统。该系统由光纤传感器、信号检测电路、单片机处理电路和显示装置组成。其特点是系统性能稳定、适应性强、精度高,可以对不同加工方法的工件实现非接触和在线测量。重点给出了该系统的主要硬件和软件及实现方法。 相似文献
10.
《Circuits and Systems II: Express Briefs, IEEE Transactions on》2009,56(1):51-55
11.
Egas Henes Neto Gilson Wirth Fernanda Lima Kastensmidt 《Journal of Electronic Testing》2008,24(5):425-437
In this paper, we propose a diagnose strategy based on built-in current sensors able to detect the effects of single event
transients (SETs) in SRAM memory decoders. By analyzing the effects, it is possible to mitigate the error by warning the system
about the erroneous write and read operation or by circuit error correction avoiding catastrophic multiple bit upset errors.
While EDAC can only protect faults in the memory cell array, the proposed method can cope with faults in the combinational
memory circuitry. This BICS-based technique can be used in combination with EDAC to achieve high reliability in memories fabricated
in nanometer technologies. Our methodology has been validated by Spice simulation and results show that our approach presents
a low area, performance and power dissipation penalty. 相似文献
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提出了一种基于内置集成电路总线技术的太阳光度计,系统采用硅光电二极管组成光电检测电路,可以有效地降低仪器的体积、功耗、价格,从而实现以很高的性价比设立大范围的观测网,同时光度计有很高的观测精度.介绍了系统的探测原理、电子学软硬件系统设计以及实验结果分析.实验结果表明太阳光度计运行可靠,可以满足气溶胶观测的要求. 相似文献
16.
As CMOS technology size scales down, multiple cell upsets (MCUs) caused by a single radiation particle have become one of the most challenging reliability issues for memories used in space application. Error correction codes (ECCs) are commonly used to protect memories against errors. Single error correction-Double error detection (SEC-DED) codes are the simplest and most typical ones, but they can only corrected single errors. The advanced ECCs, which can provide enough protection for memories, cost more overhead due to their complex decoders. Orthogonal Latin square (OLS) codes are one type of one-step majority logic decodable (OS-MLD) codes that can be decoded with low complexity and delay. However, there are no OLS codes directly fitting 32-bit data, which is a typical data size in memories. In this paper, (55, 32) and (68, 32) codes derived from (45, 25) and (55, 25) OLS codes have been proposed in order to improve OLS codes in terms of protection for the 32-bit data. The proposed codes can maintain the correction capability of OLS codes and be decoded with low delay and complexity. The evaluation of the implementations for these codes are presented and compared with those of the shortened version (60, 32) and (76, 32) OLS codes. The results show that the area and power of a 2-bit MCUs immune radiation hardened SRAM that protected by the proposed codes have been reduced by 7.76% and 6.34%, respectively. In the case of a 3-bit MCUs immune, the area and power of whole circuits have been reduced by 8.82% and 4.56% when the proposed codes are used. 相似文献
17.
提出了一种基于区域分割技术的硬件木马检测方法,通过电路设计和检测相结合的方式,在电路内植入能生成多种测试向量的自测试模块,且不同测试向量可使目标区域电路内部节点在工作时具有高、低翻转率的差异,采用区域独立供电网络设计及门控时钟控制区域分时工作等方法,提高由硬件木马产生的侧信道数据在整体电路侧信道数据中所占的比重,使含有硬件木马电路的侧信道数据与正常数据差异明显,从而更易于鉴别隐藏于电路中的硬件木马.仿真测试结果表明,本方法最高可检测出占总体电路规模0.3%的时序逻辑型硬件木马,与传统的硬件木马检测方式相比,明显提高了硬件木马检测的分辨率. 相似文献
18.
So Young Kim Wong S.S. 《IEEE transactions on circuits and systems. I, Regular papers》2007,54(9):2001-2010
The Elmore delay model is the most popular and efficient delay model used for analytical delay estimation. Closed-form delay formulas are useful for circuit design, timing-driven physical design, synthesis, and optimization. As signal rise time becomes faster and the line resistance becomes smaller from copper technology, the significance of inductance increases. Both RC and RLC delays are a strong function of signal rise time. We propose a novel and efficient delay modeling method based on nondimensionalization to consider finite input rise time as an improvement over the Elmore's approach. To further improve the accuracy of the delay model, a new correction method, effective distance correction factor (EDCF), is proposed to consider resistive shielding of downstream capacitance. EDCF can be used to correct the delays for both RC and RLC tree structures. The proposed delay modeling method was applied to a number of nets selected from an integrated circuit (IC) design, and the delay estimation results were compared with HSPICE simulations. The new delay model retains the efficiency and simplicity of the Elmore delay model with significantly improved accuracy. 相似文献
19.
提出了一种新的选择迭代式高速高精度CORDIC(COrdinate Rotation Digital Computer)算法.基于表驱动法缩小目标旋转角度,通过改进的基本角度选择方法旁路不必要的迭代;并以移位和减法实现幅度校正,减小硬件资源消耗.设定角度误差小于10-5rad时,迭代次数减小至7次以下.在DDFS(Direct Digital Frequency Synthesizer)的应用中,利用区间压缩技术在Xilinx的FPGA中实现20位定点小数电路设计.仿真及实测结果表明,该算法幅度误差小于2×10-5,输出延时不大于43.5ns,同时硬件资源消耗不增加. 相似文献
20.
Osnat Keren 《Journal of Electronic Testing》2010,26(3):337-353
The paper deals with context-oriented codes for concurrent error detection. We consider a fault model for which, in the presence
of a fault, the values on the circuit’s output are arbitrary. This model allows one to design an error detection code without
analyzing sensitive parts or error cones in the synthesized circuit. Conventional coding schemes are based on a one-to-one
mapping between an original output vector (information word) and a codeword. In this paper, we introduce a different approach,
which we call one-to-many coding. In one-to-many code, each codeword comprises a predefined set of words. The functional unit is referred to as an
encoder enabling each activation to map an information word to a different word. This flexible mapping system results in a
lower implementation cost of the functional unit and its checker. 相似文献