Novel Miniature and Broadband Millimeter-Wave Monolithic Star Mixers

In this paper, three monolithic star mixers using a new miniature dual balun are proposed. The first one is a double spiral transformer mixer, and the second one is a trifilar transformer mixer. Both of these are fabricated using a commercial GaAs pseudomorphic HEMT process. The third is a 3-D transformer mixer, which is fabricated using a commercial CMOS process. These mixers exhibit bandwidths over 25-45 GHz (57%) with local oscillator isolations better than 20 dB. These star mixers are smaller than (lambda/6timeslambda/6) for the mixer core area. Compared with traditional star mixers, these mixers demonstrate 80% size reduction, and achieve good performance with the smallest chip size among all star mixers using monolithic microwave integrated circuit processes.     

A 17.1-17.3-GHz image-reject downconverter with phase-tunable LO using 3/spl times/ subharmonic injection locking

A 17-GHz RF receiver, consisting of a low-noise amplifier (LNA) and doubly balanced mixers coupled by a monolithic 3.7:1 step-down transformer, realizes over 75 dB of image rejection in a production 100-GHz f/sub T/ SiGe BiCMOS technology. A new coupling transformer winding improves the magnetic coupling coefficient by more than 20% compared to conventional designs, which reduces parasitic effects and increases the overall efficiency of the LNA/mixer combination. Quadrature LO signals with electronically tunable phase are generated by a subharmonically injection-locked oscillator. The measured receiver IIP3 is -5.1 dBm with 17.3-dB conversion gain and 6.5-dB noise figure (SSB 50 /spl Omega/) at 17.2 GHz. The 1.9/spl times/1.0 mm/sup 2/ IC consumes 62.5 mW from a 2.2-V supply.     

Analysis and Design of Reduced-Size Marchand Rat-Race Hybrid for Millimeter-Wave Compact Balanced Mixers in 130-nm CMOS Process

The analysis and design flow for reduced-size Marchand rat-race hybrids are presented in this paper. A simplified single-to-differential mode is used to analyze the Marchand balun, and the methodology to reduce the size of Marchand balun is developed. The 60-GHz CMOS singly balanced gate mixer and diode mixer using the reduced-size Marchand rat-race hybrid are implemented to verify the design methodology. The monolithic microwave integrated circuit mixers achieve comparable performance with a compact chip size among the reported 60-GHz CMOS mixers.      

Ka-Band Monolithic GaAs Balanced Mixers

Monolithic integrated circuits have been developed on semi-insulating GaAs substrates for millimeter-wave balanced mixers. The GaAs chip is used as a suspended stripline in a cross-bar mixer circuit. A double sideband noise figure of 4.5 dB has been achieved with a monolithic GaAs balanced mixer filter chip over a 30- to 32-GHz frequency range. A monolithic GaAs balanced mixer chip has also been optimized and combined with a hybrid MIC IF preamplifier in a planar package with significant improvement in RF bandwidth and reduction in chip size. A double sideband noise figure of less than 6 dB has been achieved over a 31- to 39-GHz frequency range with a GaAs chip size of only 0.5x0.43 in. This includes the contribution of a 1.5-dB noise figure due to if preamplifier (5-500 MHz).     

Ka-band monolithic GaAs balanced mixers

Monolithic integrated circuits have been developed on semi-insulating GaAs substrates for millimeter-wave balanced mixers. The GaAs chip is used as a suspended stripline in a cross-bar mixer circuit. A double sideband noise figure of 4.5 dB has been achieved with a monolithic GaAs balanced mixer filter chip over a 30- to 32-GHz frequency range. A monolithic GaAs balanced mixer chip has also been optimized and combined with a hybrid MIC IF preamplifier in a planar package with significant improvement in RF bandwidth and reduction in chip size. A double sideband noise figure of less than 6 dB has been achieved over a 31- to 39-GHz frequency range with a GaAs chip size of only 0.5 × 0.43 in. This includes the contribution of a 1.5-dB noise figure due to IF preamplifier (5-500 MHz).     

Low-Loss and Broadband Asymmetric Broadside-Coupled Balun for Mixer Design in 0.18-$mu{hbox {m}}$ CMOS Technology

This study presents an asymmetric broadside coupled balun with low-loss broadband characteristics for mixer designs. The correlation between balun impedance and a 3D multilayer CMOS structure are discussed and analyzed. Two asymmetric multilayer meander coupled lines are adopted to implement the baluns. Three balanced mixers that comprise three miniature asymmetric broadside coupled Marchand baluns are implemented to demonstrate the applicability to MOS technology. Both a single and dual balun occupy an area of only 0.06 mm². The balun achieves a measured bandwidth of over 120%, an insertion loss of better than 4.1 dB (3 dB for an ideal balun) at the center frequency, an amplitude imbalance of less than 1 dB, and a phase imbalance of less than 5deg from 10 to 60 GHz. The first demonstrated circuit is a Ku-band mixer, which is implemented with a miniaturized balun to reduce the chip area by 80%. This 17-GHz mixer yields a conversion loss of better than 6.8 dB with a chip size of 0.24 mm². The second circuit is a 15-60-GHz broadband single-balanced mixer, which achieves a conversion loss of better than 15 dB and occupies a chip area of 0.24 mm². A three-conductor miniaturized dual balun is then developed for use in the third mixer. This star mixer incorporates two miniature dual baluns to achieve a conversion loss of better than 15 dB from 27 to 54 GHz, and occupies a chip area of 0.34 mm².     

Broad-band MMICs based on modified loss-compensation method using 0.35-/spl mu/m SiGe BiCMOS technology

Using the concept of loss compensation, novel broad-band monolithic microwave integrated circuits (MMICs), including an amplifier and an analog multiplier/mixer, with LC ladder matching networks in a commercial 0.35-mum SiGe BiCMOS technology are demonstrated for the first time. An HBT two-stage cascade single-stage distributed amplifier (2-CSSDA) using the modified loss-compensation technique is presented. It demonstrates a small-signal gain of better than 15 dB from dc to 28 GHz (gain-bandwidth product=157 GHz) with a low power consumption of 48 mW and a miniature chip size of 0.63 mm² including testing pads. The gain-bandwidth product of the modified loss-compensated CSSDA is improved approximately 68% compared with the conventional attenuation-compensation technique. The wide-band amplifier achieves a high gain-bandwidth product with the lowest power consumption and smallest chip size. The broad-band mixer designed using a Gilbert cell with the modified loss-compensation technique achieves a measured power conversion gain of 19 dB with a 3-dB bandwidth from 0.1 to 23 GHz, which is the highest gain-bandwidth product of operation among previously reported MMIC mixers. As an analog multiplier, the measured sensitivity is better than 3000 V/W from 0.1 to 25 GHz, and the measured low-frequency noise floor and corner frequency can be estimated to be 20 nV/sqrt(Hz) and 1.2 kHz, respectively. The mixer performance represents state-of-the-art result of the MMIC broad-band mixers using commercial silicon-based technologies     

Design of broad-band lumped-element baluns with inherent impedance transformation

This paper reports on a novel lumped balun topology, the second-order lattice balun, with broad-band performance. The design is based on synthetic transmission lines operating as impedance transformers. The characteristic impedance of the synthetic transmission lines may be chosen to obtain inherent impedance transformation. An analytical investigation results in closed formulas for optimum performance over a given bandwidth. It is shown that it is possible to design for equal ripple in amplitude balance and input reflection coefficient. The phase balance is theoretically perfect over the entire bandwidth. The concept is experimentally validated by a 1-GHz prototype fabricated with surface mounted chip components. It exhibits an amplitude balance better than 0.5 dB and a phase balance better than /spl plusmn/8/spl deg/ over an octave bandwidth. The effective area of the prototype is 7 /spl times/ 9 mm/sup 2/.     

A 4–41 GHz Singly Balanced Distributed Mixer Using GaAs pHEMT Technology

A broadband singly balanced distributed mixer is developed using a 0.15-mum GaAs pHEMT foundry process. It is the first time that the charge-injection approach is applied to a distributed mixer. With the advantage of charge-injection, the mixer achieves a high conversion gain with low dc consumption. The fabricated distributed mixer with an integrated broadband transformer has a compact chip size of 2mmtimes1mm. Measurement results show that the mixer achieves a conversion gain of better than 3.5dB over a broadband frequency from 4-41GHz, with a relatively low dc power consumption of 100mW     

A miniature 25-GHz 9-dB CMOS cascaded single-stage distributed amplifier

A 25-GHz complementary metal oxide semiconductor (CMOS) cascaded single-stage distributed amplifier (CSSDA) using standard 0.18-/spl mu/m CMOS technology is presented in this letter. It demonstrates the highest gain-bandwidth product (GBP) with smallest chip area reported for a fully-integrated CMOS wideband amplifier using a standard Si-based integrated circuit process. The chip size including testing pads is only 0.36mm/sup 2/, and the ratio of GBP to chip size achieves 552GHz/mm/sup 2/. This circuit is the first CSSDA realized in CMOS technology, and represents state-of-the-art performances.     

A single-chip multimode receiver for GSM900, DCS1800, PCS1900, and WCDMA

A single-chip, multimode receiver for GSM900, DCS1800, PCS1900, and UTRA/FDD WCDMA is introduced in this paper. The receiver operates at four different radio frequencies with two different baseband bandwidths. The presented chip uses a direct-conversion architecture and consists of a low-noise amplifier (LNA), downconversion mixers with on-chip local-oscillator I/Q generation, channel selection filters, and programmable gain amplifiers. In spite of four receive bands, only four on-chip inductors are used in the single-ended LNA. The repeatable receiver second-order input intercept point (IIP2) of over +42 dBm is achieved with mixer linearization circuitry together with a baseband circuitry having approximately +100-dBV out-of-band IIP2. The noise figure of the SiGe BiCMOS receiver is less than 4.8 dB in all GSM modes, and 3.5 dB in WCDMA. The power consumption from a 2.7-V supply in all GSM modes and in WCDMA mode is 42 and 50 mW, respectively. The silicon area is 9.8 mm/sup 2/ including the bonding pads.     

10-GHz Si bipolar amplifier and mixer ICs for coherent opticalsystems

Using a 30-GHz f_T silicon bipolar process, 10-GHz amplifier and mixer ICs for a multigigabit-per-second coherent optical-fiber communication system were fabricated. The dual-feedback amplifier with triple Darlington achieves a 10-GHz bandwidth and 20-dB gain. The Gilbert-cell mixer operates up to 10 GHz with a 10-dB conversion loss. The simulation technique, used for the design of these ICs includes an improved interconnect line model for the high-frequency region. The 10-GHz amplifier has a 1-mm² chip size and 210-mW power dissipation. The mixer has 2-mm² chip size and 550-mW power dissipation     

Compact 28-GHz subharmonically pumped resistive mixer MMIC using a lumped-element high-pass/band-pass balun

This work reports a novel lump-element balun for use in a miniature monolithic subharmonically pumped resistive mixer (SPRM) microwave monolithic integrated circuit. The proposed balun is simply analogous to the traditional Marchand balun. The coupled transmission lines are replaced by lump elements, significantly reducing the size of the balun. This balun requires no complicated three-dimensional electromagnetic simulations, multilayers or suspended substrate techniques; therefore, the design parameters are easily calculated. A 2.4-GHz balun is demonstrated using printed circuit board technology. The measurements show that the outputs of balun with high-pass and band-pass responses, a 1-dB gain balance, and a 5/spl deg/ phase balance from 1.7 to 2.45 GHz. The balun was then applied in the design of a 28-GHz monolithic SPRM. The measured conversion loss of the mixer was less than 11dB at a radio frequency (RF) bandwidth of 27.5-28.5 GHz at a fixed 1 GHz IF, a local oscillator (LO)-RF isolation of over 35 dB, and a 1-dB compression point higher than 9 dBm. The chip area of the mixer is less than 2.0 mm/sup 2/.     

12-GHz-Band GaAs Dual-Gate MESFET Monolithic Mixers

12-GHz-band GaAs dual-gate MESFET monolithic mixers have been developed for use in direct broadcasting satellite receivers. In order to reduce chip size, a buffer amplifier has been connected directly after a mixer IF port, instead of employing an IF matching circuit. The mixer and the buffer were fabricated on separate chips, so that individual measurements could be achieved. Chip size is 0.96X 1.26 mm for the mixer and 0.96X0.60 mm for the buffer. A dual-gate FET for the mixer, as well as a single-gate FET for the buffer, has a closely spaced electrode structure. Gate length and width are 1 µm and 320 µm, respectively. The mixer with the buffer provides 2.9+-0.4-dB conversion gain with 12.3+-0.3dB SSB noise figure in the 11.7-12.2-GHz RF band. Local oscillator (LO) frequency is 10.8 GHz. A low-noise converter was constructed by connecting a monolithic preamplifier, an image rejection filter, and a monolithic IF amplifier to the mixer. The converter provides 46.8+-1.5-dB conversion gain with 2.8+-0.2-dB SSB noise figure in the same frequency band.     

A V-band quasi-optical GaAs HEMT monolithic integrated antenna and receiver front end

A single-chip monolithic integrated V-band folded-slot antenna with two Schottky-barrier diodes and a local oscillator source is developed as a quasi-optical receiver for the first time. The monolithic microwave integrated circuit consists of a voltage-controlled oscillator (VCO), a coplanar waveguide (CPW)-to-slotline transition, a low-pass filter, a folded-slot antenna, and a 180/spl deg/ single balanced mixer. The chip is fabricated based on the 0.15-/spl mu/m GaAs high electron-mobility transistor technology and the overall chip size is 3/spl times/1.5 mm/sup 2/. A finite-difference time-domain method solver is also developed for analyzing the embedded impedance characteristics of the folded-slot antenna to design the mixer. The chip is placed on an extended hemispherical silicon substrate lens to be a quasi-optical receiver. The performance of the receiver is verified by experimental measurements. The VCO has achieved a tuning range from 61.9 to 62.5 GHz and approximately 9.3-dBm output power. The CPW-to-slotline transition has bandwidth from 50 to 70 GHz. The mixer results in 15-dB single-sideband conversion loss and the receiving patterns of the IF power are also measured.     

A 2.4-GHz dual-mode 0.18-/spl mu/m CMOS transceiver for Bluetooth and 802.11b

High-level integration of the Bluetooth and 802.11b WLAN radio systems in the 2.4-GHz ISM band is demonstrated in scaled CMOS. A dual-mode RF transceiver IC implements all transmit and receive functions including the low-noise amplifier (LNA), 0-dBm power amplifier, up/down mixers, synthesizers, channel filtering, and limiting/automatic gain control for both standards in a single chip without doubling the required silicon area to reduce the combined system cost. This is achieved by sharing the frequency up/down conversion circuits in the RF section and performing the required baseband channel filtering and gain functions with just one set of reconfigurable channel filter and amplifier for both modes. A chip implemented in 0.18-/spl mu/m CMOS occupies 4/spl times/4 mm/sup 2/ including pad and consumes 60 and 40 mA for RX and TX modes, respectively. The dual-mode receiver exhibits -80-dBm sensitivity at 0.1% BER in Bluetooth mode and at 12-dB SNR in WLAN mode.     

30-100-GHz inductors and transformers for millimeter-wave (Bi)CMOS integrated circuits

Silicon planar and three-dimensional inductors and transformers were designed and characterized on-wafer up to 100 GHz. Self-resonance frequencies (SRFs) beyond 100 GHz were obtained, demonstrating for the first time that spiral structures are suitable for applications such as 60-GHz wireless local area network and 77-GHz automotive RADAR. Minimizing area over substrate is critical to achieving high SRF. A stacked transformer is reported with S/sub 21/ of -2.5 dB at 50 GHz, and which offers improved performance and less area (30 /spl mu/m/spl times/30 /spl mu/m) than planar transformers or microstrip couplers. A compact inductor model is described, along with a methodology for extracting model parameters from simulated or measured y-parameters. Millimeter-wave SiGe BiCMOS mixer and voltage-controlled-oscillator circuits employing spiral inductors are presented with better or comparable performance to previously reported transmission-line-based circuits.     

SiGe bipolar transceiver circuits operating at 60 GHz

A low-noise amplifier, direct-conversion quadrature mixer, power amplifier, and voltage-controlled oscillators have been implemented in a 0.12-/spl mu/m, 200-GHz f/sub T/290-GHz f/sub MAX/ SiGe bipolar technology for operation at 60 GHz. At 61.5 GHz, the two-stage LNA achieves 4.5-dB NF, 15-dB gain, consuming 6 mA from 1.8 V. This is the first known demonstration of a silicon LNA at V-band. The downconverter consists of a preamplifier, I/Q double-balanced mixers, a frequency tripler, and a quadrature generator, and is again the first known demonstration of silicon active mixers at V-band. At 60 GHz, the downconverter gain is 18.6 dB and the NF is 13.3 dB, and the circuit consumes 55 mA from 2.7 V, while the output buffers consume an additional 52 mA. The balanced class-AB PA provides 10.8-dB gain, +11.2-dBm 1-dB compression point, 4.3% maximum PAE, and 16-dBm saturated output power. Finally, fully differential Colpitts VCOs have been implemented at 22 and 67 GHz. The 67-GHz VCO has a phase noise better than -98 dBc/Hz at 1-MHz offset, and provides a 3.1% tuning range for 8-mA current consumption from a 3-V supply.     

A highly linear double balanced Schottky diode S-band mixer

A high-level double balanced SiC Schottky diode mixer in SiC monolithic microwave integrated circuit (MMIC) technology has been designed, processed and characterized. The mixer is a single ended in- and output circuit with coupled transformers as baluns to enable a compact design, resulting in a total area of 2.2/spl times/2.2mm/sup 2/. The mixer has a maximum IIP/sub 3/ of 38dBm and IIP/sub 2/ of 58dBm at 3.3GHz, and a typical P/sub 1 dB/ of 23dBm in the S-band. The minimum conversion loss was 12dBm at 2.4GHz. The high power operation of the mixer shows that SiC MMIC can perform well in high microwave radiation environments.