Laser-assisted bumping for flip chip assembly

A novel laser-assisted chip bumping technique is presented in which bumps are fabricated on a carrier and subsequently transferred onto silicon chips by a laser-driven release process. Copper bumps with gold bonding layers and intermediate nickel barriers are fabricated on quartz wafers with pre-deposited polyimide layers, using UV lithography and electroplating. The bumps are thermosonically bonded to their respective chips and then released from the carrier by laser machining of the polyimide layer, using light incident through the carrier. Bumps of 60 to 85 μm diameter and 50 μm height at a pitch of 127 μm have been fabricated in peripheral arrays. Parallel bonding and subsequent transfer of arrays of 28 bumps onto test chips have been successfully demonstrated. Individual bump shear tests have been performed on a sample of 13 test chips, showing an average bond strength of 26 gf per bump     

A novel flip-chip interconnection technique using solder bumps forhigh-speed photoreceivers

A flip-chip interconnection technique using small solder bumps instead of conventional wire bonding for high-speed broadband photoreceivers is described. The technique achieves interconnection with low parasitic elements, no damage to devices, and easy assembly. A photoreceiver composed of a broadband p-i-n photodiode and a laser-speed GaAS metal-semiconductor field-effect transistor (MESFET) preamplifier connected using solder bumps that are about 26 μm in diameter, with a frequency response of over 22 GHz at 1.55 μm, is demonstrated. This confirms the effectiveness of the solder bump interconnection technique for future high-speed broadband optical modules     

Electroplated indium bump arrays and the bonding reliability

A novel electroplating indium bumping process is described,as a result of which indium bump arrays with a pitch of 100μm and a diameter of 40μm were successfully prepared.UBM(under bump metallization) for indium bumping was investigated with an XRD technique.The experimental results indicate that Ti/Pt(300(?)/200(?)) has an excellent barrier effect both at room temperature and at 200℃.The bonding reliability of the indium bumps was evaluated by a shear test.Results show that the shear strength of the ind...     

Interconnect resistance characteristics of several flip-chip bumping and assembly techniques

Several flip-chip interconnection methods were compared by measuring interconnect resistance before and after exposure to environments including pre-conditioning, 85°C/85% RH exposure, 150°C storage, and 0–100°C temperature cycling. The goal was to determine an acceptable low-cost, reliable method for bumping and assembling chips to flexible or rigid substrates using flip-chip assembly techniques. Alternative flip-chip bumping methods are compared to a traditional wafer solder bumping method. Flip-chip interconnection methods evaluated included high lead content solder, silver filled conductive adhesive, and gold stud bumps. Under bump metallurgies evaluated included bare aluminum, evaporated Cr/Cr–Cu/Cu, and electroless nickel plating.     

Compact packaging of optical and electronic components for on-board optical interconnects

An optical interconnection plate was developed in order to achieve a compact and cost-effective interconnection module for an optical data link between chips on printed circuit boards. On the silica substrate, transmission lines and solder bumps are formed on the top surface of the substrate, and polymer waveguide array with 45/spl deg/ mirror planes is formed on the back side. This optical interconnection plate technique makes the alignment procedure quite simple and economical, because all the alignment steps between the optical components can be achieved in wafer processes and a high accuracy flip-chip bonding technique. We confirmed the sufficiently high coupling efficiency and low optical crosstalk using the simplified experimental setup. Flip-chip bonding of the vertical-cavity surface-emitting laser and photodiode arrays on the top surface of the optical interconnection plate was performed using indium bumps in order to avoid thermal damage of the polymer waveguide. The fully packaged optical interconnection plate showed an optical data link at rates of 455 Mb/s. Improvement of the mirror surface roughness and the mirror angle accuracy could lead to an optical link at higher rates. In addition, the interconnection system can be easily constructed by inserting the optical interconnection plate between the processing chips or data lines requiring optical links.     

Electrical characterization of flip-chip interconnects formed using a novel conductive-adhesive-based process

Using conventional microfabrication techniques, we have developed a new, low-cost wafer bumping process that enables a high degree of control over patterning of conductive adhesive interconnects. This approach obviates the need for development of dispensing and scraping head equipment that may otherwise be required for mass fabrication of lithographically patterned adhesive bumps. Flip-chip interconnects formed using this new process offer better electrical performance as compared to those formed by squeegee-based definition techniques. This is inferred in this paper by experimentally demonstrating lower contact resistance with the polished bumps as compared to the squeegeed bumps. Furthermore, in order to study the high-speed electrical performance characteristics of these conductive adhesive bumps, a 10-GHz 1.55-/spl mu/m p-i-n photodetector fabricated in the antimonide material system was used as case study. The results from the bandwidth characterization of the polymer flip-chip-integrated detector showed minimum degradation in the high-speed performance characteristics of the detector.     

A>400 GHz fmax transferred-substrate heterojunctionbipolar transistor IC technology

We report transferred-substrate AlInAs/GaInAs bipolar transistors. A device having a 0.6 μm×25 μm emitter and a 0.8 μm×29 μm collector exhibited f_τ=134 GHz and f _max>400 GHz. A device with a 0.6 μm×25 μm emitter and a 1.8 μm×29 μm collector exhibited 400 GHz f_max 164 GHz f_τ. The improvement in f_max over previous transferred-substrate HBT's is due to improved base Ohmic contacts, narrower emitter-base and collector-base junction areas, and slightly reduced transit times. The transferred-substrate fabrication process provides electroplated gold thermal vias for transistor heat-sinking and a microstrip wiring environment on a low dielectric constant polymer substrate     

Flip-chip packaging solution for CMOS image sensor device

Chip scaled opto-electronic packaging is introduced as a cost and size effective packaging solution for mobile phone with built in camera. The chip scaled assembly includes gold bumped CMOS image sensor device and its flip-chip bonding on substrate using the anisotropic conductive material. Two types of flip-chip module were designed to have flip-chip on flex and flip-chip on glass. It is shown that well controlled bumping process of thin film deposition and wet etching gives no damage to image sensing surface during the deposition and stripping of metal film. As results, smart and high degree miniaturized image sensor module is actualized for mobile phone and the reliability test results proved the robustness of module structure having flip-chip. Solder bumping was also reviewed and successfully introduced to verify the alternative of image sensor bumping.     

Fabrication of high current and low profile micromachined inductorwith laminated Ni/Fe core

A new process for the fabrication of high current and very low profile micromachined inductors has been developed. This process involves the combination of mechanical lamination and electrodeposition of copper windings by means of LIGA-like lithography through thick epoxy photoresists. The dimension of the fabricated inductor is 16 mm×19 mm×1 mm. The fabricated inductor has an inductance value of 1.2 μH with DC saturation current of 3 A and an electrical resistance of less than 30 mΩ at 10 kHz     

Contact Resistance of Flip-Chip Joints in Wearable Electronic Textiles

Flip-chip bonding to a Cu lead frame transferred to a fabric was achieved by use of a non-conducting adhesive. Average contact resistance of the flip-chip joints was evaluated on variation of the Cu and Sn thickness of Cu/Sn bumps of size 150 × 220 μm². The total thickness of the Cu/Sn bumps was fixed at 15 μm. The average contact resistance of the flip-chip joints on the fabric was 5.4–10.8 mΩ, depending on the Sn thickness of the Cu/Sn bumps; this was lower than for flip-chip joints on a rigid Si substrate (15.6–26.5 mΩ). The average contact resistance of flip-chip joints on the fabric decreased from 10.8 mΩ to 5.5 mΩ when the chip–bump configuration was changed from 15-μm-thick Sn to 7-μm-thick Cu/8-μm-thick Sn. The contact resistance of flip-chip joints bonded with the 7-μm-thick Cu/8-μm-thick Sn bumps remained below 10 mΩ for up to 750 h in the 85°C/85% relative humidity test and even decreased to below 4 mΩ in the storage test at 125°C for up to 1000 h.     

A Fluxless and Low-Temperature Flip Chip Process Based on Insertion Technique

For heterogeneous materials assembly, the thermal expansion mismatch between the chip and the substrate is a roadblock for flip chip bonding of ultrafine-pitch $(leq 10 mu{hbox {m}})$ and large diagonal devices ( $geq$20 mm). Residual strains in bumps and device warpage have been calculated to evaluate the thermomechanical limits of a conventional flip chip soldering process using micro bumping. As a solution to overcome these limits, this paper describes a new patented flip-chip technology representing a technological breakthrough compared to conventional methods such as soldering or bonding through conductive adhesives. Electrical connections are performed by the insertion of metallic micro-tips in a ductile material. As a low-temperature process and fluxless technology, this method is adapted to fine-pitch and large devices. As a proof of concept, we present the bonding results obtained on fine-pitch large arrays of daisy chains with 500 $times$ 500 contacts and 30-$mu{hbox {m}}$ pitch. The electrical contact has been demonstrated and characterized in terms of resistance and yield.      

A new COG technique using low temperature solder bumps for LCD driver IC packaging applications

A new chip on glass (COG) technique using flip chip solder joining technology has been developed for excellent resolution and high quality liquid crystal display (LCD) panels. The flip chip solder joining technology has several advantages over the anisotropic conductive film (ACF) bonding technology: finer pitch capability, better electrical performance, and easier reworkability. Conventional solders such as eutectic Pb-Sn and Pb-5Sn require high temperature processing which can lead to degradation of the liquid crystal or the color filter in LCD modules. Thus it is desirable to develop a low temperature process below 160/spl deg/C using solders with low melting temperatures for this application. In our case, we used eutectic 58 wt%Bi-42 wt%Sn solder for this purpose. Using the eutectic Bi-Sn solder bumps of 50-80/spl mu/m pitch sizes, an ultrafine interconnection between the IC and glass substrate was successfully made at or below 160/spl deg/C. The average contact resistance of the Bi-Sn solder joints was 19m/spl Omega/ per bump, which is much lower than the contact resistance of conventional ACF bonding technologies. The contact resistance of the underfilled Bi-Sn solder joints did not change during a hot humidity test. We demonstrate that the COG technique using low temperature solder joints can be applied to advanced LCDs that lead to require excellent quality, high resolution, and low power consumption.     

Electroless remetallization of aluminum bond pads on CMOS driverchip for flip-chip attachment to vertical cavity surface emitting lasers(VCSEL's)

A method for remetallizing the bond pads of electronic chips, which are initially metallized with aluminum or aluminum alloy is presented. Application of electroless plating process for the remetallization of aluminum to a solderable gold surface can reduce the cost and complication of the widely accepted flip-chip interconnection technology. We have developed a step by step nickel/gold wafer bumping technique (remetallized bump height is 5.0 μm) for the appropriate solder (15.0 μm of In:Pb). Variation of roughness of the remetallized surface has been studied carefully. We have completed prototype research studies on test devices and successfully packaged the flip-chip bonded hybrid pair of a CMOS driver chip and a dummy structure of vertical cavity surface emitting laser (VCSEL) array. Cross section of the flip-chip solder joint is studied. Also, adhesion strength of the metal deposit is investigated     

RFID芯片超声倒装封装技术研究

超声倒装是近年来芯片封装领域中快速发展的一种倒装技术,具有连接强度高、接触电阻低、可靠性高、低温下短时完成和成本低的优势,特别适合较少凸点的RFID芯片封装。在镀Ni/Au铜基板上进行了RFID芯片超声倒装焊接实验,金凸点与镀Ni/Au铜基板之间实现了冶金结合,获得了良好的力学与电气性能,满足射频要求。     

Application of Al/PI composite bumps to COG bonding process

This work demonstrates the probing, testability and applicability of Al/PI (aluminum/polyimide) composite bumps to the chip on-glass (COG) bonding process for liquid crystal display (LCD) driver chip packaging. The experimental results showed that the thickness of Al overlayer on PI core of the bump, the location of pin contact, and the bump configuration affect bump probing testability. The bump with type IV configuration prepared in this work exhibited excellent probing testability when its Al overlayer thickness exceeded 0.8 μm. We further employed Taguchi method to identify the optimum COG bonding parameters for the Al/PI composite bump. The four bonding parameters, bonding temperature, bonding time, bonding pressure and thickness of Al overlayer are identified as 180° C, 10 s, 800 kgf/cm² and 1.4 μm, respectively. The optimum bonding condition was applied to subsequent COG bonding experiments on glass substrates containing Al pads or indium tin oxide (ITO) pads. From the results of resistance measurement along with a series of reliability tests, Al pad is found to be a good substrate bonding pad for Al/PI bump to COG process. Excellent contact quality was observed when the bumps had Al overlayer thickness over 1.1 μm. As to the COG specimens with substrate containing ITO pads, high joint resistance suggested that further contact quality refinement is necessary to realize their application to COG process     

HV‐SoP Technology for Maskless Fine‐Pitch Bumping Process

Recently, we have witnessed the gradual miniaturization of electronic devices. In miniaturized devices, flip‐chip bonding has become a necessity over other bonding methods. For the electrical connections in miniaturized devices, fine‐pitch solder bumping has been widely studied. In this study, high‐volume solder‐on‐pad (HV‐SoP) technology was developed using a novel maskless printing method. For the new SoP process, we used a special material called a solder bump maker (SBM). Using an SBM, which consists of resin and solder powder, uniform bumps can easily be made without a mask. To optimize the height of solder bumps, various conditions such as the mask design, oxygen concentration, and processing method are controlled. In this study, a double printing method, which is a modification of a general single printing method, is suggested. The average, maximum, and minimum obtained heights of solder bumps are 28.3 μm, 31.7 μm, and 26.3 μm, respectively. It is expected that the HV‐SoP process will reduce the costs for solder bumping and will be used for electrical interconnections in fine‐pitch flip‐chip bonding.     

Hybrid integration of surface-emitting microlaser chip and planaroptics substrate for interconnection applications

The bonding of a monolithic array of surface-emitting microlasers onto a glass substrate that contains a matching array of microlenses and mirrors is reported. The bonding was achieved by flip-chip solder bump bonding using indium as the solder material. The alignment precision is within ±2 μm. The optical substrate provides a simple interconnection scheme that routes the light from each laser to well defined output positions     

Increasing bondability and bonding strength of gold stud bumps onto copper pads with a deposited titanium barrier layer

A flip-chip assembly is an attractive scheme for use in high performance and miniaturized microelectronics packaging. Wafer bumping is essential before chips can be flip-bonded to a substrate. Wafer bumping can be used for mechanical-single point stud bump bonding (SBB), and is based on conventional thermosonic wire bonding. This work proposes depositing a titanium barrier layer between the copper film and the silver bonding layer to achieve perfect bondability and sufficiently strong thermosonic bonding between a stud bump and the copper pad.A titanium layer was deposited on the copper pads to prevent copper atoms from out-diffusing during thermosonic stud bump bonding. A silver film was then deposited on the surface of the titanium film as a bonding layer to increase the bondability and bonding strength for stud bumps onto copper pads. The integration of the silver bonding layer with a diffusion barrier layer of titanium on the copper pads yielded 100% bondability between the stud bump and pads. The strength of bonding between the gold bumps on the copper pads significantly exceeds the minimum average values in JEDEC specifications. The diffusion barrier layer of titanium effectively prevents copper atoms from out-diffusing to the silver bonding layer surface during thermosonic bonding, which fact can be interpreted with reference to the experimental results of energy dispersive spectrometry (EDS) and analyses of Auger depth profiles. This diffusion barrier layer of titanium efficiently provides perfect bondability and sufficiently strong bonding between a stud bump and copper pads with a silver bonding layer.     

Single chip bumping and reliability for flip chip processes

Processes of bump deposition based on mechanical procedures together with their reliability data are summarized in this paper. The stud bumping of gold, palladium, and solder is described and also a novel bumping approach for fine pitch solder deposition down to 100 μm pitches using thermosonic bonding on a modified wedge–wedge bonding machine. This wedge bumping doesn’t require a wire flame-off process step. Because of this, no active atmosphere is necessary. The minimum pad diameter which can be bumped using the solder wedge bumping is 50 μm, up to now. This bumping process is highly reproducible and therefore well-suited for different flip chip soldering applications. Palladium stud bumps provide a solderable under bump metallization. Results from aging of lead/tin solder bumps on palladium are shown. The growth of intermetallics and its impact on the mechanical reliability are investigated.     

A reliable and environmentally friendly packagingtechnology-flip-chip joining using anisotropically conductive adhesive

There is an increasing demand to move the radio base station closer to the antenna for future mobile telecommunication systems. This requires a significant reduction in weight and volume and increased environmental compatibility. This work provides an evaluation of environmental impact and reliability when using anisotropically conductive adhesives (ACA) for flip-chip joining in radio base station applications. Conventional FR-4 substrate has been used to assemble a digital ASIC chip using an anisotropically conductive adhesive and flip-chip technology. The chip has a minimum pitch of 128 μm with 7.8 mm in chip 8 and has in total 144 bumps with a bump size of 114×126 μm². Bumping was made using electroless nickel/gold technology. Bonding quality has been characterized by optical and scanning electron microscopy and substrate planarity measurement. The main parameters affecting quality are misalignment and softening of the FR-4 substrate during assembly, leading to high joint resistance. Reliability testing was conducted in the form of a temperature cycling test between -40 and ±125°C for 1000 cycles, a 125°C aging test for 100 h and a 85/85 humidity test for 500 h. The results show that relatively small resistance changes were observed after the reliability test. The environmental impact evaluation was done in the form of a material content declaration and a life cycle assessment (LCA). By using flip-chip ACA joining technology, the content of environmentally risky materials has been reduced more than ten times, and the use of precious metals has been reduced more than 30 times compared to conventional surface mount technology