High-speed low-power Darlington ECL circuit

Presents an ECL circuit with a Darlington configured dynamic current source and active-pull-down emitter-follower stage for low-power high-speed gate array application. The dynamic current source provides a large dynamic current during the switching transient to improve the power delay of the logic stage (current switch). A novel self-biasing scheme for the dynamic current source and the active-pull-down transistor with no additional devices and power in the biasing circuit is described. Based on a 0.8-μm double-poly self-aligned bipolar technology at a power consumption of 1 mW/gate, the circuit offers 28% improvement in the loaded (FI/FO=3, C_L=0.3 pF) delay and 42% improvement in the load driving capability compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed     

High-speed low-power charge-buffered active-pull-down ECI circuit

A high-speed, low-power, charge-buffered active-pull-down ECL (emitter-coupled logic) circuit is described. The circuit features a charge-buffered coupling between the common-emitter node of the switching transistors and the base of an active-pull-down n-p-n transistor. This coupling scheme provides a much larger dynamic current than what can be reasonably achieved through the capacitor coupling and a DC path to alleviate the AC-testing requirement. Furthermore, the dynamic current is utilized effectively by the logic stage, thus allowing a reduction in the power consumption of the logic stage without sacrificing the switching speed. Based on a 0.8-μm double-poly self-aligned bipolar technology at a power consumption of 1.0 mW/gate, the circuit offers 37% improvement in both the speed and load driving capability for a loaded gate compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed     

Active-pull-down nonthreshold logic BiCMOS circuits for high-speedlow-power applications

A new active-pull-down nonthreshold logic (APD-NTL) BiCMOS circuit is presented and its performance has been evaluated and compared to that of standard NTL gate. The circuit utilizes an NMOS active-pull-down emitter-follower stage. A first-order analysis has been conducted to demonstrate the NMOS-APD concept. Simulation results based on 0.6 μm BiCMOS technology indicate that at a power consumption of 1 mW/gate, the APD-NTL circuit offers 4× improvement in the load driving capability and 3.4× improvement in the speed compared to conventional NTL circuits for a load of 1 pF/gate and a logic swing of 800 mV     

High-speed low-power direct-coupled complementary push-pull ECLcircuit

This paper presents a high-speed low-power direct-coupled complementary push-pull ECL (DC-PP-ECL) circuit. The circuit features a direct-coupled pnp pull-up and npn pull-down scheme with no extra biasing circuit for the push- and pull-transistor. The bias of the pull-up pnp transistor is established entirely by direct tapping of the existing voltage levels in the current switch. The scheme provides a sharp self-terminating dynamic current pulse through the pull-up pnp transistor during the switching transient, thus completely decoupling the collector load resistor from the delay path. Based on a 0.8-μm double-poly self-aligned complementary bipolar process, the circuit offers 2.0X (2.2X) improvement in the loaded delay at 1.0 (0.5) mW/gate and 2.2X improvement in the load driving capability at 1.0 mW/gate compared with the conventional ECL circuit     

Non-quasi-static effects in advanced high-speed bipolar circuits

A detailed study on the non-quasi-state (NQS) effects in advanced high-speed bipolar circuits is presented. An NQS Gummel-Poon-compatible lumped circuit model, which accounts for carrier propagation delays across various quasi-neutral regions in bipolar devices, is implemented in the ASTAP circuit simulator. The effects are then evaluated and compared with those for the conventional Gummel-Poon model for the emitter-coupled logic (ECL) circuit, the non-threshold-logic (NTL) circuit, and various advanced circuits utilizing active-pull-down schemes. For the ECL circuit, the effect decreases with reduced power level and increased loading. For the NTL circuit, due to its front-end configuration, the effect is more significant than that for the ECL circuit but tends to increase with reduced power level. As the passive resistors (and the associated parasitic RC effect) are decoupled from the delay path and the circuit delay is made more intimately related to the intrinsic speed of the devices in various advanced active-pull-down circuits, the delay degradation due to NQS effect becomes more significant     

Capacitor-free level-sensitive active pull-down ECL circuit withself-adjusting driving capability

This paper introduces a new self-adjusting active pull-down scheme for ECL circuit. The circuit offers self-terminating dynamic pull-down action by sensing the output level rather than using traditional load-dependent capacitive coupling. No capacitor or large resistor is required, and therefore it adds no process complexity and no area penalty. Implemented in an ECL gate array in a 1.2 μm double-poly self aligned bipolar technology, the circuit offers 300-ps delay at a power consumption of 1 mW/gate under FO=1 and C_L=0.55 pF loading condition. This is a 4.4 times speed improvement over the conventional ECL circuit. Furthermore, the circuit consumes only 0.25 mW for a gate speed of 700 ps/gate, which is a 1/7.8 power reduction compared with the conventional ECL circuit. The circuit requires a regulated reference voltage, which is also studied     

On the leverage of high-fT transistors foradvanced high-speed bipolar circuits

A detailed study on the leverage of high-f_T transistors for advanced high-speed bipolar circuit applications is presented. It is shown that for the standard ECL (emitter-coupled logic) circuit, the leverage of high f_T is limited by the passive resistors (emitter-follower resistor and collector load resistor) and wire delay, especially in the low-power regime. For the standard NTL (nonthreshold logic) circuit, the leverage is higher due to its front-end configuration and lower power supply value. As the passive resistors are decoupled from the delay path in various advanced circuits utilizing active-pull-down schemes, the leverage of high F_T becomes more significant     

A self-biased feedback-controlled pull-down emitter follower forhigh-speed low-power bipolar logic circuits

A feedback-controlled active-pull-down emitter follower that is self-biased at a low steady-state current and allows the collector dotting and emitter dotting is proposed for high-speed low-power bipolar/BiCMOS digital logic circuits. The push-pull operation of this emitter follower is precisely controlled by a feedback mechanism and does not require any extra out-of-phase signal other than the emitter-follower input from the logic stage. Simulation results based on a 0.5-μm advanced Si-bipolar technology show that the pull-down delay and drive capability of a loaded 1-mW feedback-controlled pull-down ECL gate are improved to the pull-up levels, 2.7 and 10 times better than those of the conventional resistor-pull-down ECL circuit, respectively     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates

A 1.5-ns address access time, 256-kb BiCMOS SRAM has been developed. To attain this ultra-high-speed access time, an emitter-coupled logic (ECL) word driver is used to access 6-T CMOS memory cells, eliminating the ECL-MOS level-shifter time delay. The RAM uses a low-power active pull down ECL decoder. The chip contains 11-K, 60-ps ECL circuit gates. It provides variable RAM configurations and general logic functions. RAM power consumption is 18 W; chip power consumption is 35 W. The chip is fabricated by using a 0.5-μm BiCMOS process. The memory cell size is 58 μm² and the chip size is 11×11 mm     

A Power‐Efficient CMOS Adaptive Biasing Operational Transconductance Amplifier

This paper presents a two‐stage power‐efficient class‐AB operational transconductance amplifier (OTA) based on an adaptive biasing circuit suited to low‐power dissipation and low‐voltage operation. The OTA shows significant improvements in driving capability and power dissipation owing to the novel adaptive biasing circuit. The OTA dissipates only 0.4 μW from a supply voltage of ±0.6 V and exhibits excellent high driving, which results in a slew rate improvement of more than 250 times that of the conventional class‐AB amplifier. The design is fabricated using 0.18‐μm CMOS technology.     

A fully compensated active pull-down ECL circuit withself-adjusting driving capability

A new active pull-down emitter-coupled logic (ECL) circuit having full compensation against fluctuations in supply voltage and temperature is proposed. This circuit needs no capacitors but a feed-back circuit to adjust its pull-down capability to its load capacitance. The speed performance is compared between the active pull-down ECL circuit and the conventional ECL circuit using 0.8 μm SPICE parameters. The active pull-down ECL circuit is twice as fast as the conventional ECL circuit under the load capacitance of 0.8 pF with the same power dissipation. The relation between the power dissipation and the operating frequency is compared among the CMOS, the conventional ECL, and the active pull-down ECL circuits. The comparison adapts a new method in which the circuit parameters are optimized at each operating frequency. The SPICE simulation using this new method shows the conventional ECL circuit has a lower power dissipation than the CMOS circuit, even in the low operating frequency region of 100 MHz. The new active pull-down ECL circuit has the lowest power dissipation among the three circuits. The power dissipation of this circuit shows 47% lower than the CMOS circuit and 29% lower than the conventional ECL circuit at the operating frequency of 600 MHz and the load capacitance of 0.8 pF     

A 4.2-ps ECL ring-oscillator in a 285-GHz fMAX SiGetechnology

This letter reports on the room temperature operation of a conventional SiGe bipolar ECL ring oscillator with a minimum stage delay of 4.2 ps for ~250 mV single ended voltage swing. To our knowledge, this is the lowest reported delay for a gate fabricated using transistor devices. The circuit uses 0.12 × 2 μm² emitter size SiGe n-p-n transistors with a room temperature f_T of 207 GHz and f_MAX (unilateral gain extrapolation) of 285 GHz. The ring oscillator was studied as a function of various device and circuit parameters and it was found that minimum delay is more dependent on the parasitic resistance and capacitance in the n-p-n device than on pure transit time across the device     

A new carrier recovery circuit for land mobile satellitecommunication

A DCF (dual carrier filter) reverse-modulation-type carrier recovery circuit is proposed to achieve a low carrier skipping rate and satisfactory phase tracking performance for coherent detection of PSK (phase shift keying) signals in fast Rician fading channels. The proposed scheme employs both narrow and wide bandwidth carrier filters simultaneously for the reverse-modulation-type carrier recovery circuit. It is clarified by computer simulation that the Pe performance of a QPSK (quadriphase shift keying) modem employing the proposed scheme shows an improvement of 1.5 dB in required E_s/N_O at Pe=10⁴ (after Viterbi decoding (R=7/8, K=7), C/M (direct-to-multipath signal power ratio)=10 dB, interleaving size=64×64), compared with conventional coherent detection employing the reverse modulation tank-limiter scheme or the Costas loop scheme     

High-performance CMOS buffered gate modulation input (BGMI) readoutcircuits for IR FPA

A new CMOS current readout structure for the infrared (IR) focal-plane-array (FPA), called the buffered gate modulation input (BGMI) circuit, is proposed in this paper. Using the technique of unbalanced current mirror, the new BGMI circuit can achieve high charge sensitivity with adaptive current gain control and good immunity from threshold-voltage variations. Moreover, the readout dynamic range can be significantly increased by using the threshold-voltage-independent current-mode background suppression technique. To further improve the readout performance, switch current integration techniques, shared-buffer biasing technique, and dynamic charging output stage with the correlated double sampling circuit are also incorporated into the BGMI circuit. An experimental 128×128 BGMI readout chip has been designed and fabricated in 0.8 μm double-poly-double-metal (DPDM) n-well CMOS technology. The measurement results of the fabricated readout chip under 77 K and 5 V supply voltage have successfully verified both readout function and performance improvement. The fabricated chip has the maximum charge capacity of 9.5×10⁷ electrons, the transimpedance of 2.5×10⁹ Ω at 10 nA background current, and the arrive power dissipation of 40 mW. The uniformity of background suppression currents can be as high as 99%. Thus, high injection efficiency, high charge sensitivity, large dynamic range, large storage capacity, and low noise can be achieved In the BGMI circuit with the pixel size of 50×50 μm². These advantageous characteristics make the BCMI circuit suitable for various IR FPA readout applications with a wide range of background currents     

A new cryogenic CMOS readout structure for infrared focal planearray

A new current readout structure for the infrared (IR) focal-plane-array (FPA), called the switch-current integration (SCI) structure, is presented in this paper. By applying the share-buffered direct-injection (SBDI) biasing technique and off focal-plane-array (off-FPA) integration capacitor structure, a high-performance readout interface circuit for the IR FPA is realized with a pixel size of 50×50 μm². Moreover, the correlated double sampling (CDS) stage and dynamic discharging output stage are utilized to improve noise and speed performance of the readout structure under low power dissipation. In experimental SCI readout chip has been designed and fabricated in 0.8-μm double-poly-double-metal (DPDM) n-well CMOS technology. The measurement results of the fabricated readout chip at 77 K with 4 and 8 V supply voltages have successfully verified both the readout function and the performance improvement. The fabricated chip has a maximum charge capacity of 1.12×10⁸ electrons, a maximum transimpedance of 1×10⁹ Ω, and an active power dissipation of 30 mW. The proposed CMOS SCI structure can be applied to various cryogenic IR FPA's     

A high performance super self-aligned 3 V/5 V BiCMOS technologywith extremely low parasitics for low-power mixed-signal applications

A high performance BiCMOS technology, BEST2 (Bipolar Enhanced super Self-aligned Technology) designed for supporting low-power multiGHz mixed-signal applications is presented. Process modules to produce low parasitic device structures are described. The developed BiCMOS process implemented with 1 μm design rules (0.5 μm as one nesting tolerance) has achieved f_l and f_max for npn bipolar (A_e=1×2 μm²) of 23 GHz and 24 GHz at V_ce=3 V, respectively, with BV_ceo⩾5.5 volts, and βV_A product of 2400. Typical measured ECL gate delay is 48 ps/37 ps per stage (A_e=1×2 μm² ; 500 mV swing) at 0.6 mA/2.1 mA switching currents, and CMOS gate delay (gate oxide=125 Å, L_eff=0.6 μm; V_th,nch =0.45 V; V_th,pch=-0.45 V) 70 ps/stage. A BiCMOS phase-locked-loop (emitter width=1 μm; gate L_eff=0.7 μm) has achieved 6 GHz operation at 2 V power supply with total power consumption of 60 mW     

An adaptive biasing one-stage CMOS operational amplifier fordriving high capacitive loads

An adaptive biasing one-stage CMOS operational amplifier for driving high capacitive loads has been developed. The amplifier has been designed to drive liquid-crystal-displays (LCDs) in battery-supplied devices. Contradictory features like low power dissipation and high driving capability at low supply voltage are required. Complementary differential input stages provide rail-to-rail common-mode input range. With a special cross-coupled double-to-single-end conversion, a full supply output range is achieved. These improvements solve a functional problem of some existing adaptive biasing amplifiers. Simulation and measurements demonstrate good correlation and show the expected results, especially in the critical operating area     

A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy

A 7-Mb BiCMOS ECL (emitter coupled logic) SRAM was fabricated in a 0.8 μm BiCMOS process. An improved buffer with a high-level output of nearly V_CC is adopted to eliminate the DC current in the level converter circuit, and the PMOS transistor has a wide operating margin in the level converter. The configurable bit organization is realized by using a sense-amplifier switch circuit with no access degradation. A wired-OR demultiplexer for the ×1 output, having the same critical path as the ×4 output circuit, allows for the same access time between the two modes. The ×1 or ×4 mode is electrically selected by the external signal. A simplified programming redundancy technology, shift redundancy, is utilized. Address programming is performed by cutting only one fuse in the shift redundancy. The RAM operates at the ECL-10K level with an access time of 7 ns. and the power dissipation at 50 MHz is 600 mW for the × mode