A 128×128-pixel standard-CMOS image sensor with electronicshutter

A 128×128-pixel image sensor with a 20 s-10^-4 s electronic shutter has been integrated in a 1.2-μm digital CMOS technology. The pixel cell consists of four PMOS transistors and a photodiode with antiblooming suppression. Each pixel measures 24 μm by 24 μm and has a fill factor of 25%. Current is used to transfer pixel signals to the column readout amplifiers in order to minimize voltage swings on the highly capacitive column lines. Correlated double sampling is used to reduce intracolumn fixed pattern noise. The saturation voltage is 470 mV. The peak output signal to noise ratio is 45 dB, and the optical dynamic range is 56 dB. The frame transfer rate is 1.7 ms per frame     

A CMOS image sensor with analog two-dimensional DCT-basedcompression circuits for one-chip cameras

This paper presents a CMOS image sensor with on-chip compression using an analog two-dimensional discrete cosine transform (2-D DCT) processor and a variable quantization level analog-to-digital converter (ADC). The analog 2-D DCT processor is essentially suitable for the on-sensor image compression, since the analog image sensor signal can be directly processed. The small and low-power nature of the analog design allows us to achieve low-power, low-cost, one-chip digital video cameras. The 8×8-point analog 2-D DCT processor is designed with fully differential switched-capacitor circuits to obtain sufficient precision for video compression purposes. An imager array has a dedicated eight-channel parallel readout scheme for direct encoding with the analog 2-D DCT processor. The variable level quantization after the 2-D DCT can be performed by the ADC at the same time. A prototype CMOS image sensor integrating these core circuits for compression is implemented based on triple-metal double-polysilicon 0.35-μm CMOS technology. Image encoding using the implemented analog 2-D DCT processor to the image captured by the sensor is successfully performed. The maximum peak signal-to-noise ratio (PSNR) is 36.7 dB     

A signal-processing CMOS image sensor using a simple analog operation

We have developed a high-density CMOS image sensor with a normal mode and three signal-processing function modes: wide dynamic-range mode, motion-detection mode, and edge-extraction mode. Small pixel size and real-time operation are achieved by using a four-transistor and one-capacitor pixel scheme and column-parallel on-chip analog operation. The chip includes 512 (H) /spl times/384 (V) effective pixels. Each pixel has a sufficient fill factor of 24% in an area of 9.3/spl times/9.3 /spl mu/m/sup 2/. The dynamic range at the wide dynamic-range mode is a maximum 97 dB against 51 dB at the normal-readout mode. The chip consumes 79 mW, and the gain-control amplifier and 8-b analog-to-digital converter operate at 46 frames/s using a 3.3-V single power supply.     

A fully integrated low-IF CMOS GPS radio with on-chip analog image rejection

A fully integrated Global Positioning System (GPS) radio is presented. Low-IF architecture was used for a high level of integration and low power consumption. An on-chip analog image-reject filter provides 18 dB of image-noise rejection to prevent noise figure (NF) degradation. With image rejection performed in the analog radio, a single-path (nonquadrature) output was used. The integrated synthesizer only requires an off-chip phase-locked loop-filter to function. Implemented in a 0.35-/spl mu/m 2P4M CMOS process, the integrated radio has a chip area of 9.5 mm/sup 2/. The radio operates over a wide range of voltage and temperature, from 2.2 to 3.6 V and from -40/spl deg/C to +85/spl deg/C and consumes 27 mW from a 2.2-V supply. The receiver has 4 dB NF.     

General-purpose 128/spl times/128 SIMD processor array with integrated image sensor

A CMOS image sensor/processor chip fabricated in a 0.35 /spl mu/m CMOS technology is presented. The chip contains a general purpose software-programmable SIMD array of 128/spl times/128 processing elements. It executes over 20 GOPS while dissipating 240 mW of power and achieves pixel-processor density of 410 cells/mm/sup 2/. Performance and accuracy measurement results are given.     

A 1/3-in 410000-pixel CCD image sensor with feedback field-plateamplifier

The design considerations and performance of a 1/3-in format 410000-pixel interline transfer charge coupled device (CCD) (IL-CCD) image sensor are described. Some techniques have been introduced in order to shrink the pixel size to 6.4(H)×7.5(V) μm without any deterioration in dynamic range and, signal-to-noise (S/N) ratio. The photodiode structure is designed to reduce the knee effect so as to avoid an overflow of the vertical CCD (V-CCD) register up to 500 times the saturating illumination. A depleted-well CCD structure is introduced to maintain the maximum charge-handling capability of 92000 electrons/packet in the V-CCD register, and high enough transfer efficiency of the horizontal CCD (H-CCD) registers with 5-V_p-p pulse driving. A feedback field-plate amplifier (FFPA) is introduced to raise the sensitivity of the output amplifier to 16.2 μV/electron in order to obtain a large enough S/N ratio to the background noise of the peripheral circuits in a video camera     

一种新型的CMOS集成湿度传感器

利用MEMS技术，对一种新型CMOS湿度传感器进行理论分析、模拟以及结果讨论。该湿度传感器采用标准CMOS工艺制造，采用梳状铝电极结构、梳状多晶硅加热结构，衬底接地，感湿介质采用聚酰亚胺，利用商业软件Coventor进行模拟绘制出敏感电容与相对湿度的曲线图。接口电路采用开关电容电路，输出可测电压信号，利用Microsim公司的Pspice模拟电路得到相对湿度与输出电压曲线关系。     

一种新型的CMOS集成湿度传感器

利用MEMS技术 ,对一种新型CMOS湿度传感器进行理论分析、模拟以及结果讨论。该湿度传感器采用标准CMOS工艺制造 ,采用梳状铝电极结构、梳状多晶硅加热结构 ,衬底接地 ,感湿介质采用聚酰亚胺 ,利用商业软件Coventor进行模拟绘制出敏感电容与相对湿度的曲线图。接口电路采用开关电容电路 ,输出可测电压信号 ,利用Microsim公司的Pspice模拟电路得到相对湿度与输出电压曲线关系     

CMOS图像传感器新技术——C^3D

C3D(CMOS Color Captive Device)是新一代半导体成像技术,它不仅提高了像素设计技术,也改进了生产工艺.采用这种技术生产的0.25 μ mCMOS图像传感器能够在不牺牲性能的前提下增加晶体管的数量和占空因数(Fill Factor).除了增加像素设计的选择方案之外,还可实现更为复杂的功能和更低的功耗,并且在速度方面也很有优势.     

一种基于CMOS的高集成度太赫兹近场传感器

为了解决太赫兹波段近场传感器分辨率低和成本高的问题,提出了一种高图像分辨率、高集成度的传感器设计方案.该330 GHz传感器基于55 nm互补金属氧化物半导体（complementary metal oxide semiconductor,CMOS）工艺仿真实现,由330~336 GHz调谐范围的单端输出环形振荡器、宽带谐振器和功率探测器在单一硅片下集成.仿真结果表明,环形振荡器在偏置电压为2 V时达到峰值输出功率0.9 dBm@330 GHz,即1.23 mW.根据振荡器调谐范围,设计了一个宽带谐振器用于对待测物进行近场感测,通过放置不同介电常数的物体于其顶端表面,再通过探测器读出输出电压,与未放置物体时探测器的输出电压的差值即为该传感器的响应.此单片集成的传感器可以在单片上实现太赫兹照明、探测、传感以及成像功能,在未来太赫兹近场成像领域有较强的应用潜力.     

A logarithmic response CMOS image sensor with on-chip calibration

CMOS image sensors with logarithmic response are attractive devices for applications where a high dynamic range is required. Their strong point is the high dynamic range. Their weak point is the sensitivity to pixel parameter variations introduced during fabrication. This gives rise to a considerable fixed pattern noise (FPN) that deteriorates the image quality unless pixel calibration is used. In the present work a technique to remove the FPN by employing on-chip calibration is introduced, where the effect of threshold voltage variations in pixels is cancelled. An image sensor based on an active pixel structure with five transistors has been designed, fabricated, and tested. The sensor consists of 525×525 pixels measuring 7.5 μm×10 μm, and is fabricated in a 0.5-μm CMOS process. The measured dynamic range is 120 dB while the FPN is 2.5% of the output signal range     

具有视网膜仿生处理功能的CMOS图像传感器

借鉴生物视网膜进行图像采集和处理的结构及功能,设计了具有视网膜仿生片上信号处理电路的智能CMOS图像传感器(CIS)。像元内的仿生处理电路主要由自适应光接受器、滤波网络和减法运算电路3部分构成;CIS采用结构简单的空间滤波电阻网络和基于运算放大器的减法电路分别模拟水平细胞和双极细胞的功能,实现图像的边缘检测。在Chartered 0.35μm 2P4M CMOS工艺参数下,对各单元电路及6×6 CIS阵列进行仿真。     

A high-sensitivity CMOS image sensor with gain-adaptive column amplifiers

A high-sensitivity CMOS image sensor using gain-adaptive column amplifiers is presented and tested. The use of high gain for the column amplifier reduces input-referred random noise, and when coupled with a column-based digital noise cancellation technique, also reduces fixed pattern noise. An experimental application of the circuit using 0.25-/spl mu/m CMOS technology with pinned photodiodes gave an rms random noise of 263 /spl mu/V and an rms fixed pattern noise of 50 /spl mu/V.     

A CMOS image sensor with a double-junction active pixel

A CMOS image sensor that employs a vertically integrated double-junction photodiode structure is presented. This allows color imaging with only two filters. The sensor uses a 184*154 (near-QCIF) 6-transistor pixel array at a 9.6-/spl mu/m pitch implemented in 0.35-/spl mu/m technology. Results of the device characterization are presented. The imaging performance of an integrated two-filter color sensor is also projected, using measurements and software processing of subsampled images from the monochrome sensor with two color filters.     

CMOS integrated silicon pressure sensor

The sensor described includes a four-arm piezoresistance bridge circuit, an amplifier, and a bridge excitation circuit. This circuit is used to stabilize changes in sensitivity due to variations in temperature and supply voltage. The sensor was fabricated using a self-aligned double-poly Si gate p-well CMOS process combined with an electrochemical etch-stop technique using N/SUB 2/H/SUB 4/-H/SUB 2/O anisotropic etchant for the thin-square diaphragm formation. The silicon wafer was electrostatically adhered to a glass plate to minimize thermally induced stress. Less than a /spl plusmn/0.5% sensitivity shift and less than a /spl plusmn/5-mV offset shift were obtained in the 0-70/spl deg/C range, with a 1-V/kg/cm/SUP 2/ pressure sensitivity. By using a novel excitation technique, a sensitivity change of less than /spl plusmn/1.5% under a /spl plusmn/10% supply voltage variation was also achieved.     

CMOS image sensor with mixed-signal processor array

We present a single-chip integration of a CMOS image sensor with an embedded flexible processing array and dedicated analog-to-digital converter. The processor array is designed to perform convolution and transformation algorithms with arbitrary kernels. It has been designed to carry out the multiplication of analog image data with given digital kernel coefficients and to add up the results. The processor array is an analog implementation of a highly parallel architecture which is scalable to any desired sensor resolution while preserving video-rate operation. A prototype implementation has been realized in a 0.6-/spl mu/m CMOS technology. Switched current technique has been applied to obtain compact and robust circuits. The prototype's sensor resolution is 64 /spl times/ 128 pixels. The processor array occupies a small chip area and consumes only a small percentage of the power (250 /spl mu/W) of the whole image sensor.     

A time-to-first spike CMOS image sensor with coarse temporal sampling

Conventional voltage-based CMOS image sensors inherently have a dynamic range of about 60 dB. To extend the dynamic range, a two-degree of freedom time-based CMOS image sensor is proposed. Instead of reading analog voltages off chip, a time representation is used to record when the photodetector voltage passes a timing-varying threshold. The time measurements are combined with the reference voltage waveform to reconstruct the image. Experimental results on a prototype 32 × 32 pixel array CMOS image sensor verify that the two-degree of freedom sampling technique is feasible for ultra-wide dynamic range imaging. A measured 115 dB dynamic range at 30 fps is obtained. Qiang Luo received the B.S. (with honor) and M.S. degrees in electrical engineering from Fudan University, Shanghai, China, in 1995 and 1998, respectively, and the Ph.D. degree in electrical engineering from University of Florida, Gainesville, FL, in 2002. In 2001, he was with Texas Instruments Inc., Dallas, TX, where he was an intern engineer working on ultra-wide dynamic range CMOS image sensors. From 2002 to 2004, he was with National Semiconductor Corporation, Santa Clara, CA, where he was a staff circuit design engineer and worked on the design of high performance CMOS image sensors. He is currently with the Marvell Semiconductor Inc, Sunnyvale, CA, where he is working on the development of advanced DVD servo IC. His research interests include high-speed mixed-signal IC design, CMOS image sensors, DVD servo IC and device physics. Dr. John G. Harris received his BS and MS degrees in Electrical Engineering from MIT in 1983 and 1986. He earned his PhD from Caltech in the interdisciplinary Computation and Neural Systems program in 1991. After a two-year postdoc at the MIT AI lab, Dr Harris joined the Electrical and Computer Engineering Department at the University of Florida (UF). He is currently an associate professor and leads the Hybrid Signal Processing Group in researching biologically-inspired circuits, architectures and algorithms for signal processing. Dr. Harris has published over 100 research papers and patents in this area. He co-directs the Computational NeuroEngineering Lab and has a joint appointment in the Biomedical Engineering Department at UF. Zhiliang J. Chen received Ph.D. degree in electrical engineering from University of Florida in 1994. From 1994 to 2004, he was with Texas Instruments where he worked as Senior Member of Technical Staff and Design Branch Manager. In 2002 he was expatriated to COMMIT, a Texas Instruments JV company in China, as director of RF & Analog Base Band department. In 2004, he left Texas Instrument and found On-Bright (Shanghai) Corporation where he serves as president of the company. Dr. Chen currently held 22 US patents and has published morn than 10 journal papers. He was a recipient of the Best Paper Award from the 1997 ESD/EOS symposium.     

128×128 element PtSi infrared CCD image sensor

A new 128×128 element PtSi Schottky barrier infrared image sensor with ITCCD readout structure and PtSi thin film optical cavity detector structure has been fabricated,which has 50μm×50 μm pixels,a fill factor of 40 percent,the nonuniformity of 5% or less and the dynamic range of over or equal to 50 dB.The noise equivalent temperature difference is 0.2 K with f/1.0 optics at 300 K background. In this paper,the principle of operation,design consideration and fabrication technology for the device are described.     

CMOS active pixel image sensor

A new CMOS active pixel image sensor is reported. The sensor uses a 2.0 μm double-poly, double-metal foundry CMOS process and is realized as a 128×128 array of 40 μm×40 μm pixels. The sensor features TTL compatible voltages, low noise and large dynamic range, and will be useful in machine vision and smart sensor applications     

Smart CMOS image sensor arrays

In this paper, we present several smart image sensor arrays intended for various applications. We discuss the realization of image sensors in CMOS technology and show some examples of one-dimensional (1-D) and two-dimensional (2-D) smart image arrays