Potential design and transport property of 0.1-μm MOSFET withasymmetric channel profile

This paper describes potential design and transport property of a 0.1-μm n-MOSFET with asymmetric channel profile, which is formed by the tilt-angle ion-implantation after gate electrode formation. The relation between device performance and transport property of the asymmetric 0.1-μm device is explored by Monte Carlo simulations, and measured electrical characteristics. The self-consistent Monte Carlo device simulation coupled with a process simulator reveals higher electron velocity at the source end of the channel and velocity overshoot at the source side of the channel, and the smaller high-energy tail of the distribution in the drain. This transport property creates high drain current, large transconductance, and low substrate current of the 0.1-μm n-MOSFET with asymmetric channel profile     

Proposal of a partial-ground-plane (PGP) silicon-on-insulator (SOI)MOSFET for deep sub-0.1-μm channel regime

This letter proposes a new device structure which is called the “partial-ground-plane (PGP) silicon-on-insulator (SOI) MOSFET.” The PGP SOI MOSFET minimizes the short-channel effect (SCE) compared to the conventional single-gate (SG) SOI MOSFET because the gate-induced field in the SOI layer is held high by the PGP region. This results in a lower stand-by leakage current. The PGP SOI MOSFET also shows much better switching performance and extremely high analog performance because of its smaller parasitic capacitance compared to the conventional ground-plane (GP) device. Thus, it is shown that the PGP SOI MOSFET is a promising candidate for future deep-sub-0.1-μm mixed-mode LSIs     

High transconductance and velocity overshoot in NMOS devices at the0.1-μm gate-length level

Transport properties are investigated in self-aligned NMOS devices with gate lengths down to 0.07 μm. Velocity overshoot was observed in the form of the highest transconductances measured to date in Si FETs, as well as in the trend of the transconductance with gate length. The measured transconductance reached 910 μS/μm at liquid-nitrogen temperature and 590 μS/μm at room temperature. Velocity overshoot, by making such transconductances possible, should extend the value of miniaturization to dimensions that are smaller than what was commonly assumed to be worthwhile to pursue     

A 0.1-μm delta-doped MOSFET fabricated with post-low-energyimplanting selective epitaxy

A simple fabrication technology for delta-doped MOSFETs, named post-low-energy implanting selective epitaxy (PLISE) is presented. The PLISE technology needs no additional photo-lithography mask, deposition step or etching step even for CMOS devices. The only additional step is growing undoped epitaxial channel layers by UHV-CVD after the channel implantation. With this technology, delta-doped NMOSFETs with 0.1-μm gate length were successfully fabricated. By optimizing the epi-layer thickness and the channel doping level, short-channel effects are suppressed enough to achieve 0.1-μm gate length. Moreover, the junction capacitance at zero bias is reduced by 50%     

Characteristics including electron velocity overshoot for0.1-μm-gate-length GaAs SAINT MESFET's

Short-channel effects, substrate leakage current, and average electron velocity are investigated for 0.1-μm-gate-length GaAs MESFETs fabricated using the SAINT (self-aligned implantation for n⁺-layer technology) process. The threshold-voltage shift was scaled by the aspect ratio of the channel thickness to the gate length ( a/L_g). The substrate leakage current in a sub-quarter-micrometer MESFET is completely suppressed by the buried p layers and shallow n⁺-layers. The average electron velocity for 0.1- to 0.2-μm-gate-length FETs is estimated to be 3×10⁶ cm/s from the analysis of intrinsic FET parameters. This high value indicates electron velocity overshoot. Moreover, a very high f_T of 93.1 GHz has been attained by the 0.1-μm SAINT MESFET     

Reduction of hot-carrier generation in 0.1-μm recessed channelnMOSFET with laterally graded channel doping profile

To investigate the substrate current characteristics of a recessed channel structure with graded channel doping profile, we have fabricated and simulated the Inverted-Sidewall Recessed-Channel (ISRC) nMOSFET and compared it with a conventional planar nMOSFET. Experimentally, the ISRC nMOSFET shows about 30% reduction of substrate current, even though the drain current is almost the same. At 0.12-μm channel length, the I _SUB/I_DS value of the conventional nMOSFET is measured to be 1.68 times higher than that of the ISRC nMOSFET. Also, using simulation, it is verified that the reduction of electric field at the drain junction of ISRC nMOSFET results from the graded channel doping profile, not from the recessed channel structure     

Suspended SOI structure for advanced 0.1-μm CMOS RF devices

Modern silicon-on-insulator (SOI) technology and 0.1-μm-channel-length complementary metal oxide silicon (CMOS) devices make it possible to fabricate high-performance RF devices by using standard Si ULSI processes. Using the buried oxide layer of an SOI wafer as an etching stopper, we were able to integrate a suspended inductor, with high-inductor resonance-frequency of 19.6 GHz, and high-performance 0.1-μm CMOS devices. Moreover, we experimentally show that this suspended CMOS has acceptable short-channel immunity. Using two-dimensional (2-D) simulation, we clarify that the gate-potential spread sufficiently suppresses the potential shifts, which results in good short-channel characteristics     

On “effective channel length” in 0.1-μm MOSFETs

The conventional, 1-D definition of “effective channel length” (L_eff) is examined in light of the spatial dependence of channel sheet resistance in 0.1-μm MOSFETs calculated from a 2-D device model. For short-channel devices, the sheet resistance deviates significantly from the uniform, long-channel behavior that L _eff in general is different from the “metallurgical channel length”, L_met. While geometrical (charge-sharing) effects tend to make L_eff slightly shorter than L_met, lateral source-drain doping gradients, especially when coupled with retrograde channel doping, can make L_eff substantially longer than L_met. The latter might help explain the apparent “excess” short channel effect often observed in 0.1-μm CMOS devices     

A novel 0.1 μm MOSFET structure with inverted sidewall andrecessed channel

To solve the problems of trade-off between the short channel effect and the performance enhancement of sub-quartermicrometer MOSFETs, we have developed a recessed channel MOSFET structure called ISRC (Inverted-Sidewall Recessed-Channel). The oxide thickness is 4 nm and the effective channel length is 0.1 μm, which is the smallest Si-MOSFET ever reported in the recessed channel structures. The maximum saturation transconductance at V_D=2 V is 446 mS/mm for the 0.1 μm n-channel device. The threshold voltage roll-off is kept within 64 mV when the gate length varies from 1.4 μm to 0.1 μm and good subthreshold characteristics are achieved for 0.1 μm channel device     

Threshold voltage sensitivity of 0.1 μm channel lengthfully-depleted SOI NMOSFET's with back-gate bias

We found threshold voltage sensitivity to silicon thickness variation in 0.1 μm channel length fully-depleted SOI NMOSFET's can be reduced with lightly-doped channel and back-gate bias. However, after the back-interface is accumulated, the reduction is small and threshold voltage roll-off due to high drain bias increases     

Effects of silicon layer properties on device reliability for0.1-μm SOI n-MOSFET design strategies

We employ an advanced simulation method to investigate the effects of silicon layer properties on hot-electron-induced reliability for two 0.1-μm SOI n-MOSFET design strategies. The simulation approach features a Monte Carlo device simulator in conjunction with commercially available process and device simulators. The two channel designs are: 1) a lightly-doped (10¹⁶ cm^-3) channel and 2) a heavily-doped (10¹⁸ cm^-3) channel. For each design, the silicon layer thicknesses (T_Si) of 30, 60, and 90 nm are considered. The devices are biased under low-voltage conditions where the drain voltage is considerably less than the Si/SiO₂ barrier height for electron injection. A comparative analysis of the Monte Carlo simulation results shows that an increase in T_Si results in decreasing hot electron injection into the back oxide in both device designs. However, electron injection into the front oxide exhibits opposite trends of increasing injection for the heavily-doped channel design and decreasing injection for the lightly-doped channel design. These important trends are attributed to highly two-dimensional electric field and current density distributions. Simulations also show that the lightly-doped channel design is about three times more reliable for thick silicon layers. However, as the silicon layer is thinned to 30 nm, the heavily-doped channel design becomes about 10% more reliable instead     

Modeling of 0.1-µm MOSFET on SOI structure using Monte Carlo simulation technique

Simulation of a 0.1-µm MOSFET's characteristics using the Monte Carlo method is introduced in this paper. The studied device is a 0.1-µm MOSFET on an ultrathin nearly intrinsic SOI structure that is thought to be useful to suppress short-channel effects. To carry out the calculation, intravalley scattering with acoustic phonon and intervalley inelastic scattering have been taken into account in our model. Surface roughness scattering has also been considered in a particle manner using a classical model, which is a combination of both specular reflection and diffused scattering. In order to take the avalanche breakdown phenomena into account, a two-carrier many-particle Monte Carlo method has been used here. We proposed a new model for the impact ionization probability, and also for the velocity distribution of both the primary electron and the generated electron-hole pairs in this paper.     

A new 0.25-μm recessed-channel MOSFET with selectivelyhalo-doped channel and deep graded source/drain

To improve the performance and reliability of deep submicron MOS devices, a gate-recessed MOSFET (GR-MOSFET), which has a selectively halo-doped recessed channel and a deep graded source/drain formed without counterdoping, is proposed. The GR-MOS structure, which adopts a new doping concept, eliminates the tradeoff between drain-induced barrier lowering (DIBL) and hot-carrier effect, which are important to deep submicron device design. It also reduces the V_T lowering effect and the lateral electric field at the drain. A 0.25-μm GR-MOSFET with a 10-nm gate oxide has exhibited 15% higher transconductance and 10% increased saturation current at V_D=V _G=3.3 V, 1 V higher BV_DSS, and six times less substrate current compared with an LDD-MOSFET of the same device dimensions     

Simulation of sub-0.1-μm MOSFETs with completely suppressedshort-channel effect

MOSFETs in the sub-0.1-μm regime were investigated using a nonplanar device simulator CADDETH-NP. It was found that even in this regime, the short-channel effect can be suppressed in grooved gate MOSFETs because of the concave corner of the gate insulator. MOSFETs with a gate length of 0.05 μm or less with no threshold voltage lowering can be made by optimizing the concave corner radius, junction depths, and channel doping     

4- and 13-GHz tuned amplifiers implemented in a 0.1-μm CMOStechnology on SOI, SOS, and bulk substrates

Four- and 13-GHz tuned amplifiers have been implemented in a partially scaled 0.1-1 μm CMOS technology on bulk, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS) substrates. The 4-GHz bulk, SOI, and SOS amplifiers exhibit forward gains of 14, 11, and 12.5 dB and F_min's of 4.5 (bulk) and 3.5 db (SOS). The 13-GHz SOS and SOI amplifiers exhibit gains of 15 and 5.3 dB and F_unn's of 4.9 and 7.8 dB. The 4-GHz bulk amplifier has the highest resonant frequency among reported bulk CMOS amplifiers, while the 13-GHz SOS and SOI amplifiers are the first in a CMOS technology to have tuned frequencies greater than 10 GHz. These and other measurement results suggest that it may be possible to implement 20-GHz tuned amplifiers in a fully scaled 0.1-1 μm CMOS process     

Relaxation of acceptance limits (RAL): a global approach forparametric yield control of 0.1-μm deep submicron MOSFET devices

An alternative method to fixed quality acceptance limits for in-line yield control is proposed. Our study is based on a sensitivity analysis, which has revealed that conventional parametric yield-control techniques using fixed in-line acceptance (tolerance) limits, as traditionally used in semiconductor manufacturing, are not efficient in deep submicron-size devices     

Counter doping into uniformly and heavily doped channel region ofsub-0.1 μm SOI MOSFETs

We proposed counter doping into a heavily and uniformly doped channel region of SOI MOSFETs. This enabled us to suppress the short channel effects with proper threshold voltage V_th and to eliminate parasitic edge or back gate transistors. We derived a model for V_th as a function of the projected range, Rp and dose, Φ_D, of the counter doping, and showed that V_th is invariable even when the as-implanted counter doping profile redistributes. Using this technology, we demonstrated a V_th roll-off free 0.075 μm-L_Geff nMOSFET with low off-state current     

A CMOS mainframe processor with 0.5-μm channel length

A processor chip set with IBM/370 architecture is implemented on five CMOS VLSI chips containing 2.8 million transistors with an effective channel length of 0.5 μm. The chip set consists of the instruction and the fixed-point processor, two cache chips with 16 KB of data and instructions, and the floating-point processor. The chips are implemented in a 1.0-μm technology with three layers of metal. An automatic design system based on the sea-of-gates technique and the standard cell approach was used. The worst-case operating frequency of the chip set is 35 MHz (typically 50 MHz). Four chips of the processor are packaged on a ceramic multichip module. Level-sensitive scan design, built-in self-test, and parity check guarantee high test coverage and reliability     

0.1μm SOI槽栅pMOS器件特性

制造了栅长0.1μm,栅氧厚度5.6nm,栅槽180nm的SOI槽栅pMOSFET.给出了器件的转移特性和输出特性.在Vds=-1.5V时,其饱和漏电流为380μA,关态泄漏电流为1.9nA;在Vds=-0.1V下的亚阈值斜率为115mV/dec,DIBL因子为70.7mV/V.实验结果表明,0.1μm SOI槽栅pMOSFET比同尺寸体硅槽栅pMOSFET拥有更好的电流驱动能力和亚阈值特性.     

0.1μm SOI槽栅pMOS器件特性

制造了栅长0.1μm,栅氧厚度5.6nm,栅槽180nm的SOI槽栅pMOSFET.给出了器件的转移特性和输出特性.在Vds=-1.5V时,其饱和漏电流为380μA,关态泄漏电流为1.9nA;在Vds=-0.1V下的亚阈值斜率为115mV/dec,DIBL因子为70.7mV/V.实验结果表明,0.1μm SOI槽栅pMOSFET比同尺寸体硅槽栅pMOSFET拥有更好的电流驱动能力和亚阈值特性.