A new MOSFET with large-tilt-angle implanted drain (LATID)structure

The LATID device features the elimination of the sidewall spacer and self-alignment of n^- large tilt angle (LAT) and n⁺ implants to the same gate edge. Even without a spacer and a heavy drive-in, the LATID can achieve both a sufficiently long L_n- and an n⁺ gate overlap. The LATID achieves improved current drive by more than 50% and improved hot-carrier lifetime by more than three orders of magnitude as compared with a conventional lightly doped drain. The LATID technique is most promising for applications to submicrometer ULSI under 5-V operation     

LDD MOSFETs using disposable sidewall spacer technology

A technology for fabricating lightly doped drain (LDD) MOSFET devices based on disposable sidewall spacers is presented. Using a thin polysilicon buffer layer between the low-temperature oxide (LTO) sidewall spacers and the oxidized polysilicon gate, a single masking step can be used to form the n^- and n⁺ or p^- and p⁺ source/drain implants for the NMOS and PMOS devices, respectively. In addition, the LTO sidewall spacers may be removed by a wet HF strip, thus minimizing additional damage to the gate oxide that may be caused by reactive ion etch removal. The disposable sidewall spacer technology is easily adaptable to a CMOS process as demonstrated by the fabrication of a 4 K×4 SRAM circuit using a conventional 1.5-μ CMOS technology     

A new p-channel MOSFET with large-tilt-angle implanted punchthroughstopper (LATIPS)

A buried-channel p-MOSFET with a large-tile-angle implanted punchthrough stopper (LATIPS) is described. In this device the n⁺ LATIPS region was successfully realized adjacent to the p⁺ source/drain, even without a sidewall spacer, by taking advantage of the n⁺ large-tilt-angle implant. In spite of the relatively deep p⁺ junction of 0.2-μm depth and the low n-well concentration of 1×10¹⁶ cm^-3, the 0.5-μm LATIPS device (with corresponding channel length of 0.3 μm) achieved high punchthrough resistance, e.g. a low subthreshold swing of 95 mV/decade with a high transconductance of 135 mS/mm     

Disposable polysilicon LDD spacer technology

An advanced 0.5-μm CMOS disposable lightly doped drain (LDD) spacer technology has been developed. This 0.5-μm CMOS technology features surface-channel LDD NMOS and PMOS devices, n⁺/p⁺ poly gates, 125-A-thick gate oxide, and Ti-salicided source/drain/gate regions. Using only two masking steps, the NMOS and PMOS LDD spacers are defined separately to provide deep arsenic n⁺ regions for lower salicided junction leakage, while simultaneously providing shallow phosphorus n^- and boron p^- regions for improved device short-channel effects. Additionally, the process allows independent adjustment of the LDD and salicide spacers to optimize the LDD design while avoiding salicide bridging of source/drain to gate regions. The results indicate extrapolated DC hot-carrier lifetimes in excess of 10 years for a 0.3-μm electrical channel-length NMOS device operated at a power-supply voltage of 3.3 V     

Hot-carrier degradation of single-drain PMOSFETs with differingsidewall spacer thicknesses

The effect of the sidewall spacer thickness on the hot-carrier degradation of buried-channel PMOS transistors with a sidewall-offset single drain structure was studied. At the bias stress condition of maximum gate current, a large degradation was observed for transistors with no overlap between gate and drain. Results of measurements using the charge-pumping technique suggest that trapping of a large number of electrons in the CVD SiO₂ sidewall spacer is responsible for the enhanced degradation. This was also confirmed by the measurement of the threshold voltage as a function of drain bias     

Design for suppression of gate-induced drain leakage in LDD MOSFETsusing a quasi-two-dimensional analytical model

A systematic study of gate-induced drain leakage (GIDL) in single-diffusion drain (SD), lightly doped drain (LDD), and fully gate-overlapped LDD (GOLD) NMOSFETs is described. Design curves quantifying the GIDL dependence on gate oxide thickness, phosphorus dose, and spacer length are presented. In addition, a new, quasi-2-D analytical model is developed for the electric field in the gate-to-drain overlap region. This model successfully explains the observed GIDL dependence on the lateral doping profile of the drain. Also, a technique is proposed for extracting this lateral doping profile using the measured dependence of GIDL current on the applied substrate bias. Finally, the GIDL current is found to be much smaller in lightly doped LDD devices than in SD or fully overlapped LDD devices, due to smaller vertical and lateral electric fields. However, as the phosphorus dose approaches 10¹⁴/cm², the LDD and fully overlapped LDD devices exhibit similar GIDL current     

P-MOSFET's with ultra-shallow solid-phase-diffused drain structureproduced by diffusion from BSG gate-sidewall

A p-MOSFET structure with solid-phase diffused drain (SPDD) is proposed for future 0.1-μm and sub-0.1-μm devices. Highly doped ultrashallow p⁺ source and drain junctions have been obtained by solid-phase diffusion from a highly doped borosilicate glass (BSG) sidewall. The resulting shallow, high-concentration drain profile significantly improves short channel effects without increasing parasitic resistance. At the same time, an in situ highly-boron-doped LPCVD polysilicon gate is introduced to prevent the transconductance degradation which arises in ultrasmall p-MOSFETs with lower process temperature as a result of depletion formation in the p⁺-polysilicon gate. Excellent electrical characteristics and good hot-carrier reliability are achieved     

An ITLDD CMOS process with self-aligned reverse-sequenceLDD/channel implantation

An advanced inverse-T LDD (ITLDD) CMOS process has been developed. This process features self-aligned lightly-doped-drain/channel implantation for improved hot-carrier protection. Selective polysilicon deposition is used to define the thick polysilicon gate regions with a thin polysilicon gate regions overlying the lightly doped n^- and p⁺ regions. Since the thick poly gate regions are defined by nitride sidewall spacers, optical lithography can be used to define sub-half-micrometer gate length MOSFETs. The LDD implants are performed after the n⁺ and p⁺ implants are annealed, resulting in MOSFET's with improved short-channel behavior due to the smaller lateral source/drain diffusion     

Performance and reliability evaluation of high dielectric LDDspacer on deep sub-micrometer LDD MOSFET

High dielectric LDD spacer has been proposed to achieve both reliability and performance improvement on the scaled LDD MOSFET's. However, the sidewall polyoxide and spacer bottom oxide required for process reliability issue will adversely limit the DC performance improvement gained by using high dielectric LDD spacer. AC performance is evaluated by the transconductance cutoff frequency determined by the transconductance, G_M and total gate capacitance, C_GG . For deep-submicron MOSFET's, the dominance of gate to source/drain overlap capacitance in C_GG has significant impact on the AC performance. The increase of C_GG due to the enhanced fringe field from high dielectric LDD spacer significantly dominates over the increase of transconductance, and then deteriorates the AC performance. As the reliability issue is concerned, the key doping profile, N^- source/drain lateral diffusion profile was obtained from the two dimensional process simulator SUPREM-IV corresponding to wide range of LDD N^- doses. The optimized N ^- dose designed for hot carrier reliability issue (under V _GS-V_T=0.5 V_DS operation) is located around 2×10¹³ cm^-2 for both conventional LDD (denoted as OLDD in this paper) and high dielectric LDD (HLDD) devices. However, the improvement achieved by using HLDD instead of OLDD devices is then turned out to be insignificant under this optimized N^- dose condition     

Deep-submicrometer large-angle-tilt implanted drain (LATID)technology

Deep-submicrometer large-angle-tilt implanted drain (LATID) technology is described. It is found by Monte Carlo process simulation and SIMS measurements that a sufficiently long n^- region can be formed under the gate by taking advantage of large-angle-tilt implant and successfully without ion channeling by taking care of the implant direction. A design that offsets the n⁺ implant by sidewall spacers to suppress the n⁺-gate overlap to zero while keeping the n^- region fully overlapped with the gate is found to be crucial for improved performance and reliability. The device performance, such as current drivability and short-channel effects, is described, and the circuit speed is investigated. Hot-carrier effects such as lateral electric field and device lifetime over a wide range of drain structures are also investigated. The tradeoff between device performance and hot-carrier reliability in deep-submicrometer LATID FETs is discussed     

Simple gate-to-drain overlapped MOSFETs using poly spacers for highimmunity to channel hot-electron degradation

Short n-channel MOSFETs with permanent poly spacers over the lightly doped drain (LDD) region are demonstrated to be effective in increasing the resistance to channel hot-electron-induced degradation. The hot-electron lifetime of the poly-spacer devices is two to three orders of magnitude longer than that of a conventional oxide-spacer device. This improvement is entirely due to the reduced electron trapping in the gate oxide under the sidewall spacer. The disadvantages of the poly-spacer devices, higher gate-to-drain overlap capacitance and weaker gate oxide integrity, can both be minimized to within 20% of those of the oxide-spacer device by a short oxidation before the formation of the poly spacer     

Device-Optimization Technique for Robust and Low-Power FinFET SRAM Design in NanoScale Era

In this paper, we propose a methodology to model and optimize FinFET devices for robust and low-power SRAMs. We propose to optimize the gate sidewall offset spacer thickness to simultaneously minimize leakage current and drain capacitance to on-current ratio in FinFET. With the source/drain extension doping controlled at the outer edges of the spacer, the thickness of the spacer determines the channel length. Optimization reduces the sensitivity of the device threshold voltage to the fluctuations in silicon thickness (by 32%) and gate length (by 73%). Our analysis shows that optimization of spacer thickness results in 65% reduction in SRAM cell leakage and improves cell read-failure probability (by 200 X) compared to conventional FinFET SRAM. Access time of an SRAM cell designed with optimized devices is comparable to conventional SRAM. We also compared the optimized-spacer-thickness SRAM cell with one designed using longer gate length and minimum-spacer-thickness transistors. The long-channel-device-based SRAM cell is marginally robust than optimized SRAM; however, increased gate-edge direct-tunneling leakage and parasitic capacitances degrade the power consumption and access time.     

The effect of the elevated source/drain doping profile onperformance and reliability of deep submicron MOSFETs

Deep submicron NMOSFETs with elevated source/drain (ESD) were fabricated using self-aligned selective epitaxial deposition and engineered ion implanted profiles in the elevated layers, Deeper source/drain (S/D) junctions give rise to improved drive current over shallower profiles when the same spacer thickness and LDD doping level are used, Shallower junctions, especially with the heavily-doped S/D residing in the elevated layer, give better immunity to drain-induced-barrier lowering (DLBL) and bulk punchthrough. Tradeoffs between short-channel behavior and drive current with regard to S/D junction depth and spacer thickness were further studied using process/device simulations to cover a broader range of structure parameters. Despite the existence of epi facets along the sidewall spacers, the elevated S/D could be used as a sacrificial layer for silicidation, without degradation of the low-leakage junctions. The effects of the elevated S/D doping profile on substrate current and hot-electron-induced degradation were measured and analyzed. The simulated results were used, for the first time, to define the range of spacer thickness and LDD doses that are required in order for the lightly-doped region in the elevated S/D to effectively suppress the lateral electric field     

Effect of collector design on the d.c. characteristics of In0.49Ga0.51P/GaAs heterojunction bipolar transistors

InGaP/GaAs heterojunction bipolar transistors with various collector structures are compared. The dependence of d.c. device characteristics on the thickness of the n⁻ GaAs spacer in the collector of composite collector devices is presented. Results indicate that the spacer thickness significantly affects the performance of the transistor. An n⁺ doping spike on the InGaP side of the collector heterojunction is included in the collector design of the composite collector devices. Standard single-heterojunction d.c. results are compared to abrupt double- and composite collector heterojunction devices. Optimization of the spacer thickness, in conjunction with the n⁺ doping spike, eliminates most of the detrimental effects associated with a double-heterojunction device while retaining the beneficial properties of a wide-gap collector. As expected, the composite collector structure produces devices with higher breakdown voltages and lower offset voltages than single heterojunction devices. In addition, optimizing the spacer thickness can reduce the collector current saturation voltage of the composite collector device below that of a single-heterojunction device. These characteristics make composite collector heterojunction bipolar transistors ideal candidates for high power microwave device applications.     

2.4F2 memory cell technology with stacked-surroundinggate transistor (S-SGT) DRAM

This paper proposes 2.4F² memory cell technology with stacked-surrounding gate transistor (S-SGT) DRAM. One unit of the S-SGT DRAM is formed by stacking several SGT-type cells in series vertically. The SGT-type cell itself arranges gate, source, drain and plate on a silicon pillar vertically. Both gate and plate electrode surround the silicon pillar. Subsequently applied trench etching and sidewall spacer formation during S-SGT DRAM formation causes a step-like silicon pillar structure. Due to these steps, gate, plate and diffusion layer in one S-SGT DRAM unit are fabricated vertically by a self-aligned process. The cell size dependence of the self-aligned-type S-SGT DRAM was analyzed with regard to the above step widths and the number of cells in one unit. As a result, the cell design for minimizing the cell size of this device has been formulated. By using the proposed cell design, it is demonstrated by process simulation that the S-SGT DRAM in 0.5 μm design rule can achieve a cell size of 2.4F², which is half of the cell size of a conventional SGT DRAM cell (4.8F²). Therefore, the S-SGT DRAM is a promising candidate for future ultra high density DRAMs     

77 K versus 300 K operation: the quasi-saturation behavior of aDMOS device and its fully analytical model

A simulation study on the 77-K versus 300-K operation in terms of the quasi-saturation behavior of a DMOS device using low-temperature PISCES is discussed. From the analysis, a closed-form analytical quasi-saturation model for DMOS devices has been derived. Based on the analysis, for a lightly doped substrate (1×10¹⁵ cm^-3), at 77 K, the drain current at quasi-saturation is higher than that at 300 K. For a heavily doped-substrate (1×10¹⁶ cm^-3), at 77 K, the drain current at quasi-saturation is lower. The difference in drain current at quasi-saturation between 77 K and 300 K for different substrate doping densities is attributed to the incomplete ionization and saturated velocity effects     

A self-aligned elevated source/drain MOSFET

An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior     

Raised source/drain MOSFET with dual sidewall spacers

A raised source/drain (S/D) MOSFET with sidewall spacers formed both before and after selective epitaxial silicon deposition in S/D regions is discussed. The second spacer overlies any faceted regions of the epitaxial silicon near the gate edge and has advantages for MOSFETs with implant-doped or in-situ doped epitaxial silicon regions. In particular, the spacer can prevent S/D dopants from being implanted through any thinner faceted regions near the gate edge, which would otherwise result in a deeper than desired junction depth in the silicon substrate. Additionally, the spacer can prevent source-to-substrate salicide shorts through the thinner faceted regions     

A CV technique for measuring thin SOI film thickness

A technique is developed to measure silicon-on-insulator (SOI) silicon device film thickness using a MOSFET. The method is based on CV measurements between gate and source/drain at two different back-gate voltages. The SOI devices used in this study were n⁺ polysilicon gate n-channel MOSFETs fabricated with modified submicrometer CMOS technology on SIMOX (separation by implanted oxygen) wafers. The SIMOX wafers were implanted with a high dose of oxygen ions (10¹⁸ cm^-2) at 200 keV and subsequently annealed at 1230°C. The NMOS threshold boron implant dose is 2×10¹² cm^-2. This method is simple, nondestructive, and no special test structure is needed. Using this technique, SOI film thickness mapping was made on a finished wafer and a thickness variation of ±150 Å was found     

Increase of parasitic resistance in shallow p+ extensionby SiN sidewall process and its improvement by Ge preamorphization forsub-0.25-μm pMOSFET's

Anomalously high parasitic resistance is observed when SiN gate sidewall spacer is incorporated into sub-0.25-μm pMOSFET's. The parasitic resistance in p⁺ S/D extension region increases remarkably by decreasing BF₂ ion implantation energy to lower than 10 keV. It is confirmed that low activation efficiency of boron in p⁺ extension is the reason for such high parasitic resistance. The reduction of activation efficiency of boron may result from hydrogen passivation of boron acceptor; Fourier transform infrared absorption (FT-IR) measurement suggests that diffused hydrogen from SIN into p⁺ extension region forms the silicon-hydrogen-boron complex. It is also found that the activation efficiency of boron correlates well both with implantation energy of BF₂ and the amorphization rate of substrate. Therefore, in sub-0.25-μm era, the extra amorphization step is essential not only to form a shallow junction but also to enhance boron activation. Germanium preamorphization implantation (Ge PAI) is hence applied to p⁺ extension of 0.15 μm pMOSFET's. It is finally demonstrated that this Ge PAI process reduces the total parasitic resistance to improve the drain saturation current by up to 10%