共查询到19条相似文献,搜索用时 78 毫秒
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采用变速白光扫描干涉术测量大尺度台阶结构 总被引:3,自引:2,他引:1
针对传统白光扫描干涉术在对一些垂直尺度较大器件的测试中,存在测量时间长、信号利用率低等问题,本文提出了应用于白光扫描干涉测量的变速扫描策略,并开发了基于预定义模式的变速扫描和基于自动对焦模式的变速扫描两种具体的实现方式。本文方法能够控制测量系统仅在有干涉条纹存在的空间区域采集图像,而在其它区域加速运行,从而提高了测试效率。测量过程中,通过编写的测量软件控制纳米测量机(NMM),并利用NMM的高精度定位能力实现变速扫描。实验测试了一个100μm台阶结构,相对传统固定步长扫描法,变速扫描在保持高精度的基础上提高了测量效率。 相似文献
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大台阶高度测量的外差共焦方法 总被引:3,自引:1,他引:3
台阶高度是微电子产品的一个重要性能参数。基于双频激光干涉共焦显微系统(DICM)提出了一种微电子掩膜板台阶高度测量的扫描方法。在共焦显微扫描样品表面,当光强达到最大值时,将采样外差干涉的相位作为精确对准的判据。该扫描方法集中融合了外差干涉测量和共焦显微测量的优点,同时实现了高分辨率与较大量程的测量,该系统测量台阶高度的范围取决于Z向位移扫描仪PI-Foc的扫描范围,可达数十甚至近百微米。实验结果表明该系统在普通恒温的实验条件下1h内的漂移不超过5nm。该系统已经用于20μm高台阶的测量,对准分辨率为0.1nm,实验结果与台阶高度实际值有很好的一致性。 相似文献
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《微纳电子技术》2019,(1):71-77
为了在使用高倍物镜测量标准样板时获得高分辨率的样本整体区域信息,提出了一种基于尺度不变特征变换(SIFT)图像拼接算法的标准样板测量技术。首先通过高倍物镜获取局部三维结构,将其转化为二维灰度图像;然后采用SIFT和RANSAC算法得到准确的特征点;最后采用加权平均融合算法得到完整图像,重构整体样板三维结构,并利用ISO5436-1∶2000对标准样板台阶高度进行评价。实验对100和400 nm两种高度的标准样板进行了测量和拼接,并对拼接后的台阶高度进行评价,测量均值分别为100.3和398.9 nm,实验表明该技术能准确还原标准样板中台阶的高度,有效扩大了标准样板形貌重构的范围。 相似文献
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为了提高激光淬火硬化层形貌的均匀性,提出了一种基于振镜变速扫描的激光淬火光学系统。系统由QBH(quartz block head)、准直聚焦一体镜、单轴振镜和振镜变速扫描控制系统等组成。通过设定振镜扫描系统的变速区域宽度和变速系数,可实现能量中间低、两端高的“鞍形”光场分布。建立了重复变速扫描系统的等效热作用光场模型,并通过ANSYS软件模拟了45钢激光淬火过程中的温度场。重点分析了振镜扫描系统的变速系数和变速区域宽度对淬火后相变硬化层均匀性的影响。仿真结果表明,变速系数或变速区域的增大改善了硬化层的均匀性。采用千瓦级光纤激光器作为光源,进行了等变速区域不同变速系数的激光淬火实验。取硬化层深度降低至最大值90%的位置作为匀化区域的边界,变速系数为0.8时获得的硬化层的匀化区域宽度为5.1 mm,比振镜匀速扫描的匀化效果提升了约42%,实验结果与仿真结果吻合较好。 相似文献
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将白光偏振干涉、迈克耳孙干涉仪和垂直扫描系统相结合,提出了一种利用白光干涉垂直扫描测量波片延迟量(包括级次信息)的方法。准直的白光经偏振干涉系统形成两束偏振方向相同的线偏光,它们进入迈克耳孙干涉仪后分别被两干涉臂的平面镜反射形成四束光,在压电传感器(PZT)驱动干涉仪动镜垂直扫描的过程中,它们两两干涉,形成3组白光干涉包络。根据CCD各像素记录的白光干涉信号,计算白光干涉包络之间的光程差,即可获取被测延迟量。实验测量了一多级波片的延迟量,其结果(4268.1nm)与使用光谱扫描法测量得到的结果(4269.9nm)相吻合。 相似文献
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Ishimaru A. Coe R. Miller G. Geren W. 《Antennas and Propagation, IEEE Transactions on》1985,33(11):1213-1220
There are two conventional techniques dealing with mutual coupling problems for antenna arrays. The "element-by-element" method is useful for small to moderate size arrays. The "infinite periodic structure" method deals with one cell of infinite periodic structures, including all the mutual coupling effects. It cannot, however, include edge effects, current tapers, and nonuniform spacings. A new technique called the "finite periodic structure" method, is presented and applied to represent the active impedance of an array, it involves two operations. The first is to convert the discrete array problem into a series of continuous aperture problems by the use of Poisson's sum formula. The second is to use spatial Fourier transforms to represent the impedance in a form similar to the infinite periodic structure approach. The active impedance is then given by a convolution integral involving the infinite periodic structure solution and the Fourier transform of the equivalent aperture distribution of the current over the entire area of the array. The formulation is particularly useful for large finite arrays, and edge effects, current tapers, and nonuniform spacings can also be included in the general formulation. Although the general formulation is valid for both the free and forced modes of excitation, the forced excitation problem is discussed to illustrate the method. 相似文献
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为了解决非圆形大口径光学平面镜加工过程中的高精度检测问题,针对五棱镜扫描技术,使用一种基于多项式内积以及cholesky分解的非递归方法进行数据处理,同时编写了检测拟合程序,并结合工程实例,对30m望远镜(TMT),thirty meter telescope)项目的三镜(2.5m×3.5m椭圆形平面镜)进行了模拟检测的Monte-Carlo分析。分析结果表明,五棱镜扫描系统对TMT三镜低阶像差的检测精度可以达到30.6nm 5 rms,对power项、astigmatism项的检测精度分别达到9.6nm rms及13.7nmrms,能够完成大口径非圆形光学平面镜低像差的高精度检测。 相似文献
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针对大型工件,提出了一种基于单目线结构光三维扫描的方法。通过引入线结构光平面建立了视觉传感器数学模型和多项式模型,并使用高精密手动平移台控制平行线靶标在6个固定位置的移动对相机和光平面进行标定,提高标定的精度和准确度。同时对测量工件部分精准定位有效区域,减小程序运算量。该扫描方法可直接构建传感器的测量坐标系,过程简单,速度较快。通过对大尺寸铝合金铸件进行扫描测试,选取了合适的扫描速度v=1.25 mm/s,在满足精度的前提下提升了工业应用的效率。实验结果证明,此种方法能够有效准确的对物体表面进行重构,平均误差小于0.1 mm,具有较高的精度。 相似文献
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Baoxing Duan Bo Zhang Zhaoji Li 《Electron Device Letters, IEEE》2006,27(5):377-379
A new silicon-on-insulator (SOI) power MOSFET structure is proposed, in which buried oxide step structure (BOSS) is replaced by a buried oxide double step (BODS). Numerical simulations are performed to demonstrate that higher breakdown voltages are obtained resulting from a higher electric-field peak introduced near the BODS, and higher impurity concentration is depleted due to thin-film SOI than that in the conventional SOI and BOSS structure. 相似文献
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设计并加工测试了一款双面Vivaldi天线.通过结构优化, 提高了馈电效率和阻抗带宽, 并在组阵后显著降低了阵元间的互耦.实测结果表明该天线可以实现在2~8 GHz的频带内回波损耗(Return Loss, RL)小于-10 dB, 平均增益大于5 dBi.并采用“交错排列”的思路, 将所设计的双面Vivaldi天线组成超宽带阵列.此种方式可以有效解决天线尺寸和最佳阵列间距之间的矛盾, 进而抑制栅瓣, 增大波束扫描角范围.仿真分析表明, 在4~6 GHz时, E面交错阵列比普通一维阵列的扫描角范围提高20°左右. 相似文献
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Youngtae Cho Sin Kwon Jung-Woo Seo Jeong-Gil Kim Jung-Woo Cho Jung-Woo Park Hyuk Kim Sukwon Lee 《Microelectronic Engineering》2009,86(12):2417-2422
In order to apply cost effective and productive nano imprint technology to the TFT-LCD fabrication, problems owing to large patterning area have to be solved. In this works, large area UV nano imprint process was developed by using of collimated UV light and shadow masks. It was shown that complex patterns could be easily replicated on 300 mm × 400 mm substrate by a large mold which is fabricated by suggested step and repeat process. Because roll pressing and alignment technique are important steps in our process for large area nano imprint, these process steps were optimized. Also, as a key technology for enlargement of patterning area, the stitching technique was developed. The idea using a collimated UV light is used for pattern stitching in nano imprint process. Developed large area pattern fabrication technique could be applied to various applications such as TFT-LCD process or optical film fabrication extensively. 相似文献
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High-speed BiCMOS technology with a buried twin well structure 总被引:3,自引:0,他引:3
《Electron Devices, IEEE Transactions on》1987,34(6):1304-1310
A buried twin well and polysilicon emitter structure is developed for high-speed BiCMOS VLSI's. A bipolar transistor of high cutoff frequency (fT = 4 GHz) and small size (500 µm2) has been fabricated on the same chip with a standard 2-µm CMOS, without degrading the device characteristics of the MOSFET. Latchup immunity is improved due to the low well resistance of the buried layer. The well triggering current is a 0.5-1.0 order of magnitude higher than that of a standard n-well CMOS. To evaluate the utility of this technology, a 15-stage ring oscillator of the 2NAND BiCMOS gate is fabricated. The gate has a 0.71-ns propagation delay time and 0.25-mW power dissipation at 0.85-pF loading capacitance and 4-MHz operation. Drive ability is 0.24 ns/pF, which is 2.5 times larger than that of the equal-area CMOS gate. 相似文献