高帧频面阵CCD探测器应用技术研究

分析了高帧频帧转移面阵CCD的工作机制,设计了驱动电路和信号处理电路,获得了帧频为130帧/秒的高清晰图像,并提出了一种采用遮光板来提高帧频的新方法.该方法将帧频提高到了400帧/秒,具有较高的有效曝光比,并进一步改善了图像的质量.     

基于FPGA的大面阵CCD高帧频驱动电路设计

介绍了Dalsa公司的33M像素大面阵CCD的内部结构,着重分析了该款CCD的驱动时序.针对大面阵CCD图像传感器帧频较低的缺点,设计了基于现场可编程逻辑门阵列的驱动电路.改进了CCD芯片的偏置电压电路,提出了4 路同时输出以提高帧频的电路设计方法,最高帧频可达2.7帧/s ,相比单端输出时的0.7帧/s提高了约4倍.选用FPGA作为核心器件,使用VHDL语言设计驱动时序,在ISE和Modelsim环境下对所设计的驱动时序发生器进行仿真实验.实验结果表明,所设计的驱动电路能够满足大面阵CCD高帧频应用.     

扫描器性能实时检测装置中拖尾现象的消除

在扫描器性能检测设备研制过程中遇到的ccD拖尾现象,通过分析其产生机理,确定了拖尾现象的产生是由于帧转移型CCD在信号转移期间,成像区光敏单元仍处于感光状态,使成像区前一行的光敏元对成像区后一行的光敏元造成影响,从而形成拖尾.根据其产生机理,采取设计同步控制电路的办法,使得在数据读出过程中,快门处于关闭状态,使得感光区光敏元上没有光输入,从而解决了拖尾问题,实现了对于扫描器性能的实时检测.实验表明,本文所采用的技术方案,可以很好的解决CCD的拖尾问题.     

行间转移型面阵CCD成像系统设计

采用行间转移型面阵CCD KAI-1020作为图像传感器,以现场可编程门阵列（FPGA）为核心控制器,设计并实现了一个完整的成像系统。FPGA产生驱动时序、控制CCD上电顺序、调节曝光时间,并实现数据缓存。CCD模拟视频信号经过预处理,通过同轴电缆传输到CCD专用视频处理器进行相关双采样和模数转换,以10位像素深度输出到FPGA,数字视频信号经过差分芯片驱动以低压差分信号（LVDS）格式输出到数据采集卡。集成化视频处理电路提高了系统的信噪比,改善了成像质量。实验表明,CCD成像系统工作稳定可靠,像素读出时钟为10 MHz时,帧频为10帧/s。设计的CCD成像系统性能好、可靠性高、实现周期短,具有很强的可扩展性。     

CCD图像传感器拖尾的研究

对帧转移型CCD的结构进行分析，研究了造成垂直拖尾的原因，找到解决问题的方法。在摄像机系统中运用数字处理技术，实时地降低了垂直拖尾对图像的影响。     

长轨检测超声换能器驱动电路的设计

鉴于超声换能器(换能器)传统驱动电路中存在发射效率低,激励信号有拖尾的问题,该文提出了一种改进型驱动电路方案。首先,对换能器匹配和激励信号拖尾吸收的理论进行说明,并从匹配和拖尾吸收等方面综合考虑对驱动电路进行改进;其次,采用一发一收的机制,在600m60型钢轨上搭建实验平台,并对传统无匹配、有匹配驱动电路和该文设计的驱动电路的性能进行对比。实验结果表明,与传统无匹配驱动电路相比,改进型驱动电路消除了激励信号拖尾且波形光滑,接收信号中心频点相对幅值提高了98.97%;与传统有匹配驱动电路相比,改进型驱动电路消除了激励信号拖尾且波形光滑,接收信号中心频点相对幅值提高了50.45%。     

基于FPGA的多通道面阵CCD拼接成像系统

针对现有的CCD系统技术无法同时满足大面阵与高帧频的问题,提出了一种基于FPGA的高速多通道CCD拼接系统。采用智能化的AD芯片,配置生成精确且接收反馈的CCD驱动信号。调用FPGA内置的IP核,利用乒乓操作的思想操控DDR2完成多通道图像的拼接,百万像素CCD以100帧的速度处理。对多通道影响图像非均匀性进行分析,将处理图像的得到的参数反馈给AD芯片,实时调整各通道的增益,在硬件驱动电路上完成自适应非均匀性校正。经验证,该系统极大地提高了大面阵CCD的显示帧频,多通道拼接后获得较高成像质量。     

高集成度多光谱TDI CCD焦平面系统

提出了一种高集成度TDI CCD焦平面系统,成功应用TDI CCD驱动单元厚膜集成模块完成了具有16路CCD信号输出、像元读出频率20 MHz的高集成度高速多光谱TDI CCD焦平面系统的研制。通过采用双通道CCD信号处理模拟前端、厚膜集成驱动单元模块、高速LVDS图像数据传输接口以及机、电、热一体化仿真设计方法,极大提高了TDI CCD焦平面系统的集成度,降低了系统互连的复杂程度。系统共有4路图像数据传输接口,单路传输能力达到1.6~2.5 Gbps,最高可实现10 Gbps的图像数据带宽,在保证高数据率的同时,提高了数据传输的抗干扰能力。阐述了系统设计方案及多光谱TDI CCD探测器工作原理,并对其中的机电集成设计、驱动单元厚膜集成技术以及高速串行传输总线等关键技术进行了分析描述。通过采用TDI CCD传函测试片对系统进行了测试,焦平面全系统调制传函平均为0.511。     

KAI-2093型面阵CCD多模式驱动时序设计

针对某航空相机的设计要求,提出了一种可行的多模式驱动时序设计方法。采用柯达公司的KAI-2093行间转移型面阵CCD传感器,结合它的结构特点和双通道数据传输的思想分析了传感器驱动时序关系,提出了3种驱动模式:binning、no-binning和TDI模式。以Altera公司的FPGA芯片EP1C6Q240作为时序发生器并实现数据的缓存和拼接,从而实现了时序发生器与数据处理器的一体化设计。在QUARTUSII7.0开发环境下采用VHDL语言编程,通过Modelsim AE6.1b实现数据缓存器的仿真。实测结果表明,所设计的驱动时序满足KAI-2093的时序要求,binning模式下帧频可达60帧/s,120帧/s等,满足高速跟踪要求;no-binning模式下全帧输出帧频可达30帧/s;TDI模式下能保证CCD长时间工作而不影响成像质量,该设计方法提高了系统的集成度和抗干扰能力。     

气溶胶探测仪CCD成像系统的设计

设计了吸收性气溶胶探测仪CCD成像系统,该系统的硬件包括驱动时序电路、预处理和模拟前端电路、电源管理电路、FPGA主控单元,以及Camera Link通信电路等。提出一种带有反向转移的驱动时序来消除帧转移过程的残余电荷,并对该CCD成像系统性能进行测试验证。实验结果表明,该成像系统能稳定输出14 bit图像数据,帧频为1.8 frame/s,最短曝光时间为17.28 ms,非线性度误差为1.68%,当曝光饱和度为80%时,成像信噪比为54.36 dB,CCD可探测信号的动态范围为61.55 dB,可满足探测仪输出稳定、时间分辨率高、线性性能优、信噪比高、信号动态范围大的工作需求。     

Optimization of thin-film resistive-gate and capacitive-gate GaAscharge-coupled devices

Computer simulation of high-speed gallium arsenide charge coupled devices (CCDs) was performed using a two-dimensional semiconductor device simulation program. The measured performance of fabricated GaAs CCDs is compared with modeled results. The effect of active layer thickness and doping concentration on the charge transfer efficiency (CTE) and the dynamic range is investigated using different layers. Various gate architectures are compared for optimum dynamic range and compatibility with GaAs MESFET technology. The effect of clock shape on CTE is studied. Sensitivity analysis is performed on output structures. Both capacitive-gate CCD (CGCCD) and resistive-gate CCD (RGCCD) techniques are considered     

Simulation for signal charge transfer of charge coupled devices

Physical device models and numerical processing methods are presented to simulate a linear buried channel charge coupled devices (CCDs). The dynamic transfer process of CCD is carried out by a three-phase clock pulse driver. By using the semiconductor device simulation software MEDICI, dynamic transfer pictures of signal charges cells, electron concentration and electrostatic potential are presented. The key parameters of CCD such as charge transfer efficiency (CTE) and dark electrons are numerically simulated. The simulation results agree with the theoretic and experimental results.     

电荷耦合器件信号电荷转移的数值模拟

建立了线阵埋沟CCD的器件物理模型和数值模拟方法;运用半导体器件模拟软件MEDICI,数值模拟了CCD信号电荷在三相时序脉冲驱动下动态转移过程;模拟计算了CCD电荷转移效率随信号电荷包大小的变化以及暗电子数随埋沟掺杂浓度大小的变化情况。数值模拟结果与理论分析、实验测试结果吻合较好。     

帧转移型面阵CCD成像模型与仿真

基于帧转移型面阵CCD的成像原理,探讨了光电转换、电荷转移和电荷检测三个成像阶段存在的一些关键性问题,如像元响应的不一致性、相机抖动、电荷转移效率、帧转移模糊等,建立了相应的数学模型,并利用VC++6.0开发平台搭建了一整套CCD成像仿真系统。最后利用实验的方法,通过改变转移效率、曝光时间等CCD成像参数,分析比较了仿真结果。实验表明,该数学模型与面阵CCD器件成像过程较为吻合,仿真系统准确度较高。     

Development and Testing of a 2-D Transfer CCD

This paper describes the development, operation, and characterization of charge-coupled devices (CCDs) that feature an electrode structure that allows the transfer of charge both horizontally and vertically through the image area. Such devices have been termed two-dimensional (2-D) transfer CCDs (2DT CCDs), as opposed to the conventional devices, which might be called one-dimensional transfer CCDs, but in other respects are the same as conventional CCD devices. Batches of two different 2DT CCD test devices, featuring different electrode structures but with identical clocking operation in each case, were produced and tested. The methodology of 2-D charge transfer in each of the device types is described, followed by a presentation of test results from the new CCDs. The ability of both 2DT CCD transfer electrode schemes to successfully transfer charge in both horizontal and vertical directions in the image section of the devices has been proven, opening up potential new applications for 2DT CCD use     

A 1-inch 2-M pixel HDTV CCD image sensor with tungsten photo-shieldand H-CCD shunt wiring

A 1-inch 2-million pixel FIT-CCD image sensor for HDTV has been developed, which features a tungsten photo-shield and horizontal CCD (H-CCD) shunt wiring. Tungsten photo-shield, which has low reflectance and good step coverage characteristics, reduces smear level to -110 dB, combined with a frame-interline-transfer (FIT) scheme. The tungsten photo-shield also acts as a shunt busline, supplying transfer pulses to vertical CCD (V-CCD) electrodes, so that a 1.2×10ˆ5 electron charge handling capability is obtained at a frame transfer frequency of 1 MHz. Newly developed H-CCD shunt wiring suppresses vertical line pair FPN, even with smaller transfer pulse amplitudes. H-CCD shunt wiring also helps reduce power consumption in the H-CCD by 2/3 as compared to that achieved with conventional wiring     

High-density and high-quality frame transfer CCD imager with verylow smear, low dark current, and very high blue sensitivity

When the channel width of an FET becomes of the same order of magnitude as the depth of the gate depletion region, an increase of the threshold voltage is observed. This narrow channel effect has been applied successfully in creating an asymmetric potential well under an electrode for two-phase CCD operation. The feasibility of this structure has been confirmed in a 242-element analog delay line. The application is now extended to a 800 H×492 V frame transfer-type buried channel CCD imager with 14.31818 MHz frame shift, which results in a very low smear level of 0.01%, which is good enough for low-cost multimedia video camera applications     

电荷耦合器件辐射效应理论分析与模拟试验方法研究

分析了CCD电离效应和位移损伤机理,建立了一种国产埋沟CCD器件物理模型,实现了CCD信号电荷动态转移过程的数值模拟,计算了1MeV、14MeV中子引起的CCD电荷转移效率的变化规律.建立了线阵CCD辐照效应离线测量系统,实现了CCD辐射敏感参数测试.利用Co-60γ源和反应堆脉冲中子,开展了商用器件总剂量和中子位移损伤效应模拟试验,在不同辐照条件下,给出了暗电流信号、饱和电压信号、电荷转移效率以及像元不均匀性的变化情况.     

基于帧转移CCD的超高动态循环曝光控制技术研究

提出了一种可大幅度提升高光谱成像探测动态范围的基于帧转移电荷耦合器件(CCD)的曝光控制技术。该技术采用先积分后读出的工作模式,结合CCD快速电荷倾倒时序控制方法,能够有效清除空闲时段的无效电荷,实现超短积分时间和长积分时间曝光周期的快速切换;针对同一被探测目标,在规定时间范围内通过多档积分周期之间的快速切换,实现多档曝光周期的不间断循环曝光,从而使该技术的光谱探测动态范围相较传统技术提升2个数量级以上。设计了循环曝光档数和曝光时间可动态设置方式,时序仿真与测试结果表明,该方式能够有效提升高光谱成像技术在复杂光环境下的适应性。     

Cancellation of aliasing in CCD low-pass filters

The spurious frequencies caused by aliasing in a CCD low-pass filter can be canceled in the passband by designing a prefilter into the CCDs input stage. In this paper, the authors describe how single- and multiple-stage prefilters can be used, the rejection band and attenuation being set by the number of stages. They describe the design of second-order and third-order prefilters. In a basic design, the filtering effect is obtained only around the odd multiples of clock frequency; in a more complex design, the filtering effect is also obtained around twice the clock frequency. A second-order prefilter has been integrated into the input stage of a CCD low-pass filter. Experimental results are presented.