GaAs m.a.o.s.f.e.t. memory transistor

A new non-volatile memory device is reported. This device is a GaAs m.o.s.f.e.t. with charge storage in the gate in which is a double oxide structure of aluminium oxide and GaAs native oxide, both oxides are grown anodically. The fabrication of the device is described and the results of initial measurements on the charging and charge retention properties are presented.     

C.C.F.E.T.: an active charge-coupled device

A charge-coupled device is described in which an amplified measure of the charge can be obtained nondestructively at each element. Features of the device include high charge gain (?105) and the facility to reset the device and introduce charge packets into the c.c.d. by the `punchthrough? effect.     

Proton-bombardment isolated GaAlAs/GaAs charge-coupled devices

Proton bombardment is used for the first time as a channel isolation technique to fabricate buried channel homojunction charge-coupled devices (c.c.d.s) of n-GaAs channel on GaAs substrate and heterojunction c.c.d.s of n-Ga1?xAlxAs on GaAs. The c.c.d. structure is a Schottky-barrier gate buried channel 3-phase device with 30 transfer gates. The channel-stop bombardment was carried out at room temperature with an energy of 200 keV and a total dose of 1015/cm2. The c.c.d.s were tested with electrical charge injection and direct readout. The charge transfer efficiency was found to be greater than 0.999 per transfer for both GaAs and GaAlAs. The proton-bombardment isolated devices were compared with similar devices using mesa isolation and were found to perform similarly.     

Charge-splitting c.c.d. tapped delay lines

Two new types of c.c.d. tapped delay lines are described. One has parallel channels separated by channel stops from input to output. The other has channel stop wedges partitioning charge packets down the device. High performance is achieved.     

Techniques for increasing the effective charge-transfer efficiency of tapped c.c.d. registers

A design technique for multitap c.c.d. delay lines is discussed in which the effective charge transfer efficiency is increased over its intrinsic process-dependent value. The technique involves locating tap amplifiers at every alternate bit, and operating the device at twice the normal clock rate. The advantages of the technique are discussed with reference to a 32-tap, n-channel c.c.d. delay line.     

Depletion m.o.s. power transistors

A new depletion m.o.s. transistor is proposed. The structure uses anisotropic etching to define the channel in an n?p epitaxial silicon slice. The fabrication, characteristics and power capabilities of the device are discussed.     

A compact model for SiGe HBT on thin-film SOI

Heterojunction bipolar transistor (HBT) fabrication on thin-film silicon-on-insulator (SOI) has been recently demonstrated. Due to the space volume constraint (thin film) for the device fabrication, the HBT structure is different from bulk HBT. In fact, compared to a bulk device, the buried layer has been suppressed and a lateral collector contact configuration is introduced. This device features a vertical expansion followed by a lateral expansion of the base-collector space charge region. This nonconventional charge behavior induces a kink in the base-collector junction capacitance characteristics, and as a consequence a modified Early effect. Furthermore, the low current transit time is modified compared to a bulk HBT. In this paper, all these effects are analyzed and a compact model for SOI-HBT is proposed. The model is validated on real SOI-HBTs with different collector doping levels.     

具有T型电荷补偿区的横向超结SOILDMOS

非平衡超结器件的电荷补偿能力在薄层SOI器件中受到限制,文中提出一种具有T型电荷补偿区的器件结构。通过漏端刻蚀的PSOI结构使硅衬底与埋氧层同时参与纵向耐压,可以提高非平衡超结n区的电荷补偿能力;在埋氧层刻蚀区增加垂直的n型补偿区,弥补埋氧层的缺失。由横向的非平衡超结n区和漏端垂直的n区共同构成T型补偿区,可以有效缓解薄层SOI超结器件中的衬底辅助耗尽效应,优化横向电场,提高器件的耐压。器件的制作可以通过改进传统的PSOI工艺实现,应用于SOI功率集成电路。三维器件仿真结果表明,新结构下的器件耐压达到290V,相对于常规的SOI超结器件和非平衡超结器件提高了267%和164%。     

用于存储器电路的ONO结构特性研究

为研究存储器的多晶间介质采用ONO(Oxide-Nitride-Oxide)结构的基本特性,从ONO叠层的工作原理和它在器件制作中的工艺结构出发,设计了采用ONO结构存储器的模拟实验,对不同工艺条件下的ONO叠层作对比实验,通过ONO叠层的I-V曲线、漏电流、击穿场强和电荷保持特性的测试及分析,研究了不同生长条件对ONO结构的影响程度,获得了最优的ONO叠层制作条件,为存储器的设计和工艺控制提供了参考.     

Meander channel c.c.d. (m.c.c.d.) transversal filter

A simple and compact m.c.c.d. transversal filter is presented. The device features (a) an input-weight technique to achieve a large output voltage, (b) a new `split-input-gate? weighting to provide accurate filter coefficients, and (c) a simplified electrode structure by using the m.c.c.d. as a summing register.     

Simulation and Design of AlGaAs/InGaAs CCDs Based on pHEMT Technology

This paper describes the modeling, design, and fabrication of quarter-micrometer double delta-doped AlGaAs/InGaAs charge-coupled devices (CCDs) whose epitaxial layers and geometry were based around the device structure of commercial pHEMTs. A quasi-2-D physical model has been developed to investigate the properties of this novel 2-D electron gas CCD. This physical model allows the characteristics of the InGaAs transport channel as well as the dc characteristics of the device to be predicted within a reasonable amount of time. This model also shows how "individual" charge packets can be controllably transferred through the device when appropriate clocking voltages are applied to the gates of the CCD. This capacitive gate structure device is then shown to be successfully fabricated using established GaAs heterostructure fabrication techniques to ensure good repeatability. The dc characteristics of the fabricated CCD delay line are included.     

Optimum p-channel isolation structure for CMOS

A two-dimensional numerical model of the width direction of a MOSFET is used to simulate the surface potential and the subthreshold current of p-channel devices. Fully-recessed, semi-recessed, and nonrecessed oxide isolation structures with various transition angles as well as interface charge are modeled. The nonrecessed oxide structure is superior for reducing subthreshold current, in some cases more than 20 percent. The fully-recessed oxide with a 90° transition angle provides maximum device density, a planar surface, and ease of fabrication. Experimental results indicate that for the fully-recessed oxide structure the p-channel device with interface charge will show a threshold-voltage variation of only 12 percent with widths varying from 10 to 1.5 µm, and an increase in subthreshold current of an order of magnitude compared to a wide device.     

Reducing the effect of charge-transfer inefficiency in a c.c.d. video integrator

The usefulness of c.c.d.s as video integrators is limited by the charge-transfer inefficiency of the device. A method of coding the signal before passage through the c.c.d. is described which greatly reduces the effect of this inefficiency.     

Dopingless Impact Ionization MOS (DL-IMOS)- A remedy for complex process flow

We propose a unique approach for realizing dopingless impact ionization MOS (DL-IMOS) based on the charge plasma concept as a remedy for complex process flow. It uses work-function engineering of electrodes to form charge plasma as surrogate doping. This charge plasma induces a uniform p-region in the source side and an n-region in the drain side on intrinsic silicon film with a thickness less than the intrinsic Debye length. DL-IMOS offers a simple fabrication process flow as it avoids the need of ion implantation, photo masking and complicated thermal budget via annealing devices. The lower thermal budget is required for DL-IMOS fabrication enables its fabrication on single crystal silicon-on-glass substrate realized by wafer scale epitaxial transfer. It is highly immune to process variations, doping control issues and random dopant fluctuations, while retaining the inherent advantages of conventional IMOS. To epitomize the fabrication process flow for the proposed device a virtual fabrication flow is also proposed here. Extensive device simulation of the major device performance metrics such as subthreshold slope, threshold voltage, drain induced current enhancement, and breakdown voltage have been done for a wide range of electrodes work-function. To evaluate the potential applications of the proposed device at circuit level, its mixed mode simulations are also carried out.     

New n-channel m.o.s.f.e.t.s

By using plasma c.v.d. and lift-off, an n-channel m.o.s.f.e.t. with effective channel length of 0.4 ?m has been fabricated. Its main fabrication processes and obtained electrical characteristics are described.     

Maximum free charge in two-phase surface charge-coupled devices

The maximum charge that can be stored and transferred efficiently in a surface CCD is significantly larger than in the buried channel device. However, whereas in the three-phase surface CCD the maximum charge depends primarily on clock voltage differences, in the two-phase device it depends on parameters which are fixed during fabrication. It is important therefore in the design of two-phase structures, to have a detailed understanding of how this charge depends on device parameters. The implanted barrier (IB) and stepped oxide (SO) structures are analysed by comparing the surface potentials obtained from one-dimensional models of the appropriate regions and a number of contrasting dependences found between the two types of CCD. A further limit to the maximum free charge for both devices is set when the field at the oxide-semi-conductor interface (and normal to it) approaches the breakdown field for Silicon. The presence of the implanted region in the IB. CCD gives rise to a radically different field limitation for the structure.     

A wide-band low-noise charge transfer video delay line

A new wide-band low-noise charge transfer video delay line is introduced utilizing a bulk charge transfer device (BCD) with a self-aligned electrode structure, and a simple integrated sample-hold circuit. Brief analysis of charge transfer characteristics of the BCD and design considerations for the proposed device are included. Several kinds of 128-element devices are designed and examined. Measured transferred signal bandwidth is 4 MHz at 10 MHz clock of voltage swing as low as 10 V, with signal-to-noise (S/N) ratio of 42 dB. The device itself can operate beyond 20 MHz clock rate. Moreover, the device features the use of an elaborate sample-hold circuit to eliminate the complex reset pulse and filtering circuitry, high packing density of 18 /spl mu/m per element with 3-/spl mu/m line spacings assuring a high fabrication yield, and process compatibility with conventional Si gate MOS technology.     

Inverted bistability in the current-voltage characteristics of a resonant tunneling device

The current-voltage characteristics of an asymmetric double barrier resonant tunneling device show a butterfly-shaped hysteresis loop in which, for a range of voltage, the off-resonant current exceeds the resonant current. This “inverted bistability” is due to the effects of space charge buildup in the quantum well. Magnetoquantum oscillations in the tunnel current with | are used to investigate the distribution of charge within the device and the intersubband scattering processes which control the charge buildup.     

Modulation-doped AlGaAs/GaAs heterostructure charge coupled devices

The advantages of the modulation-doped heterostructure over conventional materials structures for high speed CCD applications are outlined. In addition, the first demonstration of charge transfer in a modulation-doped AlGaAs/GaAs heterojunction is reported. A ten cell, three phase Schottky barrier gate CCD was fabricated using this structure and operated as a shift register. The details of the device fabrication and characterization are presented.     

InP/Al2O3n-channel inversion-mode m.i.s.f.e.t.s using sulphur-diffused source and drain

InP metal-insulator-semiconductor field-effect transistors (m.i.s.f.e.t.s) have been fabricated using c.v.d. Al2O3 as the gate insulator and the sulphur-diffusion process for source and drain. The n-channel inversion-mode device exhibits normally off behaviour. A maximum d.c. transconductance gm of 10 mS (87 mS/mm of gate width) has been obtained.