Physical and electrical characterization of polysilicon vs. TiN gate electrodes for HfO2 transistors

The effects of pre-deposition substrate treatments and gate electrode materials on the properties and performance of high-k gate dielectric transistors were investigated. The performance of O₃ vs. HF-last/NH₃ pre-deposition treatments followed by either polysilicon (poly-Si) or TiN gate electrodes was systematically studied in devices consisting of HfO₂ gate dielectric produced by atomic layer deposition (ALD). High-angle annular dark field scanning transmission electron microscopy (HAADF-STEM) using X-ray spectra and Electron Energy Loss Spectra (EELS) were used to produce elemental profiles of nitrogen, oxygen, silicon, titanium, and hafnium to provide interfacial chemical information and to convey their changes in concentration across these high-k transistor gate-stacks of 1.0–1.8 nm equivalent oxide thickness (EOT). For the TiN electrode case, EELS spectra illustrate interfacial elemental overlap on a scale comparable to the HfO₂ microroughness. For the poly-Si electrode, an amorphous reaction region exists at the HfO₂/poly-Si interface. Using fast transient single pulse (SP) electrical measurements, electron trapping was found to be greater with poly-Si electrode devices, as compared to TiN. This may be rationalized as a result of a higher density of trap centers induced by the high-k/poly-Si material interactions and may be related to increased physical thickness of the dielectric film, as illustrated by HAADF-STEM images, and may also derive from the approximately 0.5 nm larger EOT associated with polysilicon electrodes on otherwise identical gate stacks.     

Potential remedies for the VT/Vfb-shift problem of Hf/polysilicon-based gate stacks: a solution-based survey

In this paper, we report on several different approaches that were implemented on both capacitor and scaled planar MOS transistor devices in order to prevent or undo the commonly observed V_T/V_fb-shift and –instability for Hf-based high-κ gate stacks in conjunction with a poly-Si electrode. While the latter issue can eventually be mitigated, the V_T-shift problem jeopardizes initial high-κ integration with poly-Si for the 65 nm and also for the 45 nm node. The different attempts to circumvent this problem include (1) bulk modifications of the high-κ stack/process, (2) the use of various thin capping layers at the poly/high-κ interface and (3) chemical and process modifications of the gate electrode deposition. We have observed that, although considerable improvements have been made in terms of e.g. yield, performance and instability, none of these techniques succeeded in obtaining V_T-values in line with the ITRS device specifications, i.e. avoiding Fermi Level Pinning to occur for poly-Si/Hf(Si)O(N) stacks.     

Probing stress effects in HfO2 gate stacks with time dependent measurements

Effects of constant voltage stress (CVS) on gate stacks consisting of an ALD HfO₂ dielectric with various interfacial layers were studied with time dependent sensing measurements: DC I–V, pulse I–V, and charge pumping (CP) at different frequencies. The process of injected electron trapping/de-trapping on pre-existing defects in the bulk of the high-κ film was found to constitute the major contribution to the time dependence of the threshold voltage (V_t) shift during stress. The trap generation observed with the low frequency CP measurements is suggested to occur within the interfacial oxide layer or the interfacial layer/high-κ interface, with only a minor effect on V_t.     

Electrical characterization and analysis techniques for the high-κ era

Various conventional and novel electrical characterization techniques have been combined with careful, robust analysis to properly evaluate high-κ gate dielectric stack structures. These measurement methodologies and analysis techniques have enhanced the ability to separate pre-existing defects that serve as fast transient charging and discharging sites from defects generated with stress. In addition, the differentiation of electrically active bulk high-κ traps, silicon substrate interface traps, and interfacial layer traps has been effectively demonstrated.     

Monte carlo study of mobility in Si devices with -based oxides

HfO₂-based high-κ dielectrics are among the most likely candidates to replace SiO₂ and the currently favoured oxinitride in the next generation of MOSFETs. High-κ materials allow the use of a thicker gate dielectric, maintaining the gate capacitance with reduced gate leakage. However, they lead to a fundamental mobility degradation due to the coupling of carriers to surface soft (low-energy) optical phonons. Comparing the vertical field dependence of the mobility for HfO₂ and SiO₂, the severe degradation in mobility in the presence of high-κ becomes evident. The introduction of a SiO₂ interfacial layer between the channel and the HfO₂ mitigates this degradation, by increasing the effective distance between the carriers and the SO phonons, thus decreasing the interaction strength, this does though lead to an increase in the equivalent oxide thickness (EOT) of the gate dielectric. The material of choice for the first commercial introduction of high-κ gate stacks is Hafnium Silicate (Si_xHf_1-xO₂). This alloy stands up better to the processing challenges and as a result suffers less from dielectric fluctuations. We show that as the fraction of Hf increases within the alloy, the inversion layer mobility is shown to decrease due to the corresponding decrease in the energy of the surface optical phonons and increase in the dielectric constant of the oxide.     

Challenges and performance limitations of high-k and oxynitride gate dielectrics for 90/65 nm CMOS technology

For low power applications, the increase of gate leakage current, caused by direct tunneling in ultra-thin oxide films, is the crucial factor eliminating conventional SiO₂-based gate dielectrics in sub-90 nm CMOS technology development. Recently, promising performance has been demonstrated for poly-Si/high-k and poly-Si/SiON gate stacks in addressing gate leakage requirements for low power applications. However, the use of poly-Si gate electrodes on high-k created additional issues such as channel mobility and reliability degradations, as well as Fermi level pinning of the effective gate work function. Therefore, oxynitride gate dielectrics are being proposed as an intermediate solution toward the sub-65/45 nm nodes. Apparently, an enhanced SiON gate dielectric stack was developed and reported to achieve high dielectric constant and good interfacial properties. The purpose of this paper is to provide a comprehensive review some of the device performance and limitation that high-k and oxynitride as dielectric materials are facing for sub-65/45 nm node.     

Bond strain and defects at interfaces in high-k gate stacks

The performance and reliability of aggressively-scaled field effect transistors are determined in large part by electronically-active defects and defect precursors at the Si–SiO₂, and internal SiO₂–high-k dielectric interfaces. A crucial aspect of reducing interfacial defects and defect precursors is associated with bond strain-driven bonding interfacial self-organizations that take place during high temperature annealing in inert ambients. The interfacial self-organizations, and intrinsic interface defects are addressed through an extension of bond constraint theory from bulk glasses to interfaces between non-crystalline SiO₂, and (i) crystalline Si, and (ii) non-crystalline and crystalline alternative gate dielectric materials.     

Extracting the relative dielectric constant for “high-κ layers” from CV measurements – Errors and error propagation

The paper pursues an investigation of the errors associated with the extraction of the dielectric constant (i.e., κ value) from capacitance–voltage measurements on metal oxide semiconductor capacitors. The existence of a transition layer between the high-κ dielectric and the silicon substrate is a factor that affects – in general – the assessment of the electrical data, as well as the extraction of κ. A methodology which accounts for this transition layer and the errors related to other parameters involved in the κ value extraction is presented; moreover, we apply this methodology to experimental CV results on HfO₂/SiO_x/Si structures produced in different conditions.     

A carrier-mobility model for high-k gate-dielectric Ge MOSFETs with metal gate electrode

A mobility model for high-k gate-dielectric Ge pMOSFET with metal gate electrode is proposed by considering the scattering of channel carriers by surface-optical phonons in the high-k gate dielectric. The effects of structural and physical parameters (e.g. gate dielectric thickness, electron density, effective electron mass and permittivity of gate electrode) on the carrier mobility are investigated. The carrier mobility of Ge pMOSFET with metal gate electrode is compared to that with poly-Si gate electrode. It is theoretically shown that the carrier mobility can be largely enhanced when poly-Si gate electrode is replaced by metal gate electrode. This is because metal gate electrode plays a significant role in screening the coupling between the optical phonons in the high-k gate dielectric and the charge carriers in the conduction channel.     

Interfacial layer quality effects on low-frequency noise (1/f) in p-MOSFETs with advanced gate stacks

The effects of interfacial layer quality on the low-frequency noise behavior of p-channel MOSFETs with high-κ gate dielectric and metal gate are investigated. Devices with chemically grown SiO₂ interfacial layers (0.8 nm) are compared with N₂O (0.8 nm) interfacial oxides. A 0.4 nm SiO₂ interfacial layer device is used for comparison purposes. A cross-over kind of behavior has been observed in N₂O devices, which occur at lower gate voltages (1.2–1.3 V) when normalized spectral densities and input referred noise are investigated. This behavior is found to be closely related to the observed transconductance variation in these devices. The dominant mechanism of 1/f noise is found to be Hooge’s mobility fluctuations. Hooge’s parameter, as a figure of merit, shows an increase for 0.4 nm devices when compared to 0.8 nm devices, while 0.8 nm N₂O devices confirm their cross-over nature.     

Gate leakage properties of MOS devices with tri-layer high-k gate dielectric

Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked when it is used for MOSFET with SiO₂ and high-k dielectric material as gate dielectrics, respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO₂/HfSiON with a U-shape nitrogen profile and a like-Si/SiO₂ interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5-nm HfO₂ and 1.2-nm HfSiON exhibits the lowest gate leakage.     

Scaling the MOSFET gate dielectric: From high-k to higher-k? (Invited Paper)

We discuss options for metal–oxide-semiconductor field-effect transistor (MOSFET) gate stack scaling with thin titanium nitride metal gate electrodes and high-permittivity (‘high-k’) gate dielectrics, aimed at gate-first integration schemes. Both options are based on further increasing permittivity of the dielectric stack. First, we show that hafnium-based stacks such as TiN/HfO₂ can be scaled to capacitance equivalent thickness in inversion (T_inv) of 10 Å and equivalent oxide thickness (EOT) of 6 Å by using silicon nitride instead of silicon oxide as a high-k/channel interfacial layer. This is based on the higher dielectric constant of Si₃N₄ and on its resistance to oxidation. Although the nitrogen introduces positive fixed charges, carrier mobility is not degraded. Secondly, we investigate whether Ti-based ‘higher-k’ dielectrics have the potential to ultimately replace Hf. We discuss oxygen loss from TiO₂ as a main challenge, and identify two migration pathways for such oxygen atoms: In addition to well-known down-diffusion and channel Si oxidation, we have newly observed oxygen up-diffusion through the TiN metal gate, forming SiO₂ at the poly-Si contact. We further address the performance of Si₃N₄ and HfO₂ as oxygen barrier layers.     

Conduction mechanisms of silicon oxide/titanium oxide MOS stack structures

During the last years, high-k dielectrics have been studied intensively looking for an alternative material to replace the SiO₂ films as gate dielectric in MOS transistors. Different materials and structures have been proposed. An important concern not yet solved, is the interfacial quality between high-k materials and silicon substrate. For this reason, stack structures with SiO₂ as an interfacial layer between silicon substrate and high-k film have been studied. In this contribution we analyze the main conduction mechanism observed in SiO₂/TiO₂ MOS stack structures obtained by room temperature plasma oxidation in different conditions and reactors. Films fabricated in a parallel-plate type reactor showed better quality with low current density where thermionic conduction mechanism is predominant. In lower quality films, for example those fabricated in a barrel type equipment, the current density is higher and the conduction mechanism observed is Poole–Frenkel. Finally we show that the presence of thermionic mechanism provides a weak thickness dependence and a strong current density reduction with respect to silicon oxide MOS structures with the same equivalent oxide thickness.     

Influence of the SiO2 layer thickness on the degradation of HfO2/SiO2 stacks subjected to static and dynamic stress conditions

The substitution of the SiO₂ gate oxide in MOS devices by a material with a high-k dielectric constant is being deeply studied nowadays to solve the problem of the leakage currents that appear with the progressive scaling of SiO₂ thickness. To improve the quality of the high-k/Si interface a very thin SiO₂ film is grown between both materials. In this work, HfO₂/SiO₂ stacks with different SiO₂ thickness were subjected to different types of stress (static and dynamic) to analyze the effect of this interfacial layer of SiO₂ in the degradation of the stack. The results show that the dielectric degradation depends on the stress applied and that the thickness of the SiO₂ interfacial layer influences the advanced stages of the stack degradation.     

Full-band tunneling in high-κ dielectric MOS structures

High-κ oxides such as ZrO₂ and HfO₂ have attracted great interest, due to their physical properties, suitable to replacement of SiO₂ as gate dielectric materials. In this work, we investigate the tunneling properties of ZrO₂ and HfO₂ high-κ oxides, by applying quantum mechanical methods that include the full-band structure of Si and oxide materials. Semiempirical sp³s*d tight-binding parameters have been determined to reproduce ab initio band dispersions. Transmission coefficients and tunneling current have been calculated for Si/ZrO₂/Si and Si/HfO₂/Si MOS structures, showing a very low gate leakage current in comparison to SiO₂-based structures with equivalent oxide thickness.     

Investigation of the Interfaces in Ni-FUSI/Hf-Based/Si and Ni-FUSI/SiO<Subscript>2</Subscript>/Si Stacks by Physical and Electrical Characterization Techniques

The combination of full Ni silicidation (Ni-FUSI) gate electrodes and hafnium-based high-k gate dielectrics is one of the most promising replacements for poly-Si/SiO₂/Si gate stacks for the future complementary metal–oxide–semiconductor (CMOS) sub-45-nm technology node. The key challenges to successfully adopting the Ni-FUSI/high-k dielectric/Si gate stack for advanced CMOS technology are mostly due to the interfacial properties. The origins of the electrical and physical characteristics of the Ni-FUSI/dielectric oxide interface and dielectric oxide/bulk interface were studied in detail. We found that Ni-FUSI undergoes a phase transformation during silicide formation, which depends more on annealing temperature than on the underlying gate dielectric material. The correlations of Ni–Si phase transformations with their electrical and physical changes were established by sheet resistance measurements, x-ray diffraction (XRD), atomic force microscopy (AFM), and x-ray photoelectron spectroscopy (XPS) analyses. The leakage current density–voltage (J–V) and capacitance–voltage (C–V) measurement techniques were employed to study the dielectric oxide/Si interface. The effects of the postdeposition annealing (PDA) treatment on the interface charges of dielectric oxides were studied. We found that the PDA can effectively reduce the trapping density and leakage current and eliminate hysteresis in the C–V curves. In addition, the changes in chemical bonding features at HfO₂/Si and HfSiO/Si interfaces due to PDA treatment were evaluated by XPS measurements. XPS analysis provides a better interpretation of the electrical outcomes. As a result, HfSiO films exhibited superior performance in terms of thermal stability and electrical characteristics.     

Improved low frequency noise characteristics of sub-micron MOSFETs with TaSiN/TiN gate on ALD HfO2 dielectric

Low frequency noise measurements were performed on n- and p-channel MOSFETs with TaSiN and TiN metal gates, respectively, deposited on ALD HfO₂ gate dielectric. Lower normalized current noise power spectral density is reported for these devices in comparison to poly-Si/HfO₂ devices and that yielded one order lower magnitude for extracted average effective dielectric trap density. In addition, the noise levels in PMOS devices were found to be higher than NMOSFETs and the dielectric trap distribution less dense in the upper mid-gap than the lower mid-gap region. The screened carrier scattering coefficient extracted from the noise measurements was approximately the same for metal and poly-Si high-k stacks but higher than that for the poly-Si SiO₂ system, implying higher Coulomb scattering effects. It is believed that the elimination of dopant penetration seen in poly-Si system and low thermal budgets for metal gate deposition helped lower the noise magnitude and yielded better mobility and effective trap density values.     

在metal/high-k 栅叠层中插入Ti/TiN金属层实现远距离吸氧技术

High permittivity materials have been required to replace traditional SiO₂ as the gate dielectric to extend Moore’s law.However,growth of a thin SiO₂-like interfacial layer（IL） is almost unavoidable during the deposition or subsequent high temperature annealing.This limits the scaling benefits of incorporating high-k dielectrics into transistors.In this work,a promising approach,in which an O-scavenging metal layer and a barrier layer preventing scavenged metal diffusing into the high-k gate dielectric are used to engineer the thickness of the IL,is reported. Using a Ti scavenging layer and TiN barrier layer on a HfO₂ dielectric,the effective removal of the IL and almost no Ti diffusing into the HfO₂ have been confirmed by high resolution transmission electron microscopy and X-ray photoelectron spectroscopy.     

Investigation on interfacial and electrical properties of Ge MOS capacitor with different NH3-plasma treatment procedure

The effects of different NH₃-plasma treatment procedures on interfacial and electrical properties of Ge MOS capacitors with stacked gate dielectric of HfTiON/TaON were investigated. The NH₃-plasma treatment was performed at different steps during fabrication of the stacked gate dielectric, i.e. before or after interlayer (TaON) deposition, or after deposition of high-k dielectric (HfTiON). It was found that the excellent interface quality with an interface-state density of 4.79×10¹¹ eV^-1cm^-2 and low gate leakage current (3.43×10^-5A/cm² at V_g=1 V) could be achieved for the sample with NH₃-plasma treatment directly on the Ge surface before TaON deposition. The involved mechanisms are attributed to the fact that the NH₃-plasma can directly react with the Ge surface to form more Ge-N bonds, i.e. more GeO_xN_y, which effectively blocks the inter-diffusion of elements and suppresses the formation of unstable GeO_x interfacial layer, and also passivates oxygen vacancies and dangling bonds near/at the interface due to more N incorporation and decomposed H atoms from the NH₃-plasma.     

Electrical characterization of crystalline Gd2O3 gate dielectric MOSFETs fabricated by damascene metal gate technology

This paper presents the first successful attempt to integrate crystalline high-K gate dielectrics into a virtually damage-free damascene metal gate process. Process details as well as initial electrical characterization results on fully functional gate Gd₂O₃ dielectric MOSFETs with equivalent oxide thickness down to 1.9 nm are discussed.