A highly linear receiver front-end employing modified derivative superposition method with tuned inductors for 5.25 GHz

We design a highly linear CMOS RF receiver front-end operating in the 5 GHz band using the modified derivative superposition (DS) method with one- or two-tuned inductors in the low noise amplifier (LNA) and mixer. This method can be used to adjust the magnitude and phase of the third-order currents at output, and thus ensure that they cancel each other out. We characterize the two front-ends by the third-order input intercept point (IIP3), voltage conversion gain, and a noise figure based on the TSMC 0.18 μm RF CMOS process. Our simulation results suggest that the front-end with one-tuned inductor in the mixer supports linearization with the DS method, which only sacrifices 1.9 dB of IIP3 while the other performance parameters are improved. Furthermore, the front-end with two-tuned inductors requires a precise optimum design point, because it has to adjust two inductances simultaneously for optimization. If the inductances have deviated from the optimum design point, the front-end with two-tuned inductors has worse IIP3 characteristic than the front-end with one-tuned inductor. With two-tuned inductors, the front-end has an IIP3 of 5.3 dBm with a noise figure (NF) of 4.7 dB and a voltage conversion gain of 23.1 dB. The front-end with one-tuned inductor has an IIP3 of 3.4 dBm with an NF of 4.4 dB and a voltage conversion gain of 24.5 dB. There is a power consumption of 9.2 mA from a 1.5 V supply.     

A 1.2-V RF front-end with on-chip VCO for PCS 1900 direct conversion receiver in 0.13-/spl mu/m CMOS

In this paper, a 1.2-V RF front-end realized for the personal communications services (PCS) direct conversion receiver is presented. The RF front-end comprises a low-noise amplifier (LNA), quadrature mixers, and active RC low-pass filters with gain control. Quadrature local oscillator (LO) signals are generated on chip by a double-frequency voltage-controlled oscillator (VCO) and frequency divider. A current-mode interface between the downconversion mixer output and analog baseband input together with a dynamic matching technique simultaneously improves the mixer linearity, allows the reduction of flicker noise due to the mixer switches, and minimizes the noise contribution of the analog baseband. The dynamic matching technique is employed to suppress the flicker noise of the common-mode feedback (CMFB) circuit utilized at the mixer output, which otherwise would dominate the low-frequency noise of the mixer. Various low-voltage circuit techniques are employed to enhance both the mixer second- and third-order linearity, and to lower the flicker noise. The RF front-end is fabricated in a 0.13-/spl mu/m CMOS process utilizing only standard process options. The RF front-end achieves a voltage gain of 50 dB, noise figure of 3.9 dB when integrated from 100 Hz to 135 kHz, IIP3 of -9 dBm, and at least IIP2 of +30dBm without calibration. The 4-GHz VCO meets the PCS 1900 phase noise specifications and has a phase noise of -132dBc/Hz at 3-MHz offset.     

A 0.7-7 GHz wideband reconfigurable receiver RF front-end in CMOS

In this paper,a 0.7-7 GHz wideband RF receiver front-end SoC is designed using the CMOS process.The front-end is composed of two main blocks:a single-ended wideband low noise amplifier (LNA) and an inphase/quadrature (I/Q) voltage-driven passive mixer with IF amplifiers.Based on a self-biased resistive negative feedback topology,the LNA adopts shunt-peaking inductors and a gate inductor to boost the bandwidth.The passive down-conversion mixer includes two parts:passive switches and IF amplifiers.The measurement results show that the front-end works well at different LO frequencies,and this chip is reconfigurable among 0.7 to 7 GHz by tuning the LO frequency.The measured results under 2.5-GHz LO frequency show that the front-end SoC achieves a maximum conversion gain of 26 dB,a minimum noise figure (NF) of 3.2 dB,with an IF bandwidth of greater than 500 MHz.The chip area is 1.67 × 1.08 mm2.     

A 2.4-GHz sub-mW CMOS receiver front-end for wireless sensors network

A 2.4-GHz fully integrated CMOS receiver front-end using current-reused folded-cascode circuit scheme is presented. A configuration utilizing vertically stacked low-noise amplifier (LNA) and a folded-cascode mixer is proposed to improve both conversion gain and noise figure suitable for sub-mW receiver circuits. The proposed front-end achieves a conversion gain of 31.5dB and a noise figure of 11.8dB at 10MHz with 500-/spl mu/A bias current from a 1.0-V power supply. The conversion gain and noise figure improvements of the proposed front-end over a conventional merged LNA and single-balanced mixer are 11dB and 7.2dB at 10MHz, respectively, with the same power consumption of 500/spl mu/W.     

一个双频带可重构的直接变频接收机射频前端

A dual-band reconfigurable wireless receiver RF front-end is presented, which is based on the directconversion principle and consists of a low noise amplifer （LNA） and a down-converter. By utilizing a compact switchable on-chip symmetrical inductor, the RF front-end could be switched between two operation frequency bands without extra die area cost. This RF front-end has been implemented in the 180 nm CMOS process and the measured results show that the front-end could provide a gain of 25 dB and IIP3 of 6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm^2.     

A low voltage current mode CMOS integrated receiver front-end for GPS system

This paper presents a low voltage, 1.6 GHz integrated receiver front-end which is implemented by the standard 0.35 μm, 3M2P CMOS technology. The receiver consists of a transconductance low noise amplifier (G_m-LNA), a down conversion current mode mixer and a voltage-controlled oscillator using accumulation-mode MOS varactor (A-MOS VCO). A current mode mixer is used to reduce the supply voltage to 1 V. A specially designed G_m-LNA converts RF input voltage to RF input current for the current mode mixer. This could eliminate an unnecessary I–V, V–I conversion and reduce the non-linearity contribution. Moreover, a low voltage A-MOS VCO, with a good phase noise and wide tuning frequency range, is used to generate a required oscillating frequency for the receiver. The integrated receiver front-end has a measured power conversion gain of 11.4 dB, an input referred third-order intercept point (IIP₃) of 6.1 dBm, and a noise figure of 5.87 dB. The measured total power consumption is 40.9 mW with 1 V supply.     

A 12-mW wide dynamic range CMOS front-end for a portable GPSreceiver

This paper describes a CMOS low-noise amplifier (LNA) and mixer intended for use in the front-end of a global positioning system (GPS) receiver. The circuits were implemented in a standard 0.35-μm (drawn) CMOS process, with one poly and two metal layers. The LNA has a forward gain (S21) of 17 dB and a noise figure of 3.8 dB. The mixer has a voltage conversion gain of -3.6 dB and a third-order intermodulation intercept point (IP3) of 10 dBm, input referred. The combination draws 12 mW from a 1.5-V supply     

A low power direct conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise

A low power direct-conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise is presented. The front-end includes the differential low noise amplifier, the down-conversion mixer, the LO buffer, the IF buffer and the bandgap reference. A modified common source topology is used as the input stages of the down-conversion mixer (and the LNA) to improve IIP2 of the receiver RF front-end while maintaining high IIP3. A shunt LC network is inserted into the common-source node of the switching pairs in the down-conversion mixer to absorb the parasitic capacitance and thus improve IIP2 and lower down the 1/f noise of the down-conversion mixer. The direct-conversion receiver RF front-end has been implemented in 0.18 μm CMOS process. The measured results show that the 2 GHz receiver RF front-end achieves +33 dBm in-band IIP2, 21 dB power gain, 6.2 dB NF and −2.3 dBm in-band IIP3 while only drawing 6.7 mA current from a 1.8 V power supply.     

Low-voltage 1.9-GHz front-end receiver in 0.5-μm CMOS technology

This paper describes the design of a 1.9-GHz front-end receiver. The target application of the receiver is the personal communications standard PCS1900. Powered by a 1-V supply, the receiver consists of a low noise amplifier (LNA) and a downconversion mixer. The receiver was fabricated within a 0.5-μm CMOS technology. The LNA features 15 dB of gain and a 1.8-dB noise figure. The mixer exhibits 1.5-dB conversion loss, 12-dB noise figure, and 0 dBm 1 dB-compression point     

基于90nm CMOS工艺的60GHz射频接收前端电路设计

设计了一款用于中国60 GHz标准频段的射频接收前端电路。该射频接收前端采用直接变频结构,将59～64 GHz的微波信号下变频至5～10 GHz的中频信号。射频前端包括一个四级低噪声放大器和电流注入式的吉尔伯特单平衡混频器。LNA设计中考虑了ESD的静电释放路径。后仿真表明,射频接收前端的转换增益为13.5～17.5 dB,双边带噪声因子为6.4～7.8 dB,输入1 dB压缩点为-23 dBm。电路在1.2 V电源电压下功耗仅为38.4 mW。该射频接收前端电路采用IBM 90 nm CMOS工艺设计,芯片面积为0.65 mm2。     

Design of a Noise-Canceling CMOS Wideband Receiver Front-End with Inherent Active Balun

This paper presents the design of an ESD-protected noise-canceling CMOS wideband receiver front-end for cognitive and ultra-wideband (UWB) radio-based wireless communications. Designed in a 0.13-μm CMOS technology, the RF front-end integrates a broadband low-noise amplifier (LNA) and a quadrature down-conversion mixer. While having ESD and package parasitics absorbed into a wideband input matching network, the LNA exploits a combination of a common-gate (CG) stage and a common-source (CS) stage to cancel the noise of the CG-stage and to provide a well balanced differential output for driving the double-balance mixer, which has a merged quadrature topology. A variable-gain method is developed for the LNA to achieve a large factor of gain switch without degrading the input impedance match and the balun function. Drawing 24 mA from 1.5 V, simulations show that the proposed front-end has a 3-dB bandwidth of around 10 GHz spanning from 1.8 GHz up to 11.8 GHz with a maximum voltage conversion gain of 30 dB and a noise figure of 4.3–6.7 dB over the entire band.     

A 2.7-V 900-MHz CMOS LNA and mixer

A CMOS low-noise amplifier (LNA) and a mixer for RF front-end applications are described. A current reuse technique is described that increases amplifier transconductance for the LNA and mixer without increasing power dissipation, compared to standard topologies. At 900 MHz, the LNA minimum noise figure (NF) is 1.9 dB, input third-order intercept point (IIP3) is -3.2 dBm and forward gain is 15.6 dB. With a 1-GHz local oscillator (LO) and a 900-MHz RF input, the mixer minimum double sideband noise figure (DSB NF) is 5.8 dB, IIP3 is -4.1 dBm, and power conversion gain is 8.8 dB. The LNA and mixer, respectively, consume 20 mW and 7 mW from a 2.7 V power supply. The active areas of the LNA and mixer are 0.7 mm×0.4 mm and 0.7 mm×0.2 mm, respectively. The prototypes were fabricated in a 0.5-μm CMOS process     

A 5-GHz radio front-end with automatically Q-tuned notch filter and VCO

A low-voltage receiver front-end for 5-GHz radio applications is presented. The receiver consists of a low-noise amplifier (LNA) with notch filter, a voltage-controlled oscillator (VCO), and a mixer. The LNA/notch filter has an automatic Q-tuning circuit integrated with it to provide good image rejection. On-chip transformers are used extensively in the receiver to improve performance and facilitate low-voltage operation. The receiver has a gain of 19.8 dB, noise figure of 4.5 dB, a third-order input intercept point (IIP3) of -11.5 dBm, and an image rejection of 59 dB, and the VCO had a phase noise of -116 dBc/Hz at 1-MHz offset.     

Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell

This paper presents the first quadrature RF receiver front-end where, in a single stage, low-noise amplifier (LNA), mixer and voltage-controlled oscillator (VCO) share the same bias current. The new structure exploits the intrinsic mixing functionality of a classical LC tank oscillator providing a compact and low-power solution compatible with low-voltage technologies. A 0.13-mum CMOS prototype tailored to the GPS application is presented. The experimental results exhibit a noise figure of 4.8 dB, a gain of 36 dB, an IIP3 of -19 dBm with a total power consumption of only 5.4 mW from a voltage supply of 1.2 V     

A low-power multi-band CMOS RF receiver front-end for ubiquitous sensor network applications

This paper presents the design and experimental results of a low-power multi-band RF receiver including a multi-band low-noise amplifier (LNA) and a down-conversion mixer based on the IEEE 802.15.4 standard for sensor node applications. A multi-band LNA with two inputs is tuned to two resonant frequencies by controlling the voltage on a switched MOS. The implemented RF receiver front-end achieves a maximum voltage conversion gain of 38 and 30 dB, NF of 6.2 and 9.2 dB at the 868/915 MHz and the 2.45 GHz bands, respectively. The RF receiver front-end dissipates total 3.0 mA (including I/Q mixers) under supply voltage of 1.8 V at both operation bands.     

A Subthreshold Low-Noise Amplifier Optimized for Ultra-Low-Power Applications in the ISM Band

The IEEE 802.15.4 standard relaxes the requirements on the receiver front-end making subthreshold operation a viable solution. The specification is discussed and guidelines are presented for a small area ultra-low-power design. A subthreshold biased low-noise amplifier (LNA) has been designed and fabricated for the 2.4-GHz IEEE 802.15.4 standard using a standard low-cost 0.18-mum RF CMOS process. The single-stage LNA saves on chip area by using only one inductor. The measured gain is more than 20 dB with an S₁₁ of -19 dB while using 630 muA of dc current. The measured noise figure is 5.2 dB.     

Design of Ultra-Low-Voltage RF Frontends With Complementary Current-Reused Architectures

In this paper, ultra-low-voltage circuit techniques are presented for CMOS RF frontends. By employing a complementary current-reused architecture, the RF building blocks including a low-noise amplifier (LNA) and a single-balanced down-conversion mixer can operate at a reduced supply voltage with microwatt power consumption while maintaining reasonable circuit performance at multigigahertz frequencies. Based on the MOSFET model in moderate and weak inversion, theoretical analysis and design considerations of the proposed circuit techniques are described in detail. Using a standard 0.18-mum CMOS process, prototype frontend circuits are implemented at the 5-GHz frequency band for demonstration. From the measurement results, the fully integrated LNA exhibits a gain of 9.2 dB and a noise figure of 4.5 dB at 5 GHz, while the mixer has a conversion gain of 3.2 dB and an IIP₃ of -8 dBm. Operated at a supply voltage of 0.6 V, the power consumptions of the LNA and the mixer are 900 and 792 muW, respectively.     

A 0.18μm CMOS gain-switched LNA and mixer with large dynamic range

A 2.4GHz 0.18μm CMOS gain-switched single-end Low Noise Amplifier （LNA） and a passive mixer with no external balun for near-zero-IF （Intermediate Frequency）/RF （Radio Frequency） applications are described. The LNA, fabricated in the 0.18μm 1P6M CMOS technology, adopts a gain-switched technique to increase the linearity and enlarge the dynamic range. The mixer is an IQ-based passive topology. Measurements of the CMOS chip are performed on the FR-4 PCB and the input is matched to 50Ω. Combining LNA and mixer, the front-end measured performances in high gain state are： -15dB of Sll, 18.5dB of voltage gain, 4.6dB of noise figure, 15dBm of IIP3, 85dBm to -10dBm dynamic range. The full circuit drains 6mA from a 1.8V supply.     

A 0.18μm CMOS GAIN-SWITCHED LNA AND MIXER WITH LARGE DYNAMIC RANGE

A 2.4GHz 0.18μm CMOS gain-switched single-end Low Noise Amplifier(LNA) and a passive mixer with no external balun for near-zero-IF(Intermediate Frequency)/RF(Radio Frequency) applications are described.The LNA,fabricated in the 0.18μm 1P6M CMOS technology,adopts a gain-switched technique to increase the linearity and enlarge the dynamic range.The mixer is an IQ-based passive topology.Measurements of the CMOS chip are performed on the FR-4 PCB and the input is matched to 50Ω.Combining LNA and mixer,the front...     

用于IEEE802．11b／g WLAN直接下变频接收机的射频前端设计

介绍了一种应用于IEEE802．11b／g无线局域网接收机射频前端的设计。基于直接下变频的系统架构。接收机集成了低噪声放大器、I／Q下变频器、去直流偏移滤波器、基带放大器和信道选择滤波器。电路采用TSMC0．18μm CMOS工艺设计,工作在2．4GHz ISM（工业、科学和医疗）频段,实现的低噪声放大器噪声系数为0．84dB,增益为16dB,S11低于-15dB,功耗为13mW;I／Q下变频器电压增益为2dB,输入1dB压缩点为-1 dBm,噪声系数为13dB,功耗低于10mw。整个接收机射频前端仿真得到的噪声系数为3．5dB,IIP3为-8dBm,IP2大于30dBm,电压增益为31dB,功耗为32mW。