A very high performance compact CMOS current mirror

This paper proposes a very high performance current mirror (CM), where output current accurately copies the input current without carrying any offset component. Compact implementation of Garimella et al. CM structure has been combined with super cascode configuration to achieve the proposed very high performance CM. The proposed CM offers extremely high output resistance, very low input resistance and high degree of copying accuracy over a wide operating current range. Small signal analysis is carried out to validate the performance characteristics of the circuit. The proposed CM is simulated by Mentor Graphics Eldospice in TSMC 0.18 µm CMOS, BSIM3 and Level 53 technology, using a single supply voltage of 1.5 V. The circuit is shown to have high current copying accuracy for a range of (0–500 µA) with an error less than 0.0016 % and has no offset current at the output side. The robustness of the proposed CM against the variations in device parameters and temperature changes has been reflected in simulations by carrying Monte Carlo and temperature analysis. The simulation results show that the proposed circuit provides very high output resistance of 55.76 GΩ and a very low input resistance of 0.07 Ω.     

A very high performance self-biased cascode current mirror for CMOS technology

This paper presents a novel high performance self-biased cascode current mirror (CM) for CMOS technology. The proposed circuit shows a resistance compensated high bandwidth CM operating at low voltages. This circuit uses super cascode configuration to obtain high output impedance required for high performance of CM. Active implementation of passive resistances of the proposed circuit is shown. The simulations of proposed CM are carried out by Mentor Graphics Eldospice based on TSMC 0.18 μm CMOS technology, for input current range of 0–500 μA. A bandwidth of 2.26 GHz, input and output resistances of 679 Ω and 482 MΩ respectively, are obtained with a single supply voltage of ?1 V.     

Low-voltage CMOS adjustable current mirror

A novel scheme for an adjustable low-voltage CMOS current mirror is introduced. The proposed current mirror provides continuous gain adjustment, while it simultaneously features the attractive characteristic of low-voltage operation. The behaviour of the proposed topology has been experimentally verified through a first-order lowpass filter fabricated in AMS 0.35 μm CMOS technology.     

High-swing cascode MOS current mirror

A high-swing cascode triode-region MOS current mirror, basically comprising a triode-region translinear loop, is proposed. A translinear analysis and measurement results are presented     

High-speed active-input cascode current mirror

A high-speed active-input cascode current mirror is presented. The proposed configuration combines a high output impedance with the high-frequency performance of a source- or emitter-driven active-input topology. Simulation results in a 0.35 /spl mu/m SiGe BiCMOS are presented to demonstrate the validation of the proposed current mirror. A much higher (about 30 to 40 times) output impedance is achieved, with no degradation in the high-frequency behaviour compared to conventional emitter-driven active-input current mirrors, without increasing the power consumption. The proposed configuration can be applied to both bipolar and CMOS technology.     

Low-voltage wideband compact CMOS variable gain amplifier

A novel low-voltage wideband CMOS variable gain amplifier (VGA) is proposed. Using a 0.13 /spl mu/m CMOS technology, the VGA exhibits a linear-dB controllable gain range of 40 dB with a bandwidth in excess of 130 MHz, while drawing only 50 /spl mu/A from a single 1 V power supply voltage.     

一种基于衬底驱动PMOS晶体管的低压共源共栅电流镜

基于衬底驱动PMOS晶体管设计了低压PMOS衬底驱动CMOS共源共栅电流镜电路(BDCCM),并讨论分析了其输入阻抗、输出阻抗和频率特性.基于TSMC 0.25μm 2P4M CMOS工艺的仿真和测试结果说明,BDCCM的最低输入压降要求只有0.3V,但是其输入输出线性度和频率带宽要比传统的共源共栅电流镜低,是低频低压CMOS模拟集成电路设计的新型高性能共源共栅电流镜.     

Novel high performance CMOS current conveyor

In this paper a new CMOS second generation current conveyor based on a novel voltage follower architecture is presented. Both class-A and class-AB topologies are proposed. Results from 0.8 μm designs supplied at 3.3 V show very low resistance at node X (<50 Ω), high frequency operation (100 MHz), high precision in the voltage and current transference and reduced offset. As basic application examples, a voltage-to-current converter and a current feedback operational amplifier have been considered.     

Low-voltage high-drive CMOS current feedback op-amp

A novel CMOS current feedback op-amp is presented. The solution works using a low supply voltage and provides a wide input/output swing as well as a high current driving capability. Experimental results from a prototype implemented in a 0.35-/spl mu/m technology and powered with 1.5 V are also given. The circuit exhibits a better than 500 kHz closed-loop bandwidth and a /spl plusmn/1 mA current drive capability.     

Tunable linear CMOS current mirror

Based on triode MOSFETs as tunable devices, a tunable linear current mirror is proposed, whose current gain is tunable over a wide range. Simulations show that, total harmonic distortion on the output current is within 2% for a tuning range of almost five octaves. Although the structure is in the form of an active-input current mirror, keeping the tuned MOSFETs in triode region significantly relaxes the stability problems of an active-input current mirror. This issue is revealed by theoretical analyses and further simulations are included for demonstration. An application example is also supplied.     

Compact class AB CMOS current mirror

Current mirrors are, together with differential pairs, the most common analogue building blocks in modern analogue and mixed-signal integrated circuits. Desirable features of current mirrors include: low standby power dissipation, wide input and output current swings, low supply voltage requirements, accurate current copy, and high linearity. Conventional class A topologies are unable to achieve simultaneously low quiescent power consumption and wide current swings, since they have maximum input and output currents limited by the DC bias currents. To overcome this shortcoming, class AB current mirrors have been proposed, which feature maximum currents not limited by the quiescent currents and reduced sensitivity to process tolerances [1]. Unfortunately, the additional circuitry required to achieve class AB operation often increases supply voltage requirements. For instance, the most common approach to achieve a class AB CMOS current mirror requires stacking of two MOS gate?source voltages [2]. This additional circuitry also often increases standby power consumption and adds extra intrinsic capacitances at the internal nodes. Another common issue is that quiescent currents are often dependent on supply voltage, process variations or temperature [2]. Other approaches are based on SC dynamic biasing [3], requiring the generation of two non-overlapping clock signals and suffering from charge injection errors.     

CMOS高频电流差分缓冲放大器

本文提出了一种利用修改的差分电流传输器(MDCC)与电压跟随器实现的全新高频CMOS差分电流缓冲放大器电路(CDBA).PSPICE仿真结果表明,在0～100MHz的频率范围内,提出的电路能很好地满足CDBA的端口特性.作为应用,实现了二阶电流模式多功能滤波器,并对他们进行了仿真.     

A high performance differential input CMOS current buffer

In this paper, a high accuracy CMOS differential input current buffer (CB) is proposed which employs super source followers (SSF) as input stage and regulated cascode (RGC) current mirrors as output stage. High accuracy requires very high output resistance and low input resistance. Small signal analysis is performed and it is shown that the proposed CB circuit has very low input impedances at ports n and p due to SSF transistors and also very high output impedance at output port due to RGC current mirrors. The simulation results show 9.72 Ω input resistances at ports n and p, 454 MΩ output resistance at output port with only 625 μW power consumption under ±0.9 V power supplies. The simulations are performed with HSpice using TSMC 0.18 μm process parameters and it is shown that the simulation results are in very good agreement with the theoretical ones.     

Compact implementation of high-performance CMOS current mirror

A high-performance compact current mirror implementation with very low input resistance, very high output resistance, high copying accuracy, low input and output voltage supply requirements and high bandwidth is proposed. The circuit characteristics are validated with simulations in 0.5 /spl mu/m CMOS technology and with experimental results.     

Low-voltage bulk-driven class AB four quadrant CMOS current multiplier

In this paper a low voltage bulk-driven class AB four quadrant current multiplier is proposed. For the proposed multiplier a bulk-driven class AB current mode cell has been developed and the drain current equations for NMOS and PMOS transistors of the proposed cell have been derived. This cell is used as a basic building block for bulk-driven low voltage current squarer and copier circuit, which is finally used as the fundamental building block of the proposed low-voltage bulk-driven current multiplier operating at ±1 V. All the circuits are simulated using SPICE for 0.25 μm CMOS technology.     

A new compact temperature-compensated CMOS current reference

This paper describes a new circuit integrated on silicon, which generates temperature-independent bias currents. Such a circuit is firstly employed to obtain a current reference with first-order temperature compensation, then it is modified to obtain second-order temperature compensation. The operation principle of the new circuits is described and the relationships between design and technology process parameters are derived. These circuits have been designed by a 0.35 /spl mu/m BiCMOS technology process and the thermal drift of the reference current has been evaluated by computer simulations. They show good thermal performance and in particular, the new second-order temperature-compensated current reference has a mean temperature drift of only 28 ppm//spl deg/C in the temperature range between -30/spl deg/C and 100/spl deg/C.     

Low-voltage subthreshold CMOS current mode circuits: Design and applications

The world has migrated to portable applications ranging from smart phones to Lab on a Chip applications. However they come with a new set of challenges for analog IC designers. Low voltage operation, small area and low noise are the critical design criteria for portable devices. This paper presents a g_m/I_D based design methodology for low voltage current mode circuits using standard CMOS technology. A second generation current conveyor (CCII) and a current feedback operational amplifier (CFA) are designed using the discussed design procedure. Both circuits operate from a single 0.4 V supply. The CCII is used to implement an instrumentation amplifier. Multiple applications are implemented using the CFA. Post layout simulation using TSMC 90 nm and UMC 130 nm technology show that the presented design procedure is an attractive solution for low voltage CMOS current mode circuits.     

Self-biasing of folded cascode CMOS op-amps

In cascode CMOS op-amps a large number transistors are biased using independent standard bias circuits. This results in numerous drawbacks, namely, an area and power overhead, and high sensitivity of the bias point to process variations. In this paper we present a self-biasing technique for folded cascode CMOS op-amps that uses no additional devices and no bias voltages other than the two supply rails. The resulting self-biased op-amps are free from the above mentioned drawbacks and exhibit the same performance as existing folded cascode op-amps. This is achieved by following transistor sizing constraints derived through detailed circuit analysis. The technique is applied to an existing high performance op-amp. Simulation results show that the high performance is maintained while nine bias voltages are eliminated.     

Enhancing general performance of folded cascode amplifier by recycling current

A modification to the conventional folded cascode transconductance amplifier is proposed. The proposed amplifier has the benefit of achieving a given set of design specifications while consuming a fraction of the power compared to the conventional folded cascode. Moreover, the proposed modification is robust even for low voltage applications.