Low supply voltage operation of over-40-Gb/s digital ICs based on parallel-current-switching latch circuitry

We implemented a low-voltage latch circuit topology in a full-rate 4:1 multiplexer (MUX) using InP-HBT technology. The proposed latch circuitry incorporates parallel current switching together with inductive peaking a combination that makes it suitable for over-40-Gb/s operation at supply voltages ranging from 1.5 to 1.8 V. The full-rate 4:1 MUX provided 40-Gb/s error-free operation with a power dissipation of only 1 W at a supply voltage of 1.8 V. The D-flip/flop (D-F/F) based on this latch circuitry provided 50-Gb/s D-F/F operation at a supply voltage as low as 1.5 V. Demultiplexing operation was also confirmed for the D-F/F with this circuit technology at a data rate of up to 110Gb/s with a 1.8-V supply voltage. The latch circuitry should help enable development of a low-voltage 40-Gb/s full-rate module which can be seamlessly connected with high-speed CMOS I/O circuits.     

SiGe-HBT-based 54-gb/s 4:1 multiplexer IC with full-rate clock for serial communication systems

A 4:1 multiplexer (MUX) IC for 40 Gb/s and above operations in optical fiber link systems has been developed. The ICs are based on 122-GHz-f/sub T/ 0.2-/spl mu/m self-aligned selective-epitaxial-growth SiGe HBT technology. To reduce output jitter caused by clock duty distortion, a master-slave delayed flip-flop (MS-DFF) with full-rate clock for data retiming is used at the final stage of the MUX IC. In the timing design of the critical circuit for full-rate clocking, robust timing design that has a wide timing margin between data and clock at the MS-DFF was achieved. Measurements using on-wafer probes showed that the MUX attained 54-Gb/s operation with an output voltage-swing of 400 mVpp. The output rms jitter generated by the MUX was 0.91 ps and tr/tf (10%-90%) was 11.4/11.3 ps at a data rate of 50 Gb/s. Power consumption of the IC was 2.95 W at a power supply of -4.8 V. Error-free operation (<10/sup -12/) in back-to-back configuration of the MUX and a 1:4 DEMUX IC module at a data rate of 45 Gb/s was confirmed. We therefore concluded that the MUX IC can be applied for transmitter functions in optical-fiber-link systems at a data rate of 40 Gb/s and higher for forward error correction.     

4-bit multiplexer/demultiplexer chip set for 40-Gbit/s optical communication systems

We have designed and fabricated a low-power 4:1 multiplexer (MUX), 1:4 demultiplexer (DEMUX) and full-clock-rate 1:4 DEMUX with a clock and data recovery (CDR) circuit using undoped-emitter InP-InGaAs HBTs. Our HBTs exhibit an f/sub T/ of approximately 150 GHz and an f/sub max/ of approximately 200 GHz at a collector current density of 50 kA/spl mu/m/sup 2/. In the circuit design, we utilize emitter-coupled logic and current-mode logic series gate flip-flops and optimized the collector current density of each transistor to achieve low-power operation at required high bit rates. Error-free operation at bit rates of up to 50 Gbit/s were confirmed for the 4:1 MUX and 1:4 DEMUX, which dissipates 2.3 and 2.5 W, respectively. In addition, the full-clock-rate 1:4 DEMUX with the CDR achieved 40-Gbit/s error-free operation.     

A 30-gb/s 70-mW one-stage 4:1 multiplexer in 0.13-/spl mu/m CMOS

A completely integrated 4:1 multiplexer for high-speed operation and low power consumption is presented. The circuit uses a new architecture where four data streams are multiplexed in one stage. Pulses with a duty cycle of 25% switch the inputs to the multiplexer (MUX) output. The pulses are generated from the clock signal and the divided clock signal. Measurement results show the performance of the IQ divider. Current-mode logic is used because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. The multiplexer uses no output buffer and directly drives the 50-/spl Omega/ environment. The lower number of gates compared to the conventional tree topology enables low-power design. Relaxed timing conditions are additional benefits of the one-stage MUX topology. The IC is fabricated in a 0.13-/spl mu/m standard bulk CMOS technology and uses 1.5-V supply voltage. The MUX works up to 30 Gb/s and consumes 70 mW.     

A 80-gbit/s D-type flip-flop circuit using InP HEMT technology

80-Gbit/s operation of a static D-type flip-flop (D-FF) circuit was achieved using InP-based HEMT technology, which has a cut-off frequency of 245 GHz and a transconductance of 1500 mS/mm. The circuit was designed with differential operation based on source-coupled FET logic (SCFL). To overcome deterioration of the 80-GHz clock signals in a single-ended to differential signal converter in the input buffer, a rat-race circuit was used as a converter. Measurements showed that the circuit achieved a gain of over 2 dB higher than a conventional converter using a differential pair circuit, and power consumption was reduced from 380 to 260 mW. The power supply voltage was -5.7 V, and total power consumption was 1.2 W. Since there is no commercially available 80-Gbit/s-pulse pattern generator, we developed a selector module to measure the D-FF. These measurements showed that the D-FF successfully operated at 80 Gbit/s, which is almost twice the speed reported to date.     

A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector

We describe a 40-Gbit/s-class clock and data recovery (CDR) circuit with an extremely wide pull-in range. A Darlington-type voltage-controlled oscillator (VCO) is newly designed to cover the STM-256/OC-768 full-rate-clock frequencies with a wide frequency margin. We also describe a new lock detector using an exclusive-NOR gate. The CDR IC was fabricated using InP/InGaAs HBTs. Error-free operation and wide eye opening were confirmed for 40-, 43-, and 45-Gbit/s PRBS with a word length of 2/sup 31/ - 1. We attached a frequency search and phase control (FSPC) circuit to the chip as a new frequency acquisition aid, and this allows the CDR circuit to pull in throughout a 39-45-Gbit/s range. The peak-to-peak and rms jitter of the recovered clock were 3.6 and 0.48 ps, respectively.     

5?Gb/s 2:1 fully-integrated full-rate multiplexer with on-chip clock generation circuit in 0.18-μm CMOS

A 5?Gb/s 2:1 full-rate multiplexer (MUX) has been designed and fabricated in SMIC 0.18-??m CMOS process. A clock generation circuit (CGC) is also integrated to provide the MUX with both 2.5 and 5-GHz clock signals. The CGC is realized by a clock and data recovery (CDR) loop with a divide-by-2 frequency divider embedded in, where the two required clocks are obtained after and before the divider, respectively. In addition, the phase relation between data and clock is assured automatically by CDR feedback loop and the precise layout. The whole chip area is 812?×?675???m, including pads. At a single supply voltage of 1.8?V, the total power consumption is 162?mW with an input sensitivity of <25?mV and a single-ended output swing of above 300?mV. And due to the full-rate architecture, the pulse width distortion (PWD) with multiplexed data is removed. The measured results also show that the circuit can work reliably at any input data rate between 2.46 and 2.9?Gb/s without need for external components, reference clock, or manual phase alignment between data and clock.     

SiGe clock and data recovery IC with linear-type PLL for 10-Gb/sSONET application

An integrated 10 Gb/s clock and data recovery (CDR) circuit is fabricated using SiGe technology, It consists of a linear-type phase-locked loop (PLL) based on a single-edge version of the Hogge phase detector, a LC-tank voltage-controlled oscillator (VCO) and a tri-state charge pump. A PLL equivalent model and design method to meet SONET jitter requirements are presented. The CDR was tested at 9.529 GB/s in full operation and up to 13.25 Gb/s in data recovery mode. Sensitivity is 14 mV_pp at a bit error rate (BER)=10^-9 . The measured recovered clock jitter is less than 1 ps RMS. The IC dissipates 1.5 W with a -5 V power supply     

50 Gbit/s 2:1 multiplexer in 0.13 /spl mu/m CMOS technology

A fully integrated 2:1 multiplexer IC which operates at up to 50 Gbit/s data rate is presented. The MUX uses inductive shunt peaking and an output series inductor for higher bandwidth. The MUX directly drives the 50 /spl Omega/ load. The IC is fabricated in a 0.13 /spl mu/m bulk CMOS technology and draws 65 mA at 1.5 V supply voltage. The output voltage swing is 2/spl times/100 mV.     

A 43-Gb/s full-rate-clock 4:1 multiplexer in InP-based HEMT technology

This paper describes a full-rate-clock 4:1 multiplexer (MUX) in a 0.13-/spl mu/m InP-based HEMT technology for 40-Gb/s and above optical fiber link systems. To reduce output jitter, the serialized data are retimed at the final stage by a retimer, a D-type flip-flop, which has a symmetric layout with an optimized spacing to the ground that minimizes coupling capacitances. A phase adjuster, composed of an exclusive OR and a delay switch, uses external control signals to change each phase of the serialized data and clock entering the retimer and gives a correct timing for the clock to drive the retimer. A clock distributor with a simple wired splitter divides the clock into two clocks with high gain and low current. The MUX integrates 1355 HEMTs formed using electron beam lithography. A chip mounted in a test module operated at up to 47 Gb/s with a power consumption of 7.9 W for a single supply voltage of -5.2 V.     

Low-power 50 Gbit/s InP HBT 1:4 demultiplexer IC with multiphase clock architecture

An InP HBT 1:4 demultiplexer IC with a multiphase clock architecture is described that reduces the number of circuit elements and power consumption while maintaining operating speed. The IC operated at 50 Gbit/s with 1.17 W power consumption at a supply voltage of -4.5 V. Compared to an IC with a conventional tree-type architecture using the same InP HBTs, the power consumption is less than half while the operating speed of 50 Gbit/s is maintained.     

A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique

A 20-Gb/s clock and data recovery circuit incorporates injection-locking technique to achieve high-speed operation with low power dissipation. The circuit creates spectral line at the frequency of data rate and injection-locks two cascaded LC oscillators. A frequency-monitoring mechanism is employed to ensure a close matching between the VCO natural frequency and data rate. Fabricated in 90-nm CMOS technology, this circuit achieves a bit error rate of less than 10^-9 in both continuous (PRBS of 2³¹-1) and burst modes while consuming 175 mW from a 1.5-V supply.     

A packaged high-performance decision IC up to 45-Gb/s

A packaged D-type flip-flop (DFF) decision circuit for optical OC-768 systems and testing equipment is reported. The circuit uses 1 /spl mu/m InP SHBT technology featuring f/sub T//f/sub max/=150 GHz and has been operated up to 45 Gb/s with a clock phase margin about 180/spl deg/. Measured output eye diagrams from packaged devices exhibit 9/8 ps rise/fall with only 3ps peak-peak jitter. A single-ended AC-coupled clock input makes the application of this circuit very convenient. The IC dissipates 440 mW from a -4V supply voltage.     

A high resolution frequency multiplier for clock signal generation

This paper presents a high resolution frequency multiplier (FMUL) with the ability to multiply frequency with a programmable high multiplication factor, in the order of 10²-10⁴ and of the form N/M. It was designed for chip-sets that use a real time clock (32768 Hz) for power-save operation, and an additional high-frequency oscillator, in the range of 40-60 MHz, for regular operation. Using the FMUL spares the need for the additional high-frequency oscillator. The FMUL's frequency resolution is 100 ppm, and its jitter is less than 200 ps. The circuit is designed to work with 25 V supply voltage. It is implemented in a standard 0.8 pm N-well CMOS process, and its area is 0.48 mm²     

A rail-to-rail ping-pong op-amp

A rail-to-rail ping-pong op-amp achieves offset cancellation and 1/f noise reduction without folding of the input spectrum. The clocking scheme minimizes the clock feedthrough and the residual offset due to charge injection. With a clock frequency of 100 kHz, the residual offset is less than 100 μV, and the input referred noise is about 225 nV/Hz ^1/2. The rail-to-rail distortion at 1 kHz is lower than -71 dB. The total silicon area is 610×420 μm², and the circuit dissipates 1.5 mW from a single 5 V supply     

A 150 mW 8:1 MUX and a 170 mW 1:8 DEMUX for 2.4 gb/s optical-fibercommunication systems using n-AlGaAs/i-InGaAs HJFET's

An 8:1 multiplexer (MUX) and a 1:8 demultiplexer (DEMUX) for 2.4-Gb/s optical communication systems have been developed using 0.35-μm GaAs heterojunction field-effect transistors (FETs). To ensure timing margins, a new timing generator with latches and new clock buffers with cross-coupled inverters have been developed. These large-scale integrations (LSIs) operate at over 2.4 Gb/s with a power consumption of 150 mW (MUX) and 170 mW (DEMUX) at a supply voltage of 0.7 V, and at over 5 Gb/s with power consumption of 200 mW at a supply voltage of 0.8 V     

40-Gbit/s TDM transmission technologies based on ultra-high-speedICs

This paper presents 40-Gbit/s time division multiplexing (TDM) transmission technologies based on 0.1-μm-gate-length InP high electron mobility transistor IC's and a scheme for upgrading toward a terabit-per-second capacity system. A 40-Gbit/s, 300-km, in-line transmission experiment and a dispersion-tolerant 40-Gbit/s duobinary transmission experiment are described as 40-Gbit/s single carrier system applications on dispersion-shifted fiber. An ultra-high-speed receiver configuration using a high-output-power photodiode is introduced to realize fully electrical receiver operation beyond 40 Gbit/s. The high-sensitivity operation of the optical receiver (-27.6 dBm@BER=10^-9) is demonstrated at a data bit rate of 50 Gbit/s for the first time using a unitraveling carrier photodiode. A dense wavelength division multiplexing (DWDM) system operating up to terabits per second can be easily realized on a zero-dispersion flattened transmission line using ultra-high speed TDM channels of 40 Gbit/s and beyond. An experiment demonstrates 1.04-Tbit/s DWDM transmission based on 40-Gbit/s TDM channels with high optical spectrum density (0.4 bit/s/Hz) without dispersion compensation     

A -80 dB THD, 4 Vpp switched capacitor filter for 1.5 Vbattery-operated systems

A fully differential fifth-order SC filter that can operate from power supplies as low as 1.5 V featuring a -80 dB THD up to 4 V_pp output voltage is presented. A measured p-weighted noise of 120 μV_rms leads to a dynamic range of 81.5 dB. This circuit is used as reconstruction filter for a low voltage 14-b DAC. The very low voltage operation has been possible by integrating a regulated voltage-multiplier on the same chip. The filter active area is 0.54 mm ² in a 0.8 μm CMOS technology. Typical power consumption is 0.8 mW at 1.5 V supply     

2.5 Gb／s 16：1 MUX IC Design with CMOS

A low--power and high--speed 16.-1 MUX IC designed for optical fiber communication based on TSMC 0.25μm CMOS technology is presented. A tree—type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak—to—peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8mm^2.     

A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer

This work presents a quad-channel serial-link transceiver providing a maximum full duplex raw data rate of 12.5Gb/s for a single 10-Gbit eXtended Attachment Unit Interface (XAUI) in a standard 0.18-/spl mu/m CMOS technology. To achieve low bit-error rate (BER) and high-speed operation, a mixed-mode least-mean-square (LMS) adaptive equalizer and a low-jitter delay-immune clock data recovery (CDR) circuit are used. The transceiver achieves BER lower than <4.5/spl times/10/sup -15/ while its transmitted data and recovered clock have a low jitter of 46 and 64 ps in peak-to-peak, respectively. The chip consumes 178 mW per each channel at 3.125-Gb/s/ch full duplex (TX/RX simultaneous) data rate from 1.8-V power supply.