RF power performance evaluation of surface channel diamond MESFETs

We experimentally investigate the large-signal radio frequency performances of surface-channel p-type diamond MESFETs fabricated on hydrogenated polycrystalline diamond. The devices under examination have a coplanar layout with two gate fingers, total gate periphery of 100 μm; in DC they exhibit a hole accumulation behavior with threshold voltage V_t ≈ 0-0.5 V and maximum drain current density of 120 mA/mm. The best small-signal radio frequency performances (maximum cutoff or transition frequency f_T and oscillation frequency f_max) were obtained close to the threshold and were of the order of 6 and 15 GHz, respectively. The power radio frequency response was characterized by driving the devices in class A at an operating frequency of 2 GHz and identifying through the active load-pull technique the optimum load for maximum power added efficiency. A power gain in linearity of 8 dB and an output power of approximately 0.2 W/mm with 22% power added efficiency were obtained on the optimum load impedance at a bias point V_DS = −14 V, V_GS = −1 V. To the best of our knowledge, these are the first large signal measurements ever reported for surface MESFET on polycrystalline diamond, and show the potential of such technology for the development of microwave power devices.     

Light emission of GaAs power MESFETs under RF drive

Light emission from microwave power GaAs MESFETs was observed under rf operating conditions. It is shown that the light emission occurs at the drain side of the gate stripe and the light intensity can be correlated with the rf input drive and the output power saturation characteristic of the device.     

Effects of RF life-test on LF electrical parameters of GaAs power MESFETs

Ion-implanted power MESFETs have been submitted to RF life-test under gain compression. Devices went through RF life-test with no significant dynamic performance drift but with DC parameter evolution. A complete electrical characterisation performed by low frequency gate and drain noise analysis combined with drain current transient spectroscopy revealed that no degradation has occurred in the channel. An increase by two orders of magnitude of the LF gate noise level points out a degradation located in the vicinity of the gate.     

A new unified approach to power quality management

A new control algorithm for a power converter-based device that is capable of alleviating the problems of harmonic interference and voltage regulation on radial distribution lines is introduced. It comprises a relocatable converter in series with a passive filter and is known as the Power Quality Manager. Simulation results based on an existing 88-kV line are presented. Experimental results are presented, based on a three-phase 200-VA scaled model of the existing 88-kV system. It is a cost-effective and flexible solution to improving power quality     

Failure analysis for RF characteristics of GaAs MESFETs

The effect of thermal stress on the noise degradation of GaAs MESFETs was investigated. Minimum noise figure, associated gain, scattering parameters, and capacitance–voltage profiles were measured during the tests, and the electro-chemical properties after thermal stress were analyzed by means of Auger electron spectroscopy, X-ray diffractometery, cross-sectional transmission electron microscopy, and capacitance–voltage measurements. The RF failure mode consists of an increase of the minimum noise figure and a decrease of associated gain of the FETs. The extracted equivalent circuit elements from measured scattering parameters were used to evaluate the influence of each parameter on the noise degradation. The parametric estimation showed that the noise degradation was mainly attributed to the decrease of a.c. transconductance. From the C–V analysis, we found that the decrease of a.c. transconductance was caused by the decrease of effective carrier concentration. From the electro-chemical analysis, the decrease in effective carrier concentration was resulted from the gate-sinking by the thermally activated interdiffusion between the gate metal and the GaAs channel layer. Therefore, the thermally activated carrier compensation by Ga vacancies in the channel is proposed to be the main failure mechanism for noise degradation of GaAs MESFETs.     

3.3 V operation GaAs power MESFETs with 65% power-added efficiencyfor hand-held telephones

High-low doped metal semiconductor field effect transistors (MESFETs) operating at a drain bias of 3.3 V have been developed. The MESFETs with 0.6 μm gate length and 12 mm gate width show a maximum drain current density of 310 mA/mm and a uniform transconductance of around 112 mS, ranging from V_gs=-1.8 V to 0.5 V. The device tested at 3.3 V drain bias and 900 MHz demonstrates an output power of 30.9 dBm with associate power-added-efficiency of 65% for an input power of 20 dBm     

A new approach to extracting the RF parameters of asymmetric DG MOSFETs with the NQS effect

In analog circuit design an important parameter,from the perspective of superior device performance,is linearity.The DG MOSFET in asymmetric mode operation has been found to present a better linearity.In addition to that it provides,at the discretion of analog circuit designer,an additional degree of freedom,by providing independent bias control for the front and the back gates.Here a non-quasi-static(NQS)small signal model for DGMOSFET with asymmetric gate bias is proposed for extracting the parameters of the device using TCAD simulations.The parameters extracted here for analysis are the intrinsic front and back gate to drain capacitance,Cgd1and Cgd2,the intrinsic front and back distributed channel resistance,Rgd1and Rgd2respectively,the transport delay,m,and the inductance,Lsd.The parameter extraction model for an asymmetric DG MOSFET is validated with pre-established extracted parameter data,for symmetric DG MOSFET devices,from the available literature.The device simulation is performed with respect to frequency up to 100 GHz.     

A new mathematical approach to multi-area power system reliability evaluation

In the original interconnected system reliability model the system state space consists of a set of all n-tuples X = (x₁, x₂,…, x_l, x_l+1,…, x_n) where x₁, x₂, x₃,…, x_l are generation capacities and x_l+1, …, x_n are intertie capacities. Corresponding to each load state i we have state space S_i. For each S_i there exists a map F_i:S_i → R. For each i, S_i is then decomposed into sets of acceptable states A_ks and sets of unacceptable states B_ls. Each B_l is then classified accordingly as it is a loss of load in a particular area or not. Then the appropriate reliability indices are calculated. In this approach the maximal flow function is viewed as a map F: _iS_i → R. It is shown that F is a piecewise linear function. It is also shown that there is a one-one correspondence between B sets with the same area loss of load to each of the linear functions. A useful result which aids in the reduction of computational time of frequency calculation of loss of load is then derived.     

Self-heating and trapping effects on the RF performance of GaN MESFETs

RF power performances of GaN MESFETs incorporating self-heating and trapping effects are reported. A physics-based large-signal model is used, which includes temperature dependences of transport and trapping parameters. Current collapse and dc-to-RF dispersion of output resistance and transconductance due to traps have been accounted for in the formulation. Calculated dc and pulsed I-V characteristics are in excellent agreement with the measured data. At 2 GHz, calculated maximum output power of a 0.3 /spl mu/m/spl times/100 /spl mu/m GaN MESFET is 22.8 dBm at the power gain of 6.1 dB and power-added efficiency of 28.5% are in excellent agreement with the corresponding measured values of 23 dBm, 5.8 dB, and 27.5%, respectively. Better thermal stability is observed for longer gate-length devices due to lower dissipation power density. At 2 GHz, gain compressions due to self-heating are 2.2, 1.9, and 0.75 dB for 0.30 /spl mu/m/spl times/100 /spl mu/m, 0.50 /spl mu/m/spl times/100 /spl mu/m, and 0.75 /spl mu/m/spl times/100 /spl mu/m GaN MESFETs, respectively. Significant increase in gain compression due to thermal effects is reported at elevated frequencies. At 2-GHz and 10-dBm output power, calculated third-order intermodulations (IM3s) of 0.30 /spl mu/m/spl times/100 /spl mu/m, 0.50 /spl mu/m/spl times/100 /spl mu/m, and 0.75 /spl mu/m/spl times/100 /spl mu/m GaN MESFETs are -61, -54, and - 45 dBc, respectively. For the same devices, the IM3 increases by 9, 6, and 3 dBc due to self-heating effects, respectively. Due to self-heating effects, the output referred third-order intercept point decreases by 4 dBm in a 0.30 /spl mu/m/spl times/100 /spl mu/m device.     

A new approach to power estimation and reduction in CMOS digital circuits

Modelling and optimization of dynamic capacitive power consumption in digital static CMOS circuits, taking into consideration a reason of a gate switching—gate control mode, is discussed in the present paper. The term ‘gate control mode’ means that a number and type of signals applied to input terminals of the gate have an influence on total amount of energy dissipated during a single switching cycle. Moreover, changes of input signals, which keep the gate output in a steady state, can also cause power consumption. Based on this observation, complex reasons of power losses have been considered. In consequence, the authors propose a new model of dynamic power consumption in static CMOS gates. Appropriate parameters’ calculation method for the new model was developed. The gate power model has been extended to logic networks, and consequently a new measure of the circuit activity was proposed. Switching activity, which is commonly used as a traditional measure, characterizes only the number of signal changes at the circuit node, and it is not sufficient for the proposed model. As the power consumption parameters of CMOS are dependent on their control mode, the authors used probability of the node control mode as a new measure of the circuit activity. Based on the proposed model, a procedure of combinational circuit optimization for power dissipation reduction has been developed. The procedure can be included in a design flow, after technology mapping. Results of the power estimation received for some benchmark circuits are much closer to SPICE simulations than values obtained for other methods. So the model proposed in this study improves the estimation accuracy. Additionally, we can save several percent of the consumed energy.     

A new approach to evaluate two area interconnected power generating systems reliability

This paper presents the developed application of a new approach to evaluate Loss of Load Probability (LOLP) of two area interconnected power systems consisting of different types and sizes of generating units considering independent as well as correlated system demands. This approach uses hourly loads, or any suitable time interval for system demand, for a given period. The Probability Density Function (p.d.f.) of equivalent load is obtained by convolving the p.d.f. of generating unit outages with the p.d.f. of system demands using a new approach. The proposed approach can simulate multistate representation of generating units as well. The LOLP values for each system are obtained from the p.d.f. of equivalent load. This method is applied to two interconnected systems and the results obtained are compared with those obtained using existing methods. It is found that this approach is efficient, exact and easy to apply compared with other methods.     

Symptoms of stress-induced gain degradation in power MESFETs

GaAs metal-semiconductor field effect transistors configured as microwave power amplifiers have been observed to degrade under normal device operations at high gate-to-drain fields. The nature of this degradation is an increase in the gate current, with a subsequent decrease in the gain. We present evidence that crystallographic defects in the active region are responsible for this “power slump” and that these defects originate during device operation due to the high strain fields which exist as the result of passivation layer processing. Strain data and x-ray topographic images support our assertion that passivation layer processing induces high strain in and around the gate-to-drain region of the device. Topographic images show that an increase in dislocation density occurs in the highly stressed regions after power slump. By varying deposition parameters, we can produce passivation films, which induce less stress in the active region, resulting in less dislocation generation and a less severe power slump.     

A hybrid inverse approach applied to the design of lumped-element RF coils

A combination of inverse procedures is employed in the design of radio-frequency (RF) coils with specific examples in, but not restricted to, magnetic resonance imaging. The first inverse procedure is the use of functional methods for the optimization of coil characteristics subject to restrictions on the field behavior. Continuous current distributions are derived from analysis of the fields they are required to produce. To make use of these distributions at a desired frequency, the method of moments is applied as a second inverse procedure to a discretized version of the current distribution. The advantage of this hybrid technique is that it provides a computational algorithm for optimization of feeding, tuning, impedance matching and other aspects of RF coil design. A prototype RF coil has been built using the engineering values predicted by the theory. Experimental results including images acquired from the prototype coil are presented.     

Simulating power electronic systems—A new approach

The time-varying topology created by the switch-mode operation of power semiconductor devices in energy conversion systems presents difficulties in analysis. Presently available methods for simulating the behavior of these systems include the use of the digital computer, the conventional analog computer, and the breadboard. A new philosophically distinct technique called "parity simulation" produces a topologically isomorphic transformation of the system under study; that is, it exhibits a 1:1 correspondence, or parity, with the structure of the actual network. A parity simulator utilizes terminal equivalent representations of network elements. The microcomputer based interface is highly user oriented. Nonlinear or time-varying element parameters are easily incorporated. Several simulation examples are presented.     

Improvement of RF performance of GaAs/Si MESFETs using buriedoxygen implantation

A novel buried oxygen implantation (BOI) procedure is described to reduce parasitics and improve RF performance of GaAs/Si MESFETs. Devices fabricated with this procedure show output conductance of less than 8.5 mS/mm which is the lowest reported to date for GaAs/Si MESFETs. These results are particularly important to improve the power performance of GaAs/Si MESFETs     

A new elementary operation approach to multidimensional realization and LFR uncertainty modeling: the SISO case

In this paper, a new elementary operation approach is proposed to the problem of multidimensional (n-D) Roesser state-space model realization or linear fractional representation (LFR) uncertainty modeling. The new approach can overcome the main difficulties encountered by Galkowski’s approach and always generates a standard or regular realization for a given causal n-D transfer function. In particular, the n-D realization problem is formulated as an elementary operation problem of a certain n-D polynomial matrix in a way totally different from Galkowski’s approach so that the singularity problem can be completely avoided. A general constructive realization procedure and an algorithm for evaluating the realization order associated with this procedure will be proposed, which can be easily implemented by symbolic software in, e.g., MATLAB or Maple. Some further techniques for a realization with lower order will also be shown. Symbolic and numerical examples will be presented throughout the paper to illustrate the basic ideas as well as the effectiveness of the proposed approach.     

Distributed scaling approach of MESFETs and its comparison with thelumped-element approach

An appropriate scaling procedure is described for large four-finger MESFET cells with experimental verification. A comparison is presented between lumped and distributed modeling approaches. The scalability of elements in the equivalent circuit model of a MESFET is discussed     

Evidence of detrimental surface effects on GaAs power MESFETs

GaAs power FETs submitted to biased life tests show a gradual degradation resulting in an output power loss and changes on DC characteristics such as gate-to-drain breakdown voltage and gate leakage current. It is shown that this degradation is correlated with surface effects.     

Resonant tunneling transistor lasers: A new approach to obtain multi-state switching and bistable operation

Bipolar resonant tunneling heterotransistor structures, which can be configured to operate as multi-state or as bistable lasers, are described. Both edge and surface-emitting structures are presented. Computations of various optoelectronics parameters including confinement factor, threshold current density, and cavity modes for a stripe-geometry structure are presented. In addition, simulations of base and collector currents are given for a resonant tunneling transistor to demonstrate the feasibility of lasing in the base region.     

A new decoupled algorithm for nonstationary, transient simulationsof GaAs MESFETs

Simulation of devices for which nonlocal, hot carrier transport cannot be ignored requires solution of the Poisson equation and at least the first three moments of the Boltzmann transport equation or the use of Monte Carlo techniques. These equations form nonlinear, coupled, time-dependent partial differential equations. In conventional decoupled solvers, decoupling of the equations puts a limit on the maximum allowable time step Δt, which should be kept smaller than the dielectric relaxation time τ_d of the material. This constraint makes these solvers very inefficient, especially for obtaining steady-state solutions. A highly efficient decoupled numerical algorithm which allows Δt as large as 20-50 times τ _d is presented. Results of simulations of GaAs MESFETs using both a conventional and the new decoupled solver and CPU time taken on a CRAY Y-MP by the two solvers are discussed