软件的性能设计

本文概要介绍了大型软件系统性能设计的误区,指出性能设计应该是设计过程的一个必备环节.根据实际的性能设计经验,作者提出了性能设计的基本要求和主要方法.     

电波暗室静区性能及设计要点

静区性能是电波暗室综合性能的体现,也是暗室设计的关键.分析了静区性能对试验的影响程度,以此作为确定暗室静区指标和暗室设计的依据,论述了影响静区性能的各种因素以及保证静区性能的设计要点.     

混合动力汽车动力系统的仿真与设计

本文介绍了混合动力汽车动力系统的基本设计方法,根据设计的性能要求对动力系统参数进行了设计,用电动汽车仿真软件ADVISOR对整车性能进行了仿真计算,验证了参数设计的合理性。     

无线网络优化平台数据库性能优化设计思路

由于无线上网记录数据量呈现指数级增长,导致数据加载、数据处理和数据查询出现严重的性能下降。基于此,提出利用时间价值分级、精准索引设计、混合分区设计、并行处理机制和高效SQL设计方法等技术设计角度应对性能瓶颈的优化设计思路。主要从数据增长对系统资源的需求入手逐步诊断性能问题和性能瓶颈,分析数据的增长对数据库性能下降和出现性能瓶颈的影响,针对系统运行中遇到的实际问题进行优化设计。经上海电信无线网络优化平台现网实验测试表明,运用上述优化设计方法组合设计可以很好地解决数据库性能问题,大大提高了数据库性能。     

数字视频记录仪接地设计

介绍了电子产品性能设计的重要性,详细阐述了性能设计之接地设计的技术和方法,并将该技术和方法应用到视频记录仪的电路设计中,提高了设备性能指标。     

具有良好S距离特性QPP交织器的设计

交织器的设计对提高Turbo码的性能有着重要的影响。首先研究了QPP交织器的设计原则,给出了具有良好S距离特性的QPP交织的设计方法。仿真结果表明:设计得到的QPP交织器的性能并不比通过随机搜索得到的一般S-随机交织器性能差。     

水下高频低损耗水密同轴电缆的研制

为了满足复杂多变的海洋环境对海洋信息处理设备以及传输元器件较高的信息传输可靠性要求,研制了一款兼具纵向水密性能与高频低损耗性能的水下高频低损耗水密同轴电缆.围绕纵向水密性能设计、高频低损耗性能设计、低电压驻波比性能设计技术难点,对所研制的电缆从水密同轴电缆结构组成、使用材料、性能设计、试验验证等方面进行了详尽的论述.经...     

一种CPU模块的测试设计

论述了对一种CPU模块的测试设计,此测试设计为了检测该种CPU模块的功能和性能.在设计过程中,首先,对该CPU模块的功能和性能进行了分析,并在此基础上,提出了测试需求,同时根据测试需求设计了测试方法.最后,通过对这种CPU模块的功能和性能进行测试和验证,为设计人员提供了设计和测试建议.     

基于HOOPS的三维协同设计中实时通信系统的研究与实现

协同设计中的实时通信性能是衡量该协同设计系统性能的重要指标,实时通信系统所提供的网络环境能否及时的将各设计终端的设计操作反映在服务器和其他的设计端直接决定了该协同系统协同性能的高低。在对现有的实时通信系统深入研究得基础上,给出了一个基于HOOPS的三维协同设计系统中的实时通信系统的实现框架、机制和具体的方法。     

高性能FPGA设计

本文分析了FPGA的基本结构．提出了提高FPGA性能的两个途径：面向器件设计、最少布线设计，可大幅度提高FPGA设计的性能。     

Rapid design space exploration using legacy design data and technology scaling trend

Rapid and effective design space exploration at all stages of a design process enables faster design convergence and shorter time-to-market. This is particularly important during the early stage of a design where design decisions can have a significant impact on design convergence. This paper describes a methodology for design space exploration using design target prediction models. These models are driven by legacy design data, technology scaling trends and, an in situ model-fitting process. Experiments on ISCAS benchmark circuits validate the feasibility of the proposed approach and yielded power centric designs that improved power by 7-32% for a corresponding 0-9% performance impact; or performance centric designs with improved performance of 10.31-17% for a corresponding 2-3.85% power penalty. Evolutionary algorithm based Pareto analysis on an industrial 65 nm design uncovered design tradeoffs which are not obvious to designers and optimize both power and performance. The high performance design option of the industrial design improved the straight-ported design's performance by 29% with a 2.5% power penalty, whereas the low power design option reduced the straight-ported design's power consumption by 40% for a 9% performance penalty.     

Optimization Design for Digital Binoculars

In order to develop competitive and high performance/cost ratio of digital binoculars, design scheme should be optimized in term of technical capacity, economic benefit, product performance, risk management, etc. The common optimization method is limited in qualitative analysis, and the parameter optimization method is limited in obtaining optimal parameter only from technical side. Each method has its limitation. Based on the analysis of digital binoculars parameters, optional design schemes are laid down.Analytic hierarchy process combined the qualitative analysis with the quantitative analysis together. The design schemes are optimized, and result is worked out.     

变容管电调微波带通滤波器

本文叙述采用梳状线结构的变容管电调微波带通滤波器的设计理论和方法。推导出梳状线带通滤波器的输入、输出耦合网络的参数条件,以补偿带通滤波器的谐振器之间电磁耦合随不同调谐频率的变化;并给出使带通滤波器的绝对带宽或通带回波损耗在调谐频率范围内变化最小时,梳状线谐振器的电长度应满足的相应条件,由此来保证电调带通滤波器在较宽的调谐频率范围内具有较高的通带回波损耗,且保持带通滤波器的响应形状和绝对带宽基本不变。此外,还讨论了由电调变容管的Q值引起的带通滤波器的通带有功损耗问题。文中给出了具体的设计公式。最后,给出了一个L波段变容管电调带通滤波器的研制实例和测试结果。     

A regular fabric design methodology for applications requiring specific layout-level design rules

Regular fabrics have been introduced as an approach to bridge the gap between ASICs and FPGAs in terms of cost and performance. Indeed, compared to an ASIC, by predefining most of the manufacturing masks, they highly reduce time-to-market, non-recoverable engineering costs and lithography hazards. Also, thanks to hardwired configuration and interconnections their performance is closer to those of ASICs than those of FPGAs. They are therefore well suited to many applications requiring low to medium volume applications or higher performance than those provided by FPGAs.In this paper, we evaluate the interest of using a regular fabric to reduce time and design cost significantly in applications involving specific transistor level design (radiative/spacial conditions, side-channel attacks, NMR environment, etc.). With this aim in view, after a broad state of the art overview with an emphasis on architectures and design flows, we develop our approach of a regular fabric designed to limit layout level design, ad-hoc tools and technological migration cost. Then, we evaluate its performance in a 65 nm process versus FPGA and standard cell based ASIC implementations. For sequential designs, our proposed solution is on average 2.5×slower and 2.3×bigger than a standard cell implantation, but also on average 13×faster than a FPGA.     

A Sigma-Delta ADC design automation tool with embedded performance estimator

A system-level design automation tool for designing discrete time, switched-capacitor, Sigma-Delta analog-to-digital converters is presented. The presented work utilizes a performance estimator based on EKV models. The design automation tool takes advantage of high level analytical single-bit and multibit models of the building blocks. With the contribution of the performance estimator module, the tool provides an extensive design environment for designing Sigma-Delta analog-to-digital converters. Developed models and their effects are presented with examples. Design examples for 0.5 and technologies are provided for proving the flexibility of the design automation tool.     

柔性设计技术在高性能数字信号处理器设计中的应用

本文提出大规模集成电路的柔性设计技术。将该技术应用到一种高性能DSP的设计中,解决了多晶硅电阻大、衬底接触孔问题,简化了工艺,提高了成品率和可靠性,降低了研发成本。     

一种用于图象处理的二维开关电容滤波器新的设计系统

本文描述二维实时滤波器开关电容网络的新的设计方法。该设计是在综合法的基础上,利用无损、非倒数原形电路而得到的开关电容网络。本文所使用的几个计算机软件,均已写好并调试,可将其集成为一个完整的设计系统。本文作为该设计系统的实际应用,举例设计一个二维高性能滤波器,该滤波器可以像一个CMOS单片那样实现。若与数字滤波器实现相比较,可达到降低成本和减少功耗的目的。     

卫星导航抗干扰专用芯片后端版图设计

随着电磁环境的日益复杂,卫星导航接收系统的抗干扰性能要求越来越高。在小型卫导接收系统的抗干扰设计中,体积和功耗已经成为最大的限制因素,抗干扰芯片的设计已成为解决该问题的有效途径。本文基于SoC Encounter后端版图设计工具,通过布局规划、电源设计、标准单元放置、时钟树综合及优化、布线等后端版图设计流程,完成了一款卫星导航抗干扰专用芯片的后端版图设计工作。     

X波段1.5WGaAsMMIC研究

介绍了Ｘ波段１．５Ｗ ＧａＡｓＭＭＩＣ的设计、制作和性能测试,包括ＭＥＳＦＥＴ大信号模型的建立、电路ＣＡＤ优化、ＤＯＥ灵敏度分析及Ｔ型栅工艺研究等。微波测试结果为： 在频率９．４～１０．２ＧＨｚ下, 输出功率大于３２ｄＢｍ , 增益大于１０ｄＢ。     

机器的设计过程

设计的过程是一个不断解决问题的过程,是一个项目管理的过程,是将不明了的问题转化为最终产品的过程。设计过程的成功与否决定了设计的价值,决定了最终产品的成本、质量和开发产品所需的时间。