Amplifier techniques for combining low noise, precision, and high-speed performance

A monolithic operational amplifier is presented which optimizes voltage noise both in the audio frequency band, and in the low frequency instrumentation range. In addition, the design demonstrates that the requirements for low noise do not necessitate compromising the specifications in other respects. Techniques are set forth for combining low noise with high-speed and precision performance for the first time in a monolithic amplifier. Achieved results are: 3 nV//spl radic/Hz white noise, 80 nV/SUB p-p/ noise from 0.1 to 10 Hz, 17 V//spl mu/s slew rate, 63 MHz gain-bandwidth product, 10 /spl mu/V offset voltage, 0.2 /spl mu/V//spl deg/C drift with temperature, 0.2 /spl mu/V/month drift with time, and a voltage gain of two million.     

A dual-path bandwidth extension amplifier topology with dual-loop parallel compensation

A dual-path amplifier topology with dual-loop parallel compensation technique is proposed for low-power three-stage amplifiers. By using two parallel high-speed paths for high-frequency signal propagation, there is no passive capacitive feedback network loaded at the amplifier output. Both the bandwidth and slew rate are thus significantly improved. Implemented in a 0.6-/spl mu/m CMOS process, the proposed three-stage amplifier has over 100-dB gain, 7-MHz gain-bandwidth product, and 3.3-V//spl mu/s average slew rate while only dissipating 330 /spl mu/W at 1.5 V, when driving a 25-k/spl Omega///120-pF load. The proposed amplifier achieves at least two times improvement in bandwidth-to-power and slew-rate-to-power efficiencies than all other reported multistage amplifiers using different compensation topologies.     

Low-voltage high-gain differential OTA for SC circuits

A new differential operational transconductance amplifier (OTA) for SC circuits that operates with a supply voltage of less than two transistor threshold voltages is presented. Its simplicity relies on the use of a low-voltage regulated cascode circuit, which achieves very high output impedance under low-voltage restrictions. The OTA has been designed to operate with a supply voltage of V/sub DD/=1.5 V, using a 0.6 /spl mu/m CMOS technology with transistor threshold voltages of V/sub TN/=0.75 V and V/sub TP/=-0.85 V. Post-layout simulation results for a load capacitance (C/sub L/) of 2 pF show a 75 MHz gain-bandwidth product and 100 dB DC gain with a quiescent power consumption of 750 /spl mu/W.     

Optical receiver IC for CD/DVD/blue-laser application

In this paper, an optoelectronic receiver IC for CD, DVD, and Blue-Laser optical data storage applications is presented. The IC was developed in a 0.5-/spl mu/m BiCMOS technology with integrated PIN photodiodes. It includes a new architecture of high-speed and low-noise variable gain transimpedance amplifiers witch current preamplifier input. The amplifier transimpedance gain is programmable over a gain range of 130 /spl Omega/ to 270 k/spl Omega/ by a serial interface. The amplifier small-signal bandwidth is 260 MHz for the highest gain, which gives a gain-bandwidth product of 70 THz/spl Omega/ and a sensitivity improvement by a factor of 2 compared to published OEICs. The amplifiers support a special write/clip mode which realizes a nonlinear gain reduction for high input signals. The output voltage buffers are 130-/spl Omega/ impedance matched for optimized data transmission over a flex cable. The impedance is generated by active-impedance synthesis to increase the output dynamic range.     

A miniature 25-GHz 9-dB CMOS cascaded single-stage distributed amplifier

A 25-GHz complementary metal oxide semiconductor (CMOS) cascaded single-stage distributed amplifier (CSSDA) using standard 0.18-/spl mu/m CMOS technology is presented in this letter. It demonstrates the highest gain-bandwidth product (GBP) with smallest chip area reported for a fully-integrated CMOS wideband amplifier using a standard Si-based integrated circuit process. The chip size including testing pads is only 0.36mm/sup 2/, and the ratio of GBP to chip size achieves 552GHz/mm/sup 2/. This circuit is the first CSSDA realized in CMOS technology, and represents state-of-the-art performances.     

Active-feedback frequency-compensation technique for low-power multistage amplifiers

An active-feedback frequency-compensation (AFFC) technique for low-power operational amplifiers is presented in this paper. With an active-feedback mechanism, a high-speed block separates the low-frequency high-gain path and high-frequency signal path such that high gain and wide bandwidth can be achieved simultaneously in the AFFC amplifier. The gain stage in the active-feedback network also reduces the size of the compensation capacitors such that the overall chip area of the amplifier becomes smaller and the slew rate is improved. Furthermore, the presence of a left-half-plane zero in the proposed AFFC topology improves the stability and settling behavior of the amplifier. Three-stage amplifiers based on AFFC and nested-Miller compensation (NMC) techniques have been implemented by a commercial 0.8-/spl mu/m CMOS process. When driving a 120-pF capacitive load, the AFFC amplifier achieves over 100-dB dc gain, 4.5-MHz gain-bandwidth product (GBW) , 65/spl deg/ phase margin, and 1.5-V//spl mu/s average slew rate, while only dissipating 400-/spl mu/W power at a 2-V supply. Compared to a three-stage NMC amplifier, the proposed AFFC amplifier provides improvement in both the GBW and slew rate by 11 times and reduces the chip area by 2.3 times without significant increase in the power consumption.     

Regenerator chip set for high-speed digital transmission

The authors have developed a custom two-chip set containing all of the active circuitry necessary for regeneration of digital electrical signals in a 300-Mb/s fiber-optic transmission system. The set includes an automatic gain control (AGC) amplifier with gain-bandwidth product in excess of 100 GHz, and a decision circuit with excellent dynamic sensitivity, measured up to 650 Mb/s. The chips are fabricated using a 2.5-/spl mu/m fully complementary bipolar process.     

Amplification at 258 GHz Using a Saturated Gas Resonance

A 258-GHz reflection amplifier was built which consisted of a cylindrical cavity (3 mm diam., 7 mm Iength) filled with hydrogen cyanide gas at pressures up to 0.1 torr. When the molecular resonance of the J = 2/spl rarr/3 rotational transition of H/sup 12/C/sup 15/N and the cavity resonance coincided, about 100 /spl mu/W of the monochromatic pump-power were sufficient to saturate the two-level quantum system. The pumped gas furnished a nonlinear (power-sensitive) impedance which was used to amplify weak AM-sidebands. The signal was reflected with a maximum gain of 20 dB and a bandwidth of 0.5 MHz. The variation of the amplification with gas pressure, pump power, frequency, Q-values, and cavity tuning was measured and analyzed. The low unloaded Q-value of the TE(O, 1, 11) resonator, the limited pump power available at 258 GHz, and matching difficulties prevented attainment of the theoretical gain-bandwidth product of 37 MHz at room temperatures. A measurement performed at 200/spl deg/K indicated a threefold increase of this gain-bandwidth product.     

InP D-HBT ICs for 40-Gb/s and higher bitrate lightwave transceivers

The combination of device speed (f/sub T/, f/sub max/ > 150 GHz) and breakdown voltage (V/sub bceo/ > 8 V) makes the double heterojunction bipolar InP-based transistor (D-HBT) an attractive technology to implement the most demanding analog functions of 40-Gb/s transceivers. This is illustrated by the performance of a number of analog circuits realized in an InP D-HBT technology with an 1.2- or 1.6-/spl mu/m-wide emitter finger: a low phase noise push-push voltage-controlled oscillator with -7-dBm output power at 146 GHz, a 40-GHz bandwidth and low-jitter 40-Gb/s limiting amplifier, a lumped 40-Gb/s limiting driver amplifier with 4.5-V/sub pp/ differential output swing, a distributed 40-Gb/s driver amplifier with 6-V/sub pp/ differential output swing, and a number of distributed preamplifiers with up to 1.3-THz gain-bandwidth product.     

Simple planar structure for high-performance AlInAs avalanche photodiodes

We demonstrate a high-performance AlInAs avalanche photodiode (APD) based on a novel planar diode concept. The APD features a simple planar structure without a guardring, which simplifies production making it more like a PIN photodiode process. Measured device characteristics designed for 10-Gb/s use were a dark current of 0.16 /spl mu/A, responsivity of 0.88 A/W, and a gain-bandwidth product of 120 GHz. Reliability was guaranteed by an aging test exceeding 2400 h, whose conditions were a reverse dark current of 100 /spl mu/A at 175/spl deg/C. These features and performance indicate that the AlInAs APD is highly practical.     

Low-power InP/GaAsSb/InP DHBT cascode transimpedance amplifier with GBP/P/sub dc/ of 7.2 GHz/mW

A low-power high gain-bandwidth monolithic cascode transimpedance amplifier using novel InP/GaAsSb/InP DHBT technology was investigated. The amplifier exhibited state-of-the-art performance of 17.3 dB gain, 12 GHz bandwidth, 55 dB/spl Omega/ transimpedance, and a corresponding gain-bandwidth of 6.7 THz/spl Omega/ while consuming only 12.2 mW DC power. It also achieved good gain-bandwidth-product per DC power figure-of-merit (GBP/P/sub dc/) of 7.2 GHz/mW     

HBT matrix amplifier with gain-cell enhancing gain and bandwidth

A 2 /spl mu/m InGaP/GaAs heterojunction bipolar transistor (HBT) matrix amplifier with a new gain cell achieving 17.2 dB gain and 41 GHz bandwidth is reported. Using the gain-bandwidth products per transistor f/sub t/ and f/sub max/ as the figures of merit for measuring the effectiveness of amplifier design, it achieves 4.72 and 4.43, respectively, demonstrating among the best-reported bipolar broadband amplifiers     

0.5-V analog circuit techniques and their application in OTA and filter design

We present design techniques that make possible the operation of analog circuits with very low supply voltages, down to 0.5 V. We use operational transconductance amplifier (OTA) and filter design as a vehicle to introduce these techniques. Two OTAs, one with body inputs and the other with gate inputs, are designed. Biasing strategies to maintain common-mode voltages and attain maximum signal swing over process, voltage, and temperature are proposed. Prototype chips were fabricated in a 0.18-/spl mu/m CMOS process using standard 0.5-V V/sub T/ devices. The body-input OTA has a measured 52-dB DC gain, a 2.5-MHz gain-bandwidth, and consumes 110 /spl mu/W. The gate-input OTA has a measured 62-dB DC gain (with automatic gain-enhancement), a 10-MHz gain-bandwidth, and consumes 75 /spl mu/W. Design techniques for active-RC filters are also presented. Weak-inversion MOS varactors are proposed and modeled. These are used along with 0.5-V gate-input OTAs to design a fully integrated, 135-kHz fifth-order elliptic low-pass filter. The prototype chip in a 0.18-/spl mu/m CMOS process with V/sub T/ of 0.5-V also includes an on-chip phase-locked loop for tuning. The 1-mm/sup 2/ chip has a measured dynamic range of 57 dB and draws 2.2 mA from the 0.5-V supply.     

Long-wavelength In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As large-area avalanche photodiodes and arrays

Large-area (500-/spl mu/m diameter) mesa-structure In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As avalanche photodiodes (APDs) are reported. The dark current density was /spl sim/2.5/spl times/10/sup -2/ nA//spl mu/m/sup 2/ at 90% of breakdown; low surface leakage current density (/spl sim/4.2 pA//spl mu/m) was achieved with wet chemical etching and SiO/sub 2/ passivation. An 18 /spl times/ 18 APD array with uniform distributions of breakdown voltage, dark current, and multiplication gain has also been demonstrated. The APDs in the array achieved 3-dB bandwidth of /spl sim/8 GHz at low gain and a gain-bandwidth product of /spl sim/120 GHz.     

Reversed nested Miller compensation with voltage buffer and ing resistor

This paper presents a new reversed nested Miller compensation technique for multistage operational amplifier (opamp) design. The new compensation technique inverts the sign of the right half complex plane zero and shifts the frequency of the complex conjugate poles to a higher frequency. Simulation results indicate that the gain-bandwidth product and settling time are improved by factors of two and three, respectively, without degrading stability and power consumption. To verify the proposed technique, a three-stage opamp is fabricated with 0.6-/spl mu/m CMOS technology. The measured results of the test circuit agree with the results that are obtained from theoretical analysis and circuit simulation.     

Operational amplifier integrators for the measurement of the delay times of microwave transistors

A simple low frequency technique for the measurement of subnanosecond delay times with an operational amplifier connected as a summing integrator is described. Previous integrator theory is extended to incorporate second-order effects. The operational amplifier gain-bandwidth product is shown to set a limit to the sensitivity of the integrator. For a gain-bandwidth product of 1 GHz the smallest measurable delay time is estimated to be about 5 ps, which is small enough for measurements on the fastest microwave transistors. Expressions for the delay times of transistors are derived from the hybrid-/spl pi/ model. Examples of measured delay times of microwave transistors are given and the results are compared with theoretical predictions.     

220-GHz metamorphic HEMT amplifier MMICs for high-resolution imaging applications

In this paper, the development of 220-GHz low-noise amplifier (LNA) MMICs for use in high-resolution active and passive millimeter-wave imaging systems is presented. The amplifier circuits have been realized using a well-proven 0.1-/spl mu/m gate length and an advanced 0.05-/spl mu/m gate length InAlAs/InGaAs based depletion-type metamorphic high electron mobility transistor technology. Furthermore, coplanar circuit topology in combination with cascode transistors was applied, leading to a compact chip size and an excellent gain performance at high millimeter-wave frequencies. A realized single-stage 0.05-/spl mu/m cascode LNA exhibited a small-signal gain of 10 dB at 222 GHz, while a 0.1-/spl mu/m four-stage amplifier circuit achieved a linear gain of 20 dB at the frequency of operation and more than 10 dB over the bandwidth from 180 to 225 GHz.     

Low-Voltage Super class AB CMOS OTA cells with very high slew rate and power efficiency

A simple technique to achieve low-voltage power-efficient class AB operational transconductance amplifiers (OTAs) is presented. It is based on the combination of class AB differential input stages and local common-mode feedback (LCMFB) which provides additional dynamic current boosting, increased gain-bandwidth product (GBW), and near-optimal current efficiency. LCMFB is applied to various class AB differential input stages, leading to different class AB OTA topologies. Three OTA realizations based on this technique have been fabricated in a 0.5-/spl mu/m CMOS technology. For an 80-pF load they show enhancement factors of slew rate and GBW of up to 280 and 3.6, respectively, compared to a conventional class A OTA with the same 10-/spl mu/A quiescent currents and /spl plusmn/1-V supply voltages. In addition, the overhead in terms of common-mode input range, output swing, silicon area, noise, and static power consumption, is minimal.     

Continuous-time common-mode feedback for high-speed switched-capacitor networks

This paper deals with the design of a continuous-time common-mode feedback (CMFB) for switched-capacitor networks. Its reduced input capacitance decreases the capacitive load at the output of the fully differential amplifier, improving its achievable gain-bandwidth (GBW) product and slew rate. This topology is more suitable for high-speed switched-capacitor applications when compared to a conventional switched-capacitor CMFB, enabling operation at higher clock frequencies. Additionally, it provides a superior rejection to the negative power supply noise (PSRR/sup -/). The performance of the CMFB is demonstrated in the implementation of a second-order 10.7-MHz bandpass switched-capacitor filter and compared with that of an identical filter using the conventional switched-capacitor CMFB (SC-CMFB). The filter using the continuous-time CMFB reduces the error due to finite GBW and slew rate to less than 1% for clock frequencies up to 72 MHz while providing a dynamic range of 59 dB and a PSRR/sup -/>22 dB. Both circuits were fabricated in 0.35-/spl mu/m CMOS technology.     

一种提高GaAs HBT放大器增益带宽积的技术

提出了一种提高GaAsHBT共射共基宽带放大器增益带宽积的技术,给出了一种宽带补偿的改进型共射共基宽带增益单元。小信号分析表明:在相同半导体工艺条件下,基于这种改进型电路结构的放大器具有更高的增益带宽积。采用2μmInGaP/GaAsHBT晶体管工艺,分别设计了无高频损耗补偿和具有高频损耗补偿电路的共射共基放大器,并成功流片,在同样测试条件下,新的增益单元其增益带宽积达到了原来的近400%。