基于FPGA的动态可重构边缘检测系统设计

根据当前硬件实时图像边缘检测易受噪声影响的特点,采用了对图像进行高通滤波预处理,提取边缘特征之后再使用Sobel算子进行边缘检测的方法,并且为了提高芯片资源利用率,利用Xilinx公司FPGA的动态可重构特性,对高通滤波和So-bel算法进行分时复用,通过比较,证明取得了理想的效果。     

Low-complex processing element architecture for successive cancellation decoder

A low-complexity design architecture for implementing the Successive Cancellation (SC) decoding algorithm for polar codes is presented. Hardware design of polar decoders is accomplished using SC decoding due to the reduced intricacy of the algorithm. Merged processing element (MPE) block is the primary area occupying factor of the SC decoder as it incorporates numerous sign and magnitude conversions. Two’s complement method is typically used in the MPE block of SC decoder. In this paper, a low-complex MPE architecture with minimal two’s complement conversion is proposed. A reformulation is also applied to the merged processing elements at the final stage of SC decoder to generate two output bits at a time. The proposed merged processing element thereby reduces the hardware complexity of the SC decoder and also reduces latency by an average of 64%. An SC decoder with code length 1024 and code rate 1/2 was designed and synthesized using 45-nm CMOS technology. The implementation results of the proposed decoder display significant improvement in the Technology Scaled Normalized Throughput (TSNT) value and an average 48% reduction in hardware complexity compared to the prevalent SC decoder architectures. Compared to the conventional SC decoder, the presented method displayed a 23% reduction in area.     

More on the decoder error probability for Reed-Solomon codes

A combinatorial technique similar to the principle of inclusion and exclusion is used to obtain an exact formula for P_E (u), the decoder error probability for Reed-Solomon codes. The P_E(u) for the (255, 223) Reed-Solomon code used by NASA and for the (31, 15) Reed-Solomon code (JTIDS code) are calculated using the exact formula and are observed to approach the Qs of the codes rapidly as u gets large. An upper bound for the expression |P_E(u)/ Q-1| is derived and shown to decrease nearly exponentially as u increases     

一种基于AFSS的可重构天线设计

针对5G智能天线双频工作,提出一种基于有源频率选择表面（active frequency selective surface, AFSS）的可重构天线,该天线由蝶形频率可重构馈源和八棱柱形AFSS构成,馈源采用的是共面波导方式馈电的蝶形单极子. AFSS由对称弯钩状缝隙的周期结构构成,通过PIN二极管进行加载,使得AFSS能够在3.4～3.6 GHz和4.8～5.0 GHz两个5G频段互为反射模式和透射模式. 利用AFSS对馈源天线激励的电磁波进行空间调控,可实现两个频段的全向和定向波束的切换,也可实现水平面波束扫描. 根据仿真设计的天线模型进行设计加工和实际测试,结果表明:该天线的工作频段可以覆盖以上两个频段,低频定向波束增益为7.6 dBi,高频定向波束增益为8.6 dBi;并且能实现高/低频双波段切换、全向/定向波束切换和水平面内360°波束扫描功能. 该天线具有波束切换灵活、功耗低、造价低等特点,在新一代无线通信系统中具有一定的应用价值.     

一种基于FPGA的Turbo码译码器的设计

主要论述了一种基于FPGA的Turbo码译码器的设计。首先简单介绍了编码器和交织器的原理;然后介绍了基于Max-Log-MAP算法的译码器原理,详细论述了各个子模块;最后给出了系统仿真的误码率图形。     

Multi-hour, multi-traffic class network design for virtualpath-based dynamically reconfigurable wide-area ATM networks

The virtual path (VP) concept has been gaining attention in terms of effective deployment of asynchronous transfer mode (ATM) networks in recent years. In a recent paper, we outlined a framework and models for network design and management of dynamically reconfigurable ATM networks based on the virtual path concept from a network planning and management perspective. Our approach has been based on statistical multiplexing of traffic within a traffic class by using a virtual path for the class and deterministic multiplexing of different virtual paths, and on providing dynamic bandwidth and reconfigurability through virtual path concept depending on traffic load during the course of the day. In this paper, we discuss in detail, a multi-hour, multi-traffic class network (capacity) design model for providing specified quality-of-service in such dynamically reconfigurable networks. This is done based on the observation that statistical multiplexing of virtual circuits for a traffic class in a virtual path, and the deterministic multiplexing of different virtual paths leads to decoupling of the network dimensioning problem into the bandwidth estimation problem and the combined virtual path routing and capacity design problem. We discuss how bandwidth estimation can be done, then how the design problem can be solved by a decomposition algorithm by looking at the dual problem and using subgradient optimization. We provide computational results for realistic network traffic data to show the effectiveness of our approach. We show for the test problems considered, our approach does between 6% to 20% better than a local shortest-path heuristic. We also show that considering network dynamism through variation of traffic during the course of a day by doing dynamic bandwidth and virtual path reconfiguration can save between 10% and 14% in network design costs compared to a static network based on maximum busy hour traffic     

基于S-PIN二极管的频率可重构天线设计

基于固态等离子体表面P-I-N(S-PIN)二极管设计了一款可重构天线,该天线用多个S-PIN单元代替金属作为辐射器。在一种激励模式下,天线作为单极子天线辐射;在另一种激励模式下,天线作为偶极子天线进行辐射。天线实现了X波段到Ka波段的频率可重构,即在X波段和Ka波段分别有2个工作频点,2个频段均有广泛用途,可适用于一些要求宽频带范围内频率可重构的场合。     

资源限制型可重构并行信息处理方法

针对立方体钠卫星GNC信息处理系统高计算性能与低功率消耗相矛盾的问题,提出了一种资源限制型可重构并行信息处理方法。该方法采用紧耦合可重构并行信息处理架构,将GNC信息处理中需要多次迭代计算且不适合CPU处理的复杂软件算法,以动态部分重构硬件电路单元（DPR）的方式实现,采用基于互斥量的多核并行可重构资源调度算法,通过多核CPU并行管理与调度共享的DPR单元,完成软件算法的硬件加速与优化。实验结果表明,该方法实现了立方星GNC信息处理系统的高效实时快速处理,与传统信息处理方法相比,可节约50%左右的功耗,可应用于计算资源极为有限的星上信息处理领域,具有很好的工程应用前景。     

基于DVD应用的流水线RS-PC解码的VLSI设计

基于DVD数据纠错的应用，设计实现了全程流水线处理的RS-PC解码，采用分解的无逆BM(Berlekamp—Massey)算法和脉动时序控制实现RS解码器的三级流水线处理，采用行列独立的缓冲器和纠错解码器实现行列纠错的两级流水线处理。该RS-PC解码能达到非常快的处理速度，在行列纠错处理无迭代的情况下，数据率可达到每时钟一个字节。     

可重用AVS芯片结构软硬件协同设计

根据软硬件设计思想设计一个结构划分合理的可重用的AVS视频解码器结构.通过ARM平台软件移植,然后使用ARM ESL工具对系统模块性能进行整体评估,然后根据评估结果以及硬件实现复杂度进行软硬件结构的划分,定制软硬件模块接口,从硬件扩展考虑把硬件部分设计为与H.264解码器兼容并用SystemC模拟,最后在SOC Designer 平台做协同验证及仿真.     

网络结构自调整的柔性内涵初探

从微观和定量意义的服务效果对应用要求一致匹配的角度探索了网络重构柔性的内涵,具体地揭示了跟随应用时变要求的时变信道这一可重构网络的核心特征,然后从该时变信道"一致满足"应用要求的目标出发,进一步揭示了重构柔性的"渐变跟随"、"着眼整体"、"隐性隔离"和"自主驱动"4个重要内涵,采用指数移动平均、n:m表决、马尔科夫决策和强化学习定量地刻画了效果对要求的稳定偏离和资源调整幅度的最佳顺序决策。     

基于PCI总线的MPEG-2解码插卡软件接口设计

介绍一种基于PCI局部总线的MPEG－2多节目传输流实时解码卡的硬件接口及上层软件设计，上层软件通过分析硬盘存储的多节目传输流给出节目信息，然后根据用户输入选择一路节目播放，发送模块将硬盘中的编码数据通过PCI总线发送到解码卡，在解码卡上通过专用解码芯片实时解码并显示，上层软件采用多线程方式实现内存与PCI总线，内存与硬盘之间的交替数据传输，文中给出了软件设计思想和结构。     

基于DSP的机载选呼解码器设计

针对机载电子设备综合化的需求,本文以DSP处理器为核心实现了机载选择呼叫数字化解码器系统,利用数字信号处理算法设计解码方法及通过状态机方法设计解码控制流程,完成解码纯软件化实现.通过在高强度噪声环境下仿真实验及某型飞机试验室实验,验证了系统的有效性.     

Reconfigurable topology synthesis for application-specific NoC on partially dynamically reconfigurable systems

In this paper, a four-stage method for synthesizing reconfigurable ASNoC topology is proposed for partially dynamically reconfigurable systems, where the topology is reconfigured dynamically at run-time along with the application's execution. Firstly, a simulated annealing based topology-aware integrated optimization framework is proposed to generate the proper schedule and floorplan of task modules. Secondly, based on the schedule and floorplan of task modules, an Integer Linear Programming (ILP)-based method and a heuristic method, are proposed to partition the communication requirements of the application into $T$ time intervals. Thirdly, we explore the proper positions of switches in the floorplan for global communications. Finally, considering the reconfiguration costs between adjacent time intervals, the routing path allocation problem is solved for time intervals in an iterative procedure to generate fine-grained dynamically reconfigurable ASNoC topologies. Experimental results show that, compared to the random partition of communication requirements, the proposed heuristic method and ILP-based method can achieve 5.4% and 10.0% power consumption improvement, respectively. And, the reconfigurable ASNoC can achieve 31.6% power consumption improvement when compared with static ASNoC.     

基于流水线映射的粗粒度可重构运算阵列电路设计

媒体处理算法内在的并行性推动了媒体处理器朝着运算阵列架构的方向发展.在分析了算法映射对电路执行效果的影响后,将运算阵列设计与算法映射相结合,针对如何有效利用阵列提出了一种流水线映射的方案,并分析了该映射方法对系统性能的影响.在此基础之上,以H 264中的IDCT算法为例提取流水线模型,并基于该模型设计出了粗粒度的可重构阵列.实验结果表明,该阵列在功耗、速度、器件利用率等方面具有明显优势,具有较好的应用价值.     

基于级联码的信道编译码设计与FPGA实现

介绍了RS(255,223)码级联卷积(4,3,3)码编译码器的实现,对于编码和译码端不同的结构特点.分别采用并行和串行结构实现.其中RS译码采用欧几里德算法,卷积译码采用维特比算法.同时给出了该编译码器的FPGA实现,按照自上而下的设计流程,在保证速度的同时最大限度地减少了资源占用.     

基于机顶盒VoIP语音解码模块的设计与验证

随着三网融合和机顶盒行业的发展,机顶盒应用功能的扩展已成为机顶盒厂商取得行业竞争优势的重要途径。本文基于重庆微电子有限公司机顶盒VoIP项目,提出一种VoIP解码模块的设计方案,重点探讨了影响机顶盒VoIP解码端实时性和语音质量的主要因素,并根据这些因素从语音编解码算法选取、解码端缓存方案,终端控制策略3个角度给出解决方案。最后,结合项目其它模块资源对VoIP系统进行测试,验证了机顶盒VoIP解码模块设计方案的可行性,为项目后续开发奠定了基础。     

基于MBSE的微波统一测控系统测试性设计

针对当前微波统一测控系统研制中存在的测试性要求宽松、测试性设计模式落后的问题,通过综合权衡可靠性、维修性和保障性的各项要求和约束条件,确定了微波统一测控系统的测试性定量要求,并对开展测试性定量设计和验证的可行性进行了论证;采用系统工程设计思想,将测试性设计和功能设计融合,构建了基于模型的系统工程（Model-based Systems Engineering,MBSE）的测试性设计环境和设计流程,可为微波统一测控系统在数字化研制过程中开展测试性设计和仿真验证提供参考。     

基于Multisim 12的正交编码器与解码器的电路设计与仿真

正交编码器用于检测旋转运动系统的位置和速度。因为正交编码器具有良好的抗噪声性能,能有效消除脉冲边缘震荡造成的干扰,在测速时能有效提高准确性,所以,正交编码与解码器的配合使用实现了对多种电机的闭环控制,从而达到精确控制。这里以Multisim 12软件为平台,模拟设计了正交编码与解码器,可以较直观地展现正交编码器与解码器的电路原理与工作过程,为深入了解、学习正交编码与解码器提供了更多途径,同时为Multisim 12学习者提供一些资料与便利。     

FPGA实现IRIG-B(DC)码编码和解码的设计

为达到IRIG-B码与时间信号输入、输出的精确同步,采用现代化靶场的IRIG-B码编码和解码的原理,从工程的角度出发,提出了使用现场可编程门阵列(FPGA)来实现IRIG-B玛编码和解码的设计方案和体系结构,设计中会涉及到几个不同的时钟频率,FPGA对时钟的同步性具有灵活性、效率高、且功耗低,抗干扰性好的特点.结果表明,FPGA能够确保为从设备提供同源的时钟基准,使时钟与信号的延迟控制在200ns以内,从而得到了IRIG-B码与时间精确同步的效果.