Testability of artificial neural networks: A behavioral approach

Testability analysis of neural architectures can be performed at a very high abstraction level on the computational paradigm. In this paper, we consider the case of feed-forward multi-layered neural networks. We introduce a behavioral error model which allows good mapping of the physical faults in widely different implementations. Conditions for error controllability, observability and global testability are analytically derived; their purpose is that of verifying whether it is possible to excite all modeled errors and to propagate the error's effects to the primary outputs (actual test vectors being then technological-dependent). Mapping of physical faults onto behavioral errors is performed for some representative, architectures.     

Testability analysis and fault modeling of BiCMOS circuits

Defect models have been used for testability analysis of BiCMOS circuits and the results have been compared with an analysis of CMOS circuits. Using a nominal point approach, faults generated are classified as logical or performance degradation faults. It is found that logical fault testing can only cover a small percentage of the total fault set, 54% for BiCMOS, versus 69% for equivalent CMOS gates. Delay faults and current faults are analyzed as applied to BiCMOS and CMOS gates. It is shown that logical fault testing in conjunction with either delay fault testing or current fault testing promises the highest fault coverage for BiCMOS logic gates, around 95%.This research was partially supported by the Department of National Defence of Canada, Academic Research Program, grant # 3705-921.     

光电跟踪系统测试性分析与评估

可测试性设计是提高武器装备可用度,降低全寿命费用中的重要环节.光电跟踪系统是舰载武器系统的重要组成部分,对其进行可测试性分析与评估是装备技术保障的重要工作.提出了利用测试性建模技术对光电跟踪系统的测试性进行分析评估的方法,能为装备的测试性设计和快速维修保障提供重要参考.     

忆阻自突触Hopfield神经网络的动力学分析与电路仿真

通过理论分析和仿真的方法,研究了一种4维忆阻自突触Hopfiled神经网络(以下简称MAHNN)的动力学行为及其仿真电路的实现.首先,分析了MAHNN能够产生复杂动力学行为的基本条件.其次,利用常规的动力学分析方法如分岔图、李氏指数、相轨迹图和时域图,分析了它的动力学行为.MATLAB数值仿真结果揭示了MAHNN存在与...     

免清洗焊接工艺与在线测试的兼容性

介绍了电路板组装免清洗工艺及其与在线测试的兼容性问题 ,并提出了相应的对策     

Testability of parity checkers

Checkers are used in digital circuits to detect both intermittent and stuck-at faults. The most common error detectors are parity checkers. Such circuits are themselves subject to failures. The use of parity trees is outlined, and techniques for testing them are surveyed. The effect of the checker's structure on its testability is discussed. Several fault models are considered: single stuck-at, multiple stuck-at, and bridging faults. The effectiveness of single stuck-at fault test sets in detecting multiple stuck-at and bridging faults is described. Upper bounds for the double fault coverage of the minimal single fault test are given for different tree structures. The testabilities of some selected checkers are examined to illustrate the concepts developed. A built-in self-test is proposed     

Information capacity of the Hopfield model

The information capacity of general forms of memory is formalized. The number of bits of information that can be stored in the Hopfield model of associative memory is estimated. It is found that the asymptotic information capacity of a Hopfield network ofNneurons is of the orderN^{3}b. The number of arbitrary state vectors that can be made stable in a Hopfield network ofNneurons is proved to be bounded above byN.     

可测性度量的计算及研究

本文对ＳＣＯＡＰ可测性度量方法作了改进，提出了动态ＳＣＯＡＰ算法。此算法反映测试生成过程中系统和电路各节点可测性的变化，比静态ＳＣＯＡＰ更准确地描述了每个故障的可测性难度，为测试生成过程提供更有效的启发性信息。     

集成电路可测试性设计与验证

文章介绍了集成电路系统芯片(So C)以及IP核相关理论知识,对DFT集成电路可测试性设计进行了概述,给出了几种常用IC产品的测试方法,并对以后DFT可测试性设计的发展进行了论述;提出了一种基于图像处理的多级滤波芯片DFT测试进行分析,给出了DFT Compiler软件实验验证报告,有效地提高了测试覆盖率。     

测试性技术分析与试验验证刍议

测试性质量特性是武器装备试验考核内容之一,攸关武器装备能否快速地检测故障并隔离故障。文中阐述了装备测试技术设计、测试性试验需求和靶场验证方法,着重研究了测试性定性检查、定量检查的基本准则和实施途径。并指出故障特征的分析提取和样本集的有效生成是测试验证的关键,旨在为提升武器装备测试性试验能力提供参考。     

Testability Properties of Divergent Trees

The testability of a class of regular circuits calleddivergent trees is investigated under a functional fault model. Divergent trees include such practical circuits as decoders anddemultiplexers. We prove that uncontrolled divergent trees aretestable with a fixed number of test patterns (C-testable) if andonly if the module function is surjective. Testable controlled treesare also surjective but require sensitizing vectors for errorpropagation. We derive the conditions for testing controlleddivergent trees with a test set whose size is proportional to thenumber of levels p found in the tree (L-testability). By viewing a tree as overlapping arrays of various types, we also deriveconditions for a controlled divergent tree to be C-testable. Typicaldecoders/demultiplexers are shown to only partially satisfy L- andC-testability conditions but a design modification that ensuresL-testability is demonstrated.     

Hopfield神经网络的存贮容量

我们把理论推导与数值模拟相结合得出一个较好的误差函数近似解析式。应用该解析式分析了Ｈｏｐｆｉｅｌｄ神经网络绝对存同容量，得到了一更严格的结果。     

基于TEAMS的测试性建模与分析

随着测试性技术的快速发展，设备的测试性受到越来越多的重视。在研究测试性设计的主要技术和参数基础上，基于 TEAMS 软件建立了典型通信设备的测试性设计模型，进行了测试性仿真与分析，为提高设备的测试性提供定性定量的支持。     

On the convergence properties of the Hopfield model

The main contribution of the present work is showing that the known convergence properties of the Hopfield model can be reduced to a very simple case, for which an elementary proof is provided. The convergence properties of the Hopfield model are dependent on the structure of the interconnections matrix W and the method by which the nodes are updated. Three cases are known: (1) convergence to a stable state when operating in a serial mode with symmetric W; (2) convergence to a cycle of length 2, at most, when operating in a fully parallel mode with symmetric W; and (3) convergence to a cycle of length 4 when operating in a fully parallel mode with antisymmetric W. The three known results are reviewed and it is proven that the fully parallel mode of operation is a special case of the serial model of operation. There are three more cases than can be considered using this characterization: serial mode of operation, antisymmetric W; serial mode of operation, arbitrary W; and fully parallel mode of operation, arbitrary W. By exhibiting exponential lower bounds on the length of the cycles in other cases, it is proven that the three known cases are the only interesting ones     

基于MCU的可测性设计与实现

随着客户需求的复杂化及先进EDA工具的使用,MCU芯片向高复杂性、高集成度、高性能发展,电路规模越来越大,这使得MCU的可测性设计变得越来越困难。介绍了传统测试结构及其局限性,以及优化后的测试结构及其测试策略,实现了CKS32F0XX芯片的测试向量产生及整体测试。     

The capacity of the Hopfield associative memory

Techniques from coding theory are applied to study rigorously the capacity of the Hopfield associative memory. Such a memory storesn-tuple ofpm 1's. The components change depending on a hard-limited version of linear functions of all other components. With symmetric connections between components, a stable state is ultimately reached. By building up the connection matrix as a sum-of-outer products ofmfundamental memories, one hopes to be able to recover a certain one of themmemories by using an initialn-tuple probe vector less than a Hamming distancen/2away from the fundamental memory. Ifmfundamental memories are chosen at random, the maximum asympotic value ofmin order that most of themoriginal memories are exactly recoverable isn/(2 log n). With the added restriction that every one of themfundamental memories be recoverable exactly,mcan be no more thann/(4 log n)asymptotically asnapproaches infinity. Extensions are also considered, in particular to capacity under quantization of the outer-product connection matrix. This quantized memory capacity problem is closely related to the capacity of the quantized Gaussian channel.     

一种可测性调度分配方法

提出一种基于演化算法的可测性调度分配方法.应用演化算法,在调度和分配过程中研究电路的可测性设计.该方法的贡献是:给出了三个可测性准则;设计了可测性目标函数;提出了一种新颖的演化编码和演化操作,提高了搜索速度和解的质量.实验结果验证了该方法的可行性.     

Testability enhancement of domino CMOS logic

A simple circuit technique to enhance the testability of domino CMOS circuits is presented. The fact that domino CMOS gates always have their outputs precharged low enables one to test for output stuck-at-one faults by a simple modification of the domino gate.     

软件可测试性分析方法的研究

软件可测试性在软件质量度量中占有的位置越来越突出，各种度量方法也在不断发展成型。本文对现有的软件可测试性分析方法进行了讨论,并对每一类方法进行了分析比较。