An LSI adaptive array processor

Describes an LSI adaptive array processor (AAP) for two-dimensional data processings. The AAP contains a large number of one-bit processing elements (PEs) arranged in a square array. The large degree of parallelism and control registers in each PE allow for high speed and flexible operations. High transfer capability is also obtained by a simple inter-PE connection network with hierarchical bypasses. The high applicability to various data processings is indicated by a matrix multiplication example, utilizing an algorithm similar to a systolic one. An AAP LSI composed of 8/spl times/8 PEs with powerful functions has been implemented in a 96.0 mm/SUP 2/ chip by using 2 /spl mu/m Si-gate p-well CMOS technology. A high-speed cycle time of 55 ns, low power dissipation of 1.1 W, and high packing density of 1170 transistors/mm/SUP 2/ has been achieved by a skilful manual design. Though the LSI contains as many as 111900 transistors, the design effort has only required one man-year due to cellular array regularity. This LSI is expected to realize a high-performance AAP compactly.     

一种改进的稳健自适应波束形成算法

当快拍数较小时,自适应波束形成算法的性能将会降低,而对角加载算法是提高这类自适应波束形成算法稳健性的简单而有效的方法,但是至今没有一种比较有效的方法来确定对角加载值。本文提出了一种确定加载值的方法,这种方法在加载值和协方差矩阵的估计误差之间建立联系,它能够根据阵列的输出数据动态的调整加载值。计算机仿真证实了该算法的有效性。     

An experimental four-element adaptive array

The experimental pattern behavior of a four-element adaptive array based on a steepest-descent feedback algorithm is described. The array uses four multiturn loop elements on an aircraft fuselage mock-up. Operational patterns have been measured as a function of various parameters: frequency, element placement, desired signal and interference angles of arrival, signal powers, etc. Typical patterns are presented and the performance characteristics of the array are described.     

Monolithic array of optoelectronic broad-band switches

The response of monolithic arrays of GaAs photoconductors to optical intensity modulation signals and their feasibility of operating as crosspoint arrays in integrated broadband switch matrices are investigated. It is found that individual photoconductors can switch signals at frequencies of up to 1.3 GHz with isolation better than 70 dB and switching time less than 10 ns. In a 2/spl times/2 monolithic array, 65-dB switch isolation and 80-dB crosstalk isolation between channels are achieved in the frequency range 0-130 MHz. The responsivity is essentially uniform within this frequency range and has a value of 0.84 A/W at 820 nm. At higher frequencies electromagnetic coupling between output lines limits the performance with the layout used. This monolithic array thus demonstrates compact broadband matrix switching of signals in the frequency range up to 100 MHz using the optoelectronic switching principle.     

An array processor for general purpose digital image compression

A new VLSI processor (DIP chip) for image compression is presented which combines principles of multipipeline and array processing. The device is not specific to any one image compression algorithm and can be regarded as a general purpose processor. The chip has been implemented using a CMOS 1.0-μm process on a 14.4×13.5-mm² die. An internal clock frequency of 40 MHz results in 1.2×10⁹ operations/s on 8-bit data. Solutions to problems associated with the large bandwidth required, for both image data and instruction streams, is the main aim of the paper. The necessary problem of increasing the array clock frequency relative to the input/output clock frequency without the need for a large on-chip instruction cache or fast external clock speeds is also addressed     

An adaptive array for interference rejection

An adaptive array that rejects undesired or interfering signals is presented. The array pattern is controlled by an adaptive feedback system based on a steepest descent minimization of mean-square error. Error is defined as the difference between the array output and a locally generated reference signal. Minimization of mean-square error is closely related to maximization of signal-to-noise ratio (SNR). A two-element adaptive array has been built, and its experimental performance is discussed. Typical patterns for various desired and interfering signals are shown, as well as measured transient response. Finally, some experiments showing the array behavior with modulated signals are described. The results show that such an antenna system is capable of automatically rejecting interfering signals, subject only to certain basic constraints. No a priori information about the angles of arrival of the signals is required, Detailed knowledge of the waveforms of the desired and interfering signals is also not needed, although the spectral characteristics of the desired signal must be known.     

An adaptive algorithm for array processing

A mathematical summary of the joint complex least squares lattice (JCLSL) adaptive algorithm is presented. The algorithm has as inputs two scalar discrete time series (primary. and reference channels). Output consists of the filtered reference channel subtracted from the primary channel. The convergence characteristics of the algorithm are illustrated experimentally for a problem where the reference channel time series consists of dual constant frequency sinusoids which undergo an instantaneous step in frequency. The primary channel time series consists of dual constant frequency sinusoids whose frequencies coincide with those of the reference channel after the step. Lastly, an application of the JCLSL algorithm to the rejection of ocean acoustic boundary reverberation is described.     

CMOS image sensor with mixed-signal processor array

We present a single-chip integration of a CMOS image sensor with an embedded flexible processing array and dedicated analog-to-digital converter. The processor array is designed to perform convolution and transformation algorithms with arbitrary kernels. It has been designed to carry out the multiplication of analog image data with given digital kernel coefficients and to add up the results. The processor array is an analog implementation of a highly parallel architecture which is scalable to any desired sensor resolution while preserving video-rate operation. A prototype implementation has been realized in a 0.6-/spl mu/m CMOS technology. Switched current technique has been applied to obtain compact and robust circuits. The prototype's sensor resolution is 64 /spl times/ 128 pixels. The processor array occupies a small chip area and consumes only a small percentage of the power (250 /spl mu/W) of the whole image sensor.     

下一代32位架构：在性能与功能之间寻求平衡

ARM一直致力于以最低的成本和功耗追求更高的性能。这一努力已经通过连续一代又一代处理器内核的发布得到了实现，每一代新的处理器内核都会引入新的流水线设计、新的指令集以及新的高速缓存结构。这促成了众多创新移动产品的诞生．并且推动了ARM架构向性能、功耗以及成本之间的完美平衡发展。     

An optical processor for radio pulses from an antenna array

A coherent optical method of processing pulsed radio signals received by a planar antenna array is described. The output is the two-dimensional optical image of the brightness distribution of the radio sky. Experimental results for a 4 × 4 array are presented.     

An adaptive antenna array under directional constraint

The concept of the adaptive system working on the principle of minimizing the output power under the constrained response to specified directions is introduced. Theoretical analysis and computer simulation experiments on this directional constraint system are also presented. By comparison with the computer experiment, the differential equation approach is shown to be useful to predict the behavior of the system. The effect of error in setting the constraint direction is investigated, and it is demonstrated that the system is not very sensitive to such error. This margin can be made even greater by adopting the double directional constraints system. This system is also analyzed theoretically and experimented by computer simulation. History of output power components during adaptation is shown, which enables the comprehension of the behavior of the system.     

Cellular array processor CAP and applications

The general-purpose, highly parallel, cellular array processor (CAP) we developed features multiple-instruction stream, multiple-data stream (MIMD) processing and image display. Processor elements can number in several hundreds. The present system uses 256 processors. Each processor element consists of a general-purpose microprocessor, memory, and a special VLSI chip that performs parallel-processing-specific functions such as processor communication and synchronization. The VLSI has two 2M byte/s independent common bus interfaces for data broadcating and six 15M bit/s serial communication ports for local data communication. The chip also can process image data in real time for multiple processors. Use of the communication interfaces enables a variety of processor networks to be configured. One CAP application has been computer graphics, in which ray tracing is used to generate quality images.     

A mixed-signal array processor with early vision applications

Many early vision tasks require only 6 to 8 b of precision. For these applications, a special-purpose analog circuit is often a smaller, faster, and lower power solution than a general-purpose digital processor, but the analog chips lack the programmability of digital image processors. This paper presents a programmable mixed-signal array processor which combines the programmability of a digital processor with the small area and low power of an analog circuit. Each processor cell in the array utilizes a digitally programmable analog arithmetic unit with an accuracy of 1.3%. The analog arithmetic unit utilizes a unique circuit that combines a cyclic switched-capacitor analog-to-digital converter (ADC) and digital-to-analog converter (DAC) to perform addition, subtraction, multiplication, and division, Each processor cell, fabricated in a 0.8-μm triple-metal CMOS process, operates at a speed of 0.8 MIPS, consumes 1.8 mW of power at 5 V, and uses 700 μm by 270 μm of silicon area. An array of these processor cells performed an edge detection algorithm and a subpixel resolution algorithm     

Single-chip image sensors with a digital processor array

The architectures, implementation and applications of two smart sensors, LAPP and PASIC, are described. The basic idea of these two designs is to integrate an image sensor array with a digital processor array in a single chip. The integrated camera-and-processor eliminates the bottleneck of sequential image read-out that characterizes conventional systems. They provide fast, compact and economic solutions for tasks such as industrial inspection, optical character recognition and robot vision.     

A new structure for adaptive broad-band beamforming

The performance characteristics of adaptive array systems with derivative constraints have been investigated by several authors. As a result of the derivative constraints, the array beamwidth in the look direction could be made as broad as desired; however, this increased beamwidth was achieved at the price of reducing array gain. A structure is proposed for an adaptive broadband beamforming system in a manner that can produce a broader beamwidth in the look direction without any derivative constraints imposed on the adaptive processor. Compared to the conventional Frost beamformer with derivative constraints, the computer simulations illustrate the effectiveness of the proposed structure, which broadens the beamwidth in the look direction with only slight sacrifice of array gain     

The tripole antenna: An adaptive array with full polarization flexibility

The performance of an adaptive array using three mutually perpendicular dipoles (a "tripole") is studied. A desired signal and an interference signal, each with arbitrary angle of arrival and polarization, are assumed incident on the array. Uncorrelated thermal noise is also assumed present on each element signal. The output desired signal-to-interference-plus-noise ratio (SINR) is computed as a function of the signal arrival angles and polarizations. It is shown that for most angles of arrival and polarizations, the array has an excellent ability to protect a desired signal from interference. Certain special cases where the performance is not good are discussed in detail.     

An onboard processor and adaptive scanning controller for the Second-Generation Precipitation Radar

Technology for the 14- and 35-GHz Second-Generation Precipitation Radar (PR-2) is currently being developed by the National Aeronautics and Space Administration Jet Propulsion Laboratory to support the development of future spaceborne radar missions. PR-2 will rely on high-performance onboard processing techniques in order to improve the observation capabilities (swath width, spatial resolution, and precision) of a low-Earth orbiting rainfall radar. Using field-programmable gate arrays (FPGAs), we have developed a prototype spaceborne processor and controller module that will support advanced capabilities in the PR-2 such as autotargeting of rain and compression of rainfall science data. In this paper, we describe the new technology components designed for the onboard processor, including an FPGA-based 40 /spl times/ 10/sup 9/ op/s pulse-compression receiver/filter with a range sidelobe performance of -72 dB, and an adaptive scanning controller which yields a six-fold increase in the number of radar looks over areas of precipitation.     

An algorithm for linearly constrained adaptive array processing

A constrained least mean-squares algorithm has been derived which is capable of adjusting an array of sensors in real time to respond to a signal coming from a desired direction while discriminating against noises coming from other directions. Analysis and computer simulations confirm that the algorithm is able to iteratively adapt variable weights on the taps of the sensor array to minimize noise power in the array output. A set of linear equality constraints on the weights maintains a chosen frequency characteristic for the array in the direction of interest. The array problem would be a classical constrained least-mean-squares problem except that the signal and noise statistics are assumed unknown a priori. A geometrical presentation shows that the algorithm is able to maintain the constraints and prevent the accumulation of quantization errors in a digital implementation.     

An adaptive array in a spread-spectrum communication system

This paper describes the integration of an LMS adaptive array into a pseudonoise (PN) coded biphase modulated communication system. The paper explains how these systems my be combined and presents a systems overview of the interaction between the adaptive array and the signaling waveform. An experimental system is described, and typical performance results are presented. The hybrid system requires only very modest spectrum-spreading ratios, such as 5:1, for the adaptive array to null interference. The combined system provides the interference protection of the adaptive array during the code timing acquisition phase as well as after code lockup.     

通用处理器多核流水线自适应同步方法

在通用处理器上进行信号处理是软件无线电发展的方向之一,现有的共享存储并行编程（OpenMP）和直接线程并行法难以对信号处理进行并行加速。针对串行算法的并行化问题,引入多核流水线方法,对传统串行方法和多核流水线的实时性进行了分析对比。针对多核流水线的同步问题,研究了一种分布式的自适应线程同步方法。结合信号处理实例,对串行方法和多核流水线的实时性进行测试,结果表明多核流水线的吞吐率是串行方法的2.1倍,处理能力大大提高。