Near-optimum decoding of product codes: block turbo codes

This paper describes an iterative decoding algorithm for any product code built using linear block codes. It is based on soft-input/soft-output decoders for decoding the component codes so that near-optimum performance is obtained at each iteration. This soft-input/soft-output decoder is a Chase decoder which delivers soft outputs instead of binary decisions. The soft output of the decoder is an estimation of the log-likelihood ratio (LLR) of the binary decisions given by the Chase decoder. The theoretical justifications of this algorithm are developed and the method used for computing the soft output is fully described. The iterative decoding of product codes is also known as the block turbo code (BTC) because the concept is quite similar to turbo codes based on iterative decoding of concatenated recursive convolutional codes. The performance of different Bose-Chaudhuri-Hocquenghem (BCH)-BTCs are given for the Gaussian and the Rayleigh channel. Performance on the Gaussian channel indicates that data transmission at 0.8 dB of Shannon's limit or more than 98% (R/C>0.98) of channel capacity can be achieved with high-code-rate BTC using only four iterations. For the Rayleigh channel, the slope of the bit-error rate (BER) curve is as steep as for the Gaussian channel without using channel state information     

Complexity Reduction in SISO Decoding of Block Codes

SISO decoding for block codes can be carried out based on a trellis representation of the code. However, the complexity entailed by such decoding is most often prohibitive and thus prevents practical implementation. This paper examines a new decoding scheme based on the soft-output Viterbi algorithm (SOVA) applied to a sectionalized trellis for linear block codes. The computational complexities of the new SOVA decoder and of the conventional SOVA decoder, based on a bit-level trellis, are theoretically analyzed and derived for different linear block codes. These results are used to obtain optimum sectionalizations of a trellis for SOVA. For comparisons, the optimum sectionalizations for Maximum A Posteriori (MAP) and Maximum Logarithm MAP (Max-Log-MAP) algorithms, and their corresponding computational complexities are included. The results confirm that the new SOVA decoder is the most computationally efficient SISO decoder, in comparisons to MAP and Max-Log-MAP algorithms. The simulation results of the bit error rate (BER) performance, assuming binary phase -- shift keying (BPSK) and additive white Gaussian noise (AWGN) channel, demonstrate that the performance of the new decoding scheme is not degraded. The BER performance of iterative SOVA decoding of serially concatenated block codes shows no difference in the quality of the soft outputs of the new decoding scheme and of the conventional SOVA.     

Bit error probability calculations for convolutional codes withshort constraint lengths on very noisy channels

A technique for estimating convolutional code performance on very noisy channels is considered. Specifically, the performance of short constraint length codes operating near the channel cutoff rate is estimated. Decoding convolutional codes with a sliding window decoder (SWD) are considered. This decoder is an optimal (maximum likelihood) symbol decoder as the window size grows toward infinity, while the Viterbi decoder is the maximum-likelihood sequence estimator. The difference in the decoded BERs (bit error rates) between the two decoders is very small and approaches zero asymptotically as the channel BER decreases. Therefore, an estimate on the decoded BER for the SWD can also be used as an estimate of the decoded BER for Viterbi decoding     

基于高斯消元的BATS码的改进译码算法

BATS码是一种包括外码和内码的纠删码,外码是喷泉码的矩阵形式。内码是网络编码结构,采用随机线性网络编码算法。BATS码的常用译码算法为BP译码算法,但对有限长BATS码,BP译码算法的性能有大幅度的衰减。因此,在计算资源充足的情况下,可以在BP译码器后采用高斯消元算法对BATS码进行译码。采用高斯消元算法时,矩阵满秩则输入数据包可译,反之则不可译。因此,利用当矩阵不满秩时也有部分包可译的特点,识别并将这部分可译包译出,从而提高高斯消元译码器的译码性能。     

中长帧非规则LDPC码译码器的FPGA实现

LDPC(低密度奇偶校验码)是一种优秀的线性分组码,是目前距香农限最近的一类纠错编码。与Turbo码相比,LDPC码能得到更高的译码速度和更好的误码率性能,从而被认为是下一代通信系统和磁盘存储系统中备选的纠错编码。简要介绍了适于硬件实现的LDPC码译码算法,并基于软判决译码规则,使用Verilog硬件描述语言,在X ilinx V irtex2 6000 FPGA上实现了码率为1/2、帧长504bit的非规则LDPC码译码器。     

Layered Approx-Regular LDPC: Code Construction and Encoder/Decoder Design

Layered approximately regular (LAR) low-density parity-check (LDPC) codes are proposed, with which one single pair of encoder and decoder support various code lengths and code rates. The parity check matrices of LAR-LDPC codes have a "layer-block-cell" structure with some additional constraints. An encoder architecture is then designed for LAR-LDPC codes, by making two improvements to the Richardson-Urbanke approach: the forward substitution operation is entirely removed and the dense-matrix-vector multiplication is handled using feedback shift-registers. A partially parallel decoder architecture is also designed for LAR-LDPC codes, where a layered modified min-sum decoding algorithm is used to trade off among complexity, speed, and performance. More importantly, the interconnection network, which is inevitable for partially parallel decoders, has much lower hardware complexity compared with that for general LDPC codes. Both the encoder and decoder architectures are highly flexible in code length and code rate.     

Closest coset decoding of |u|u+v| codes

The general concept of closest coset decoding (CCD) is presented, and a soft-decoding technique for block codes that is based on partitioning a code into a subcode and its cosets is described. The computational complexity of the CCD algorithm is significantly less than that required if a maximum-likelihood detector (MLD) is used. A set-partitioning procedure and details of the CCD algorithm for soft decoding of |u|u+v| codes are presented. Upper bounds on the bit-error-rate (BER) performance of the proposed algorithm are combined, and numerical results and computer simulation tests for the BER performance of second-order Reed-Muller codes of length 16 and 32 are presented. The algorithm is a suboptimum decoding scheme and, in the range of signal-to-noise-power-density ratios of interest, its BER performance is only a few tenths of a dB inferior to the performance of the MLD for the codes examined     

基于分布式奇偶校验码的低复杂度极化码SCLF译码算法

针对极化码串行抵消列表比特翻转(Successive Cancellation List Bit-Flip, SCLF)译码算法复杂度较高的问题,提出一种基于分布式奇偶校验码的低复杂度极化码SCLF译码(SCLF Decoding Algorithm for Low-Complexity Polar Codes Based on Distributed Parity Check Codes, DPC-SCLF)算法。与仅采用循环冗余校验(Cyclic Redundancy Check, CRC)码校验的SCLF译码算法不同,该算法首先利用极化信道偏序关系构造关键集,然后采用分布式奇偶校验(Parity Check, PC)码与CRC码结合的方式对错误比特进行检验、识别和翻转,提高了翻转精度,减少了重译码次数。此外,在译码时利用路径剪枝操作,提高了正确路径的竞争力,改善了误码性能,且利用提前终止译码进程操作,减少了译码比特数。仿真结果表明,与D-Post-SCLF译码算法和RCS-SCLF译码算法相比,所提出算法具有更低的译码复杂度且在中高信噪比下具有更好的误码性能。     

Turbo编码GMSK信号准相干解调时的迭代信道估计和译码研究

针对准相干解调Turbo编码GMSK信号,提出了一种简便的迭代信道估计算法。该方法基于Turbo码的迭代译码原理,将信道估计和译码联合考虑,利用译码器输出反馈进行迭代信道估计,从而提高了估计精度。仿真结果表明,该方法能显著地改善系统误码率性能。     

Decoding spherical codes for the Gaussian channel

A decoding algorithm for permutation codes that is equivalent to maximum-likelihood decoding, but less complex than the correlation decoder, is presented. A general construction for iteratively maximum-likelihood decodable (IMLD) codes is proved and used to construct IMLD codes for every dimension n. D. Slepian (1965) defined permutation modulation codes and presented an efficient algorithm for their decoding. Slepian's decoding scheme is one of the principal components of the permutation code decoding algorithm presented     

New Syndrome Check Error Estimation and Its Concatenated Coding

A low-complexity and high performance SCEE (Syndrome Check Error Estimation) decoding method for convolutional codes and its concatenated SCEE/RS (Reed–Solomon) coding scheme are proposed. First, we describe the operation of the decoding steps in the proposed algorithm. Then deterministic values on the decoding operation are derived when some combination of predecoder-reencoder is used. Computer simulation results show that the computational complexity of the proposed SCEE decoder is significantly reduced compared to that of conventional Viterbi decoder without degradation of the P_e performance. Also, simulation results of BER performance of the concatenated SCEE/Hard Decision Viterbi (HD-Viterbi) and SCEE/RS (Reed–Solomon) codes are presented.     

Modified min-sum SCAN decoding algorithm for polar codes

The state-of-the-art soft-output decoder of polar codes is the soft cancellation (SCAN) decoding algorithm, which performs well at the cost of plentiful computations. Based on the SCAN decoding algorithm, a modified method with revised iterative formula is proposed, marked modified min-sum SCAN (MMS-SCAN). The proposed algorithm simplifies the update formula of nodes and reduces the complexity of iterative decoding process by the piecewise approximation function. Meanwhile, the bit error rate (BER) of the proposed method can approach the performance of original SCAN decoding method without performance loss. The simulation reveals that the MMS-SCAN decoding algorithm can achieve the effect that the BER curve almost coincides with the original SCAN decoding curve.     

Using linear programming to Decode Binary linear codes

A new method is given for performing approximate maximum-likelihood (ML) decoding of an arbitrary binary linear code based on observations received from any discrete memoryless symmetric channel. The decoding algorithm is based on a linear programming (LP) relaxation that is defined by a factor graph or parity-check representation of the code. The resulting "LP decoder" generalizes our previous work on turbo-like codes. A precise combinatorial characterization of when the LP decoder succeeds is provided, based on pseudocodewords associated with the factor graph. Our definition of a pseudocodeword unifies other such notions known for iterative algorithms, including "stopping sets," "irreducible closed walks," "trellis cycles," "deviation sets," and "graph covers." The fractional distance d/sub frac/ of a code is introduced, which is a lower bound on the classical distance. It is shown that the efficient LP decoder will correct up to /spl lceil/d/sub frac//2/spl rceil/-1 errors and that there are codes with d/sub frac/=/spl Omega/(n/sup 1-/spl epsi//). An efficient algorithm to compute the fractional distance is presented. Experimental evidence shows a similar performance on low-density parity-check (LDPC) codes between LP decoding and the min-sum and sum-product algorithms. Methods for tightening the LP relaxation to improve performance are also provided.     

Reconfigurable Hardware Architectures for Sequential and Hybrid Decoding

A novel reconfigurable sequential decoder architecture based on the Fano algorithm is presented in which the constraint length, the threshold spacing, and the time-out threshold are all run time reconfigurable. To maximize decoding performance, a maximum possible backward depth (of a whole frame) is performed. This is achieved by using shift registers combined with memory to store the information of an entire visited path. A field-programmable gate array) prototype of the decoder is built and actual hardware decoding performances in terms of decoding speeds, bit error rates (BERs), and buffer overflow rates, are obtained and comparisons made. To overcome the decoding delay that is inherent in sequential decoders, a hybrid scheme, including simple block codes and cyclic redundancy check is proposed to limit the number of backward search operations that the sequential decoder has to execute. As a result, a significant reduction in decoding delay and buffer overflow rate is achieved while maintaining comparative decoding performance in terms of BER     

SVD iterative detection of turbo-coded multiantenna unitary differential modulation

A new suboptimal demodulator based on a singular value decomposition for estimation of unitary matrices is introduced. Noncoherent communication over the Rayleigh flat fading channel with multiple transmit and receive antennas, where no channel state information is available at the receiver is investigated. Codes achieving bit-error rate (BER) lower than 10/sup -4/ at bit energy over the noise spectral density ratio (E/sub b//N/sub 0/) of 1.6-1.9 dB from code restricted capacity limit were found. At higher data rates, computation of code restricted capacity is impractical. Therefore, the mutual information upper bound of the capacity attaining isotropically random unitary transmit matrices was used. The codes achieve BER lower than 10/sup -4/ at E/sub b//N/sub 0/ of 3.2-6 dB from this bound, with coding rates of 1.125-5.06 bits per channel use, and different modulation decoding complexities. The codes comprise a serial concatenation of turbo code and a unitary matrix differential modulation code. The receiver employs the high-performance coupled iterative decoding of the turbo code and the modulation code. Information theoretic arguments are harnessed to form guidelines for code design and to evaluate performance of the iterative decoder.     

Multilevel block codes for Rayleigh-fading channels

New multilevel block codes for Rayleigh-fading channels are presented. At high signal-to-noise ratios (SNRs), the proposed block codes can achieve better bit error performance over TCM codes, optimum for fading channels, with comparable decoder complexity and bandwidth efficiency. The code construction is based on variant length binary component block codes. As component codes for the 8-PSK multilevel block construction, the authors propose two modified forms of Reed-Muller codes giving a good trade-off between the decoder complexity and the effective code rates. Code design criteria are derived from the error performance analysis. Multistage decoding shows very slight degradation of bit error performance relative to the maximum likelihood algorithm     

High-throughput LDPC decoders

A high-throughput memory-efficient decoder architecture for low-density parity-check (LDPC) codes is proposed based on a novel turbo decoding algorithm. The architecture benefits from various optimizations performed at three levels of abstraction in system design-namely LDPC code design, decoding algorithm, and decoder architecture. First, the interconnect complexity problem of current decoder implementations is mitigated by designing architecture-aware LDPC codes having embedded structural regularity features that result in a regular and scalable message-transport network with reduced control overhead. Second, the memory overhead problem in current day decoders is reduced by more than 75% by employing a new turbo decoding algorithm for LDPC codes that removes the multiple checkto-bit message update bottleneck of the current algorithm. A new merged-schedule merge-passing algorithm is also proposed that reduces the memory overhead of the current algorithm for low to moderate-throughput decoders. Moreover, a parallel soft-input-soft-output (SISO) message update mechanism is proposed that implements the recursions of the Balh-Cocke-Jelinek-Raviv (BCJR) algorithm in terms of simple "max-quartet" operations that do not require lookup-tables and incur negligible loss in performance compared to the ideal case. Finally, an efficient programmable architecture coupled with a scalable and dynamic transport network for storing and routing messages is proposed, and a full-decoder architecture is presented. Simulations demonstrate that the proposed architecture attains a throughput of 1.92 Gb/s for a frame length of 2304 bits, and achieves savings of 89.13% and 69.83% in power consumption and silicon area over state-of-the-art, with a reduction of 60.5% in interconnect length.     

基于SSCANL译码器的联合迭代检测译码算法

为了提升基于极化码的稀疏码多址接入（sparse code multiple access,SCMA）系统接收机性能,提出了基于简化软消除列表（simplify soft cancellation list,SSCANL）译码器的循环冗余校验（cyclic redundancy check,CRC）辅助联合迭代检测译码接收机方案。该方案中极化码译码器使用SSCANL译码算法,采用译码节点删除技术对软消除列表（soft cancellation list,SCANL）算法所需要的L次软消除译码（soft cancellation, SCAN）进行简化,通过近似删除冻结位节点,简化节点间软信息更新计算过程,从而降低译码算法的计算复杂度。仿真结果表明,SSCANL算法可获得与SCANL算法一致的性能,其计算复杂度与SCANL算法相比有所降低,码率越低,算法复杂度降低效果越好;且基于SSCANL译码器的CRC 辅助联合迭代检测译码接收机方案相较基于SCAN译码器的联合迭代检测译码（joint iterative detection and decoding based on SCAN decoder, JIDD-SCAN）方案、基于SCAN译码器的CRC辅助联合迭代检测译码（CRC aided joint iterative detection and decoding based on SCAN decoder,C-JIDD-SCAN）方案,在误码率为10^-4时,性能分别提升了约0.65 dB、0.59 dB。     

基于VHDL的TPC译码器设计

Turbo乘积码是一种性能卓越的前向纠错码,具有译码复杂度低,且在低信噪比时可以获得近似最优的性能。介绍基于Chase算法的Turbo乘积码软入软出（SISO）迭代译码算法,提出基于VHDL硬件描述语言的TPC译码器设计方案,并在FPGA芯片上进行了仿真和验证。仿真结果证明该译码器有很大的实用性和灵活性。     

Soft-Output BEAST Decoding With Application to Product Codes

A Bidirectional Efficient Algorithm for Searching code Trees (BEAST) is proposed for efficient soft-output decoding of block codes and concatenated block codes. BEAST operates on trees corresponding to the minimal trellis of a block code and finds a list of the most probable codewords. The complexity of the BEAST search is significantly lower than the complexity of trellis-based algorithms, such as the Viterbi algorithm and its list generalizations. The outputs of BEAST, a list of best codewords and their metrics, are used to obtain approximate a posteriori probabilities (APPs) of the transmitted symbols, yielding a soft-input soft-output (SISO) symbol decoder referred to as the BEAST-APP decoder. This decoder is employed as a component decoder in iterative schemes for decoding of product and incomplete product codes. Its performance and convergence behavior are investigated using extrinsic information transfer (EXIT) charts and compared to existing decoding schemes. It is shown that the BEAST-APP decoder achieves performances close to the Bahl–Cocke–Jelinek–Raviv (BCJR) decoder with a substantially lower computational complexity.