三态门总线传输电路的Multisim仿真方案

基于探索仿真三态门总线传输电路的目的,采用Multisim10仿真软件对总线连接的三态门分时轮流工作时的波形进行了仿真实验测试,给出了仿真实验方案,即用Multisim仿真软件构成环形计数器产生各个三态门的控制信号、用脉冲信号源产生各个三态门不同输入数据信号,用Multisim仿真软件中的逻辑分析仪多踪同步显示各个三态门的控制信号、数据输入信号及总线输出信号波形,结论是仿真实验可直观形象地描述三态门总线传输电路的工作特性,所述方法的创新点是解决了三态门的工作波形无法用电子实验仪器进行分析验证的问题。     

三态门逻辑功能的Multisim仿真方案

介绍了用Multisim仿真软件分析三态门工作过程的方法,目的是探索三态门工作波形的仿真实验技术,即用Multisim仿真软件中的字组产生器产生三态门的控制信号及输入信号,用Multisim中示波器、逻辑分析仪多踪同步显示三态门的各个输入信号及输出信号波形。并介绍了不同工作条件下仿真时Multisim中字组产生器的设置方法、字组产生器的字组内容如何反映三态门输入端的不同输入情况。结论是可直观形象地描述三态门的工作过程。所述方法的创新点是解决了三态门的工作波形无法用电子实验仪器进行分析验证的问题。     

集成计数器74LS161的Multisim仿真

介绍了用Multisim仿真软件分析集成计数器74LS161工作过程的方法,即用Multisim仿真软件中的字组产生器产生计数器的时钟脉冲、控制信号等多路信号,字组产生器的字组内容反映计数器的工作方式及逻辑功能,用Multisim中逻辑分析仪多踪同步显示计数器的各种输入信号及状态输出信号波形,可直观描述计数器的工作过程。所述方法的创新点是,解决了计数器的工作波形无法用电子实验仪器进行分析验证的问题。     

移位寄存器的Multisim仿真

介绍用Multisim仿真软件分析移位寄存器逻辑功能的方法,验证了4-D触发器构成的移位寄存器的逻辑功能。用Multisim仿真软件中的字组产生器产生的信号作为移位寄存器的时钟脉冲和输入数据,字组内容反映移位寄存器的输入信号和控制信号,用Multisim中的逻辑分析仪多踪同步显示各输入信号、控制信号和输出信号波形,直观地描述移位寄存器的工作过程。所述方法创新地解决了移位寄存器工作过程无法用实验仪器验证的问题。     

Multisim在触发器工作波形分析中的应用

介绍用Multisim仿真软件进行触发器工作波形仿真分析的方法,目的是探索触发器工作波形的仿真实验技术,即用Multisim仿真软件中的字组产生器产生触发器的时钟脉冲、数据输入、异步控制等多路信号,用Multisim中逻辑分析仪多踪同步显示触发器的各种输入及状态输出波形。并介绍了几种典型触发方式,不同逻辑功能触发器工作波形仿真分析时Multisim中字组产生器的设置方法。该软件可直观形象地描述触发器的逻辑功能和状态变化特点。所述方法的创新点是解决了触发器工作波形无法用电子实验仪器进行分析验证的问题。     

用Multisim仿真分析数据选择器的工作过程

介绍用Multisim仿真软件分析数据选择器工作过程的方法,即用Multisim仿真软件中的字组产生器产生数据选择器的各个数据输入信号,字组产生器的字组内容反映数据选择器不同数据输入端的输入情况,用Multisim中逻辑分析仪多踪同步显示数据选择器的各个数据输入信号及输出信号波形,可直观描述数据选择器的数据选择的工作过程。所述方法的创新点是解决了数据选择器的工作波形无法用电子实验仪器进行分析验证的问题。     

二进制译码器逻辑功能的Multisim仿真方案

介绍了用Multisim仿真软件分析二进制译码器工作过程的方法,即用Multisim仿真软件中字组产生器产生二进制译码器的使能控制信号和地址输入信号。字组产生器的字组内容反映二进制译码器输入端的不同输入情况,用Multisim中逻辑分析仪多踪同步显示二进制译码器的各个输入信号及输出信号波形,可直观描述二进制译码器的译码工作过程。该方法解决了二进制译码器的工作波形无法用电子实验仪器进行分析验证的问题。     

门电路延迟时间的Multisim仿真测试方案

介绍了用Multisim仿真软件测试门电路延迟时间的方法，提出了三种测试方案，即将奇数个门首尾相接构成环形振荡电路，用虚拟示波器测试所产生振荡信号的周期，计算门的传输延迟时阔；奇数个门首尾相接构成环形振荡电路，用虚拟示波器测试其中一个门的输入信号、输出信号波形及延迟时间；在一个门的输入端加入矩形脉冲信号，测试一个门的输入信号、输出信号波形及延迟时间。所述方法的创新点是，解决了受示波器上限频率限制实际硬件测试效果不明显的问题，并给出Multisim软件将门的初始输出状态设置为0时，使测试电路不能正常工作的解决方法。     

基于Multisim的顺序脉冲发生器的虚拟仿真

介绍了用中规模计数器74LS163和译码器74LS138构建8路顺序脉冲发生器的Multisim虚拟仿真方案,用仿真软件中的虚拟仪器同时观察和测试时钟脉冲信号与8路脉冲顺序发生器的输出信号。所述方法的实际意义是解决了多路顺序脉冲发生器的输出波形无法用实际电子实验仪器进行分析验证的问题。     

电容滤波电路工作波形的Multisim仿真分析

基于探索电容滤波电路工作波形仿真实验技术的目的,采用Multisim10仿真软件对电容滤波电路的工作波形进行了仿真实验测试,给出了Multisim仿真实验方案,仿真分析了滤波电容选取不同数值时电路工作波形、电路性能的变化情况。结论是仿真实验可直观形象地描述电容滤波电路的工作特性,有利于系统地研究电路的构成及电路元件参数的选择。     

An adjustable work function technology using Mo gate for CMOSdevices

Nitrogen implantation of Mo gate was used to fabricate MOS capacitors and CMOS transistors. Initial studies demonstrate that the work function of Mo is sensitive to nitrogen implantation energy. Mo with (110) orientation exhibits a high work function, making it suitable for bulk p-MOSFET gate electrodes. Nitrogen implantation can be used to lower the Mo work function, making it suitable for n-MOSFET gate electrodes. A gate work function reduction of 0.42 eV was achieved for the n-FETs on CMOS wafers. With further optimization, this single metal gate technology may potentially replace conventional poly-Si gate technology for CMOS and can also be used for multiple-V_T technologies     

SYNTHESIS OF MULTIVALUED CMOS CIRCUITS WITH MANY VARIABLES BASED ON TRANSMISSION FUNCTION THEORY

Based on transmission function theory,the synthesis technique for multivaluedCMOS circuits is discussed.By comparing the CMOS circuits based on transmission functiontheory with the T gate,it is shown that their action principles are identical.Based on it,thesynthesis method for multivalued CMOS circuits with many variables by using function decom-position is proposed.     

CMOS Dual-Work-Function Engineering by Using Implanted Ni-FUSI

For the first time, a simple CMOS fully silicided (FUSI) process achieving n/pMOS band-edge work function was demonstrated, which is fully compatible with conventional CMOS process. Dual-work-function CMOS FUSI, with a wide range of 800 mV, was achieved by implantation of Yb into the poly of the nMOS gate (4.1-eV work function) and Ga into the poly of the pMOS gate (4.9-eV work function), respectively. The placement of the tuning elements at the metal/dielectric interface was engineered with the thermal budget, as well as the implant dose and species.     

基于传输函数理论的多值多变量CMOS电路综合

本文讨论了基于传输函数理论的多值CMOS电路综合技术。通过对基于传输函数理论的CMOS电路与T门的分析比较,指出了它们的工作原理的一致性。在此基础上提出了用函数分解综合多值多变量CMOS电路的方法。     

An integratable dual metal gate CMOS process using an ultrathin aluminum nitride buffer layer

We propose and demonstrate a novel approach for dual metal gate CMOS process integration through the use of a very thin aluminum nitride (AlN/sub x/) buffer layer between metal and gate oxide. This buffer layer prevents the gate oxide from being exposed to a metal etching process which potentially causes oxide thinning and damage. Subsequent annealing consumes the very thin AlN/sub x/ layer and converts it into a new metal alloy film by reacting with gate metals, resulting in no increase in EOT due to this buffer layer. The work function of the original gate metal is also modified as a result of its reaction with AlN/sub x/, making this approach extremely attractive for engineering the work function for dual metal gate CMOS applications.     

A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO/sub 2/ by using HfN replacement gate

A replacement gate process employing a HfN dummy gate and sub-1-nm equivalent oxide thickness (EOT) HfO/sub 2/ gate dielectric is demonstrated. The excellent thermal stability of the HfN-HfO/sub 2/ gate stack enables its use in high temperature CMOS processes. The replacement of HfN with other metal gate materials with work functions adequate for n- and pMOS is facilitated by a high etch selectivity of HfN with respect to HfO/sub 2/, without any degradation to the EOT, gate leakage, or time-dependent dielectric breakdown characteristics of HfO/sub 2/. By replacing the HfN dummy gate with Ta and Ni in nMOS and pMOS devices, respectively, a work function difference of /spl sim/0.8 eV between nMOS and pMOS gate electrodes is achieved. This process could be applicable to sub-50-nm CMOS technology employing ultrathin HfO/sub 2/ gate dielectric.     

模-数-差信号发生器的设计与实现

模-数-差信号发生器主要由集成压控振荡器ICL8038构成的函数信号发生器电路、模.数.差变换与输出电路以及电源电路组成.设计是在函数信号发生器和双路直流电源基础上,采取比例放大、串联分压、二极管检波等变换与组合方法,实现由正弦波、三角波、方波、直流信号组成的模拟信号,TTL和CMOS信号组成的数字信号,以及具有AC和DC信号的差分信号.模-数-差信号发生器集多种常用信号于一体,使用简便,可适应多种场合的电子测量.     

Latched domino CMOS logic

A new gate configuration, the latched domino (Ldomino) CMOS gate, is presented. It can be used to alleviate the inversion problem inherent in domino CMOS, while improving speed and reducing layout area. Ldomino logic can serve as an efficient interface stage between blocks of static and domino or differential-cascode voltage-switch logic. The function of interfacing single-ended logic signals to differential domino-compatible logic signals is combined with the capability of efficient implementation of complex logic functions, thereby improving the logic flexibility of domino logic. A simple 4-bit ALU is used as an illustrative example of the application of Ldomino logic.     

锗预非晶化注入对镍硅(NiSi)金属栅功函数的影响研究

随着超大规模集成电路技术的发展,CMOS器件的制备过程需要同时引入金属栅和超浅结等新的先进工艺技术,因此各种新工艺的兼容性研究具有重要意义.本文研究了超浅结工艺中使用的锗预非晶化对镍硅(NiSi)金属栅功函数的影响.对具有不同剂量Ge注入的NiSi金属栅MOS电容样品的研究表明,锗预非晶化采用的Ge注入对NiSi金属栅的功函数影响很小(小于0.03eV),而且Ge注入也不会导致氧化层中固定电荷以及氧化层和硅衬底之间界面态的增加.这些结果表明,在自对准的先进CMOS工艺中,NiSi金属栅工艺和锗预非晶化超浅结工艺可以互相兼容.     

Investigation of NiSi and TiSi as CMOS gate materials

NiSi is a promising new candidate for CMOS gate metal material because its workfunction can be adjusted by the implantation of dopants into the silicon before silicidation. In this report, NiSi and TiSi are studied, and the work functions of each are found to be adjustable over a wider range than previously published. This range covers the work function values required to achieve correct threshold voltages (V/sub t/) for both deep-scaled bulk CMOS and fully depleted, silicon-on-insulator MOSFETs. The influence of these silicides on the gate oxide and interface quality is also examined thoroughly via measurements of capacitance, minority carrier mobility, and gate-leakage current. While no degradation of the interface is observed with NiSi gates, TiSi gates generate interface traps and significantly degrade transistor device performance. With all the merits of a metal gate and no apparent degradation of interface quality, NiSi can be integrated with minor modification into a standard CMOS process and is a promising gate metal material for future CMOS technology generations.