一种理解和设计传输门逻辑和静态CMOS门逻辑电路的方法

在充分了解NMOS管和PMOS管电学特性的基础上,我们总结了一个理解和设计传输门逻辑和静态CMOS门逻辑电路的方法,这种方法能够简单易懂的去理解基于MOS器件的传输门和静态CMOS门逻辑电路。运用这种方法,我们也可以方便的去设计传输门和静态CMOS门逻辑电路。我们的方法将静态逻辑门电路和传输门逻辑电路有机的统一起来,便于理解学生的理解和记忆。     

高温CMOS数字集成电路直流传输特性的分析

分析了高温CMOS倒相器和门电路的直流传输特性,建立了相应的解析模型。根据分析,高温MOSFET阈值电压和载流子迁移率的降低,以及MOSFET漏端pn结泄漏电流的增加引起了CMOS倒相器和门电路直流传输特性劣化。在MOSFET漏端pn结泄漏电流的影响下,高温CMOS倒相器和门电路的输出高电平下降,低电平上升,导致了电路的功能失效。给出的理论模型和实验结果一致。     

超导逻辑门RCJL的传输特性

ＲＣＪＬ（电阻耦合约瑟夫孙逻辑）是电流注入控制型的典型超导逻辑门电路。本文用四阶龙格－库塔法分析了ＲＣＪＬ的传输特性，并分别对门的边沿激励、阻尼作用及门间隔离电阻对传输性能的影响作了详细的分析讨论。     

适合数模兼容传输的Ku波段微波传输系统

讨论了一种既能传送模拟信号也能传输数字信号的Ku波段微波传输系统,此系统成本低、使用灵活方便,适用于实况转播,两地间数模信号的传输。     

三态门总线传输电路的Multisim仿真方案

基于探索仿真三态门总线传输电路的目的,采用Multisim10仿真软件对总线连接的三态门分时轮流工作时的波形进行了仿真实验测试,给出了仿真实验方案,即用Multisim仿真软件构成环形计数器产生各个三态门的控制信号、用脉冲信号源产生各个三态门不同输入数据信号,用Multisim仿真软件中的逻辑分析仪多踪同步显示各个三态门的控制信号、数据输入信号及总线输出信号波形,结论是仿真实验可直观形象地描述三态门总线传输电路的工作特性,所述方法的创新点是解决了三态门的工作波形无法用电子实验仪器进行分析验证的问题。     

用传输门VCO和动态PFD设计低功耗CMOS琐相环

锁相环（PLL）是VLSI系统的重要单元电路之一,为了实现高速低功耗的CMOS锁相环,用传输门VCO和动态反相器PFD电路设计CMOS锁相环。传输门结构VCO具有高速、低电压和低功耗的特性,而动态反相器PFD具有功耗低和面积小的特点。SPICE模拟表明,当电源电压为2．5V时,基于0．6μmCMOS工艺设计的CMOS锁相环电路,工作频率高达1000MHz,而功耗低于50mW。     

利用单片机实现的模拟信号和数字信号单线混合传输

本文以单片机89C2051为核心，采用DAC TLC5618、模拟开关MAX319设计了能实现模拟信号和数字信号单线混合传输的系统。     

2微米CMOS门阵单元库

门阵单元库是ASIC设计的基础工作。本文介绍了2微米CMOS门阵单元库的建库过程，同时对建库的基本方法作了简要的说明。     

The transient analysis of latch-up in CMOS transmission gate induced by laser

An analytical model of transient latch-up in CMOS transmission gate induced by laser is established. The time-dependent current characteristics of the parasitic silicon controlled rectifier (SCR) under different injected photocurrent are illustrated. The model analyzes the trigger conditions for latch-up and describes the dynamic process varying with time. The photocurrent threshold causing latch-up under different pulse widths and repetition frequencies is obtained, which agrees well with the experimental results reported in the literature.     

三态门逻辑功能的Multisim仿真方案

介绍了用Multisim仿真软件分析三态门工作过程的方法,目的是探索三态门工作波形的仿真实验技术,即用Multisim仿真软件中的字组产生器产生三态门的控制信号及输入信号,用Multisim中示波器、逻辑分析仪多踪同步显示三态门的各个输入信号及输出信号波形。并介绍了不同工作条件下仿真时Multisim中字组产生器的设置方法、字组产生器的字组内容如何反映三态门输入端的不同输入情况。结论是可直观形象地描述三态门的工作过程。所述方法的创新点是解决了三态门的工作波形无法用电子实验仪器进行分析验证的问题。     

非对称式多谐振荡器的Multisim仿真

针对Multisim中器件从0输出状态开始仿真,仿真非对称式多谐振荡器工作波形不能形成振荡输出,提出了在仿真电路的输入端接入转换开关,仿真时先将转换开关接地使电路脱离系统设置的初始输出状态,再通过转换开关构成非对称式多谐振荡器,进行正常工作状态的仿真.特点是直观形象地描述了多谐振荡器的工作工程、解决了多谐振荡器工作波形无法用电子实验仪器进行分析验证的问题.     

基于Multisim电子仿真软件的电路设计与研究

应用仿真系统对电子技术方面进行测量和验证,可以改革传统设计模式,提高实验效率,启发和拓宽开发者的思路。在此通过介绍Multisim软件的功能、特点,并结合电子电路实例叙述其设计、仿真与分析的具体运用。通过分析证明其有利于创新课程教学内容与标准,有利于充分激发和培养学生自主学习能力及学习的乐趣,同时也说明Multisim是一种功能强大的电子电路仿真软件。     

低功耗CMOS低噪声放大器的分析与设计

基于TSMC 0.18μm CMOS工艺,设计了一种低功耗约束下的CMOS低噪声放大器。与传统的共源共栅结构相比,该电路在共源晶体管的栅源间并联一个电容,以优化噪声;并引入一个电感,与级间寄生电容谐振,以提高增益;通过减小晶体管的尺寸,实现了低功耗。模拟结果表明,在2.45 GHz工作频率下,增益大于14 dB,噪声系数小于1 dB,直流功耗小于2 mW。     

Design of Two‐Stage Class AB CMOS Buffers: A Systematic Approach

A systematic approach for the design of two‐stage class AB CMOS unity‐gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity‐gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 µm CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 µW).     

浅谈Multisim仿真软件在模拟电子技术课程教学中的应用

模拟电子技术是电子类专业的一门极其重要的专业基础课,是一门电子技术方面入门性质的技术基础课程,具有很强的工程性和实践性。为了使学生易于掌握相关知识,在课程教学中,适当引入Multisim电路仿真软件进行辅助教学,将抽象的理论较为形象地显示出来,便于大家理解,在一定程度上可以激发学生的学习兴趣,提高学生的实践动手能力。     

Clock Feedthrough in CMOS Analog Transmission Gate Switches

An analysis of clock feedthrough in CMOS analog transmission gate (TG) switches is presented in this paper. The mechanism for clock feedthrough and a related model of a transmission gate switch are established in the current-voltage domain. A region map is developed for the TG switch during the period when both devices are turned off. The region map is further divided into zones. From these region and zone maps, the sign and relative magnitude of the clock feedthrough noise can be efficiently estimated for different signal levels. Placing the input voltage near half of the power supply voltage is a useful technique for minimizing clock feedthrough noise. A model of clock feedthrough noise as compared with SPICE simulations exhibits less than 3% error. This research was supported in part by the Semiconductor Research Corporation under Contract No. 99-TJ-687, the DARPA/ITO under AFRL Contract F29601-00-K-0182, grants from the New York State Office of Science, Technology & Academic Research to the Center for Advanced Technology—Electronic Imaging Systems and to the Microelectronics Design Center, and by grants from Xerox Corporation, IBM Corporation, Intel Corporation, Lucent Technologies Corporation, and Eastman Kodak Company. Weize Xu received the B.S. degree from Nanjing University of Posts and Telecommunications, China in 1982, and the M.S. degrees from the University of Rhode Island in 1993, both in electrical engineering. Since 1997, he has been a senor research engineer and analog IC design specialist at Eastman Kodak Company. His research interests include high speed analog IC designs, pipelined A/D converter, low power switched capacitor circuit analysis and design, CMOS image sensor design, and analysis of noise in mixed signal ICs. He currently is a Ph.D candidate at the University of Rochester. Eby G. Friedman (S'78-M'79-SM'90-F'00) received the B.S. degree from Lafayette College in 1979, and the M.S. and Ph.D. degrees from the University of California, Irvine, in 1981 and 1989, respectively, all in electrical engineering. From 1979 to 1991, he was with Hughes Aircraft Company, rising to the position of manager of the Signal Processing Design and Test Department, responsible for the design and test of high performance digital and analog IC's. He has been with the Department of Electrical and Computer Engineering at the University of Rochester since 1991, where he is a Distinguished Professor, the Director of the High Performance VLSI/IC Design and Analysis Laboratory, and the Director of the Center for Electronic Imaging Systems. He also enjoyed a sabbatical at the Technion—Israel Institute of Technology during the 2000/2001 academic year. His current research and teaching interests are in high performance synchronous digital and mixed-signal microelectronic design and analysis with application to high speed portable processors and low power wireless communications. He is the author of more than 250 papers and book chapters, several patents, and the author or editor of seven books in the fields of high speed and low power CMOS design techniques, high speed interconnect, and the theory and application of synchronous clock distribution networks. Dr. Friedman is the Regional Editor of the Journal of Circuits, Systems, and Computers, a Member of the editorial boards of the Proceedings of the IEEE, Analog Integrated Circuits and Signal Processing microelectronics Journal, and Journal of VLSI Signal Processing, a Member of the Circuits and Systems (CAS) Society Board of Governors, and a Member of the technical program committee of a number of conferences. He previously was the past Editor-in-Chief of the IEEE Transactions on VLSI Systems, a Member of the editorial board of the IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Chair of the IEEE Transactions on VLSI Systems steering committee, CAS liaison to the Solid-State Circuits Society, Chair of the VLSI Systems and Applications CAS Technical Committee, Chair of the Electron Devices Chapter of the IEEE Rochester Section, Program or Technical chair of several IEEE conferences, Guest Editor of several special issues in a variety of journals, and a recipient of the Howard Hughes Masters and Doctoral Fellowships, an IBM University Research Award, an Outstanding IEEE Chapter Chairman Award, and a University of Rochester College of Engineering Teaching Excellence Award. Dr. Friedman is a Senior Fulbright Fellow and an IEEE Fellow.     

基于Multisim的计数器设计仿真

计数器是常用的时序逻辑电路器件,文中介绍了以四位同步二进制集成计数器74LS161和异步二-五-十模值计数器74LS290为主要芯片,设计实现了任意模值计数器电路,并用Multisim软件进行了仿真。仿真验证了设计的正确性和可靠性,设计与仿真结果表明,中规模集成计数器可有效实现任意模值计数功能,并且虚拟仿真为电子电路的设计与开发提高了效率。