A 20--40-GHz Push--Push Dielectric Resonator Oscillator

A novel coupling method is employed in the design of a push-push broad-band dielectric resonator oscillator for K- and Ka-band operation. The oscillators realized with this technique exhibit excellent spectral purity, power output, and suppression of spurious outputs.     

A 1.6-GHz Current-Controlled Oscillator with Integrated Inductor

A 1.6 GHz fully monolithic silicon bipolar LC current-controlledoscillator (CCO) circuit implemented in a 0.8 µmBiCMOS technology and characterized for use in wireless applicationsis presented. The integrated resonator circuit uses high speed(18 GHz) bipolar transistors, a 14 nH rectangular spiral inductorfabricated by using a standard 2-level metallization, and a widebandpn-varactor structure. Additionally, to save chip area, the integratedcapacitors were fabricated below the planar inductor structure.In order to aid the IC design, a simple equivalent circuit modelfor the integrated inductor on silicon was developed and tested.The measured quiescent power dissipation of the integrated CCOcircuit is 1.9 mW to 5.5 mW from a supply of 2–;3 V, anda typical phase noise varies from –82 to –86 dBc/Hz at 100 kHz offset.     

A 5.8-GHz Quadrature Cross-Coupled Oscillator

This paper describes the implementation of a quadrature cross-coupled relaxation oscillator to be used in an OFDM RF front-end transceiver. A prototype of the oscillator was realized in a SiGe BiCMOS technology, and an oscillation frequency of 5.8 GHz was obtained which is 1/6 of the maximum f _T of the bipolar transistors. The circuit performance is evaluated by simulation and by experiment.     

A Dual-Diode 73-GHz Gunn Oscillator

It is shown that two resonant cap structures can be mounted in a common waveguide to combine power from two Gunn diodes. Approximately 80-mW power was obtained at 73 GHz.     

一种38.4~43.4 GHz CMOS压控振荡器

设计了一种基于65 nm CMOS工艺的交叉耦合全差分40 GHz压控振荡器(VCO)。为了减小仿真结果与测试结果的差距,对电感及其连接其他元件而延长的金属线在电磁场仿真软件里重新进行了仿真。设计中应用了厚栅容抗管来增大电压的调谐范围,从而实现更高的频率覆盖范围。流片后的测试结果表明,VCO的振荡频率覆盖38.4~43.4 GHz,调谐范围达到12.2%,符合基于无线局域网IEEE 802.11ad标准设计的两级下变频60 GHz无线收发机对本振频率的要求。当振荡频率为39 GHz时,应用该VCO的锁相环锁定在41.76 GHz时测得1 MHz偏移频率处的相位噪声为－90.9 dBc/Hz。芯片采用1 V电源电压供电,功耗为5.7~8.6 mW,核心芯片面积为(0.197×0.436) mm²。     

A 26-GHz High-Performance MIC Transmitter/Receiver for Digital Radio Subscriber Systems

A high-performance 26-GHz microwave integrated circuit (MIC) transmitter/receiver using frequency-shift-keying (FSK) modulation has been developed. All RF components are fabricated using MIC technology and integrated into a single compact module. Newly developed MIC components include an FSK modulator, a time division multiple access (TDMA) switch, and a single-balanced mixer. The FSK modulator is composed of an IMPATT diode, a varactor diode, and a dielectric resonator. A high-frequency stability of 50 ppm is obtained in the tempera-ture range of -10-45°C. The configuration and performance of the TDMA switch with a high ON/OFF ratio and a low insertion loss are described, A transmitting power of 21 dBm and a receiving noise figure of 8.7 dB are obtained. The bit error rate is measured to evaluate the overall transmitter/receiver performance. The required carrier-to-noise ratio (CNR) has been considerably improved by adopting FSK modulation and by using the MIC transmitter/receiver described in this paper.     

A Fully Embedded LTCC Multilayer BPF for 3-D Integration of 40-GHz Radio

This paper demonstrates a low loss fully embedded multilayer bandpass filter (BPF) using low-temperature cofired ceramic (LTCC) technology for 3-D integration of 40-GHz multimedia wireless system (MWS) radio. The LTCC filter implemented in a stripline configuration occupies an area of only 5.5 times 2.3 times 0.6 mm including shielding structure and coplanar waveguide (CPW) transitions. The measured insertion loss was as small as 1.9 dB at a center frequency of 41.8 GHz, and the return loss was 12.2 dB including the loss associated with two CPW-to-stripline transitions. This six-layer BPF showed 3-dB bandwidth of 10.5% from 39.6 to 44.0 GHz at a center frequency of 41.8 GHz and suppressed the local oscillator (LO) signal to 20.2 dB at a local oscillator frequency of 38.8 GHz, making it suitable for the 40 GHz MWS applications.     

一个2.4 GHz CMOS LC压控振荡器的设计

采用单层多晶6层金属(1P6M)的0.18μm标准CMOS工艺,设计了一个2.4 GHz电感电容压控振荡器(LC tank VCO)。该压控振荡器的电路结构选用互补交叉耦合型。测试结果表明,在VCO的输入参考频率为1 MHz,工作电压1.8 V时,工作电流为5.5 mA,频率调谐范围2.1~2.8 GHz。     

A 40-GHz Flip-Flop-Based Frequency Divider

This brief presents the design and implementation of a 40-GHz flip-flop-based frequency divider which incorporates a novel latch topology with two distinct tail current sources and an enabled cross-coupled pair during the tracking mode. The proposed topology will speed up the latch operation and increase the driving capability. It is capable of performing frequency division at 40 GHz without shunt or series peaking inductors. The circuit was fabricated in a 0.18-mum SiGe BiCMOS process, where only CMOS transistors were used. It draws an average current of 5 mA from a 1.8-V supply voltage     

A 94-GHz Diode-Based Single Six-Port Reflectometer

This paper describes design considerations and gives measurement results for a single six-port reflectometer constructed from WR-10 waveguide with silicon Schottky diode detectors. Tradeoffs between various types of power detectors are discussed along with criteria for six-port junction design. The merits of two calibration procedures are compared. Measurements at 94 GHz indicate good agreement between expected and experimental values of q-points and of a sliding mismatch with nominal 0.1 reflection coefficient.     

A 60-GHz 38-pJ/bit 3.5-Gb/s 90-nm CMOS OOK Digital Radio

A 60-GHz fully integrated bits-in bits-out on–off keying (OOK) digital radio has been designed in a standard 90-nm CMOS process technology. The transmitter provides 2 dBm of output power at a 3.5-Gb/s data rate while consuming 156 mW of dc power, including the on-chip 60-GHz frequency synthesizer. A pulse-shaping filter has been integrated to support high data rates while maintaining spectral efficiency. The receiver performs direct-conversion noncoherent demodulation at data rates up to 3.5 Gb/s while consuming 108 mW of dc power, for a total average transceiver energy consumption of 38 pJ/bit in time division duplex operation. To the best of the authors' knowledge, this is the lowest energy per bit reported to date in the 60-GHz band for fully integrated single-chip CMOS OOK radios.      

一种单电源高集成度蔡氏振荡器

二端非线性电阻的实现是研究蔡氏电路中混沌现象的一个重要环节,传统的非线性电阻大多采用正负电源供电的运放和电阻、电容等分立器件来搭建。在分析非线性电阻工作原理的基础上,提出采用单电源供电的集成电路制造工艺实现负阻器件的思想。设计的非线性负阻器件主要由轨到轨运算放大器、基准电压/电流产生等模块组成,并在0.18 μm标准CMOS工艺下设计实现。仿真结果表明,在1.8 V单电源工作模式下,蔡氏电路两个关键节点的李萨如波形表现为双螺旋吸引子,证明该振荡器电路有效,整个电路的功耗约为2.45 mA。     

A 30-GHz Self-Injection-Locked Oscillator Having a Long Optical Delay Line for Phase-Noise Reduction

We demonstrate a millimeter-wave self-injection-locked (SIL) oscillator having a long optical delay line as a feedback route. In the SIL oscillator, a part of output signal is self-injected into the oscillator after passing through a long optical delay line, resulting in locked oscillation and phase-noise reduction. By controlling the self-injection power, we achieve 30-GHz oscillation with a sidemode suppression ratio larger than 50 dB and about 18-dB phase-noise reduction at 10-kHz frequency offset.     

Demonstration of a 311-GHz Fundamental Oscillator Using InP HBT Technology

In this paper, a sub-millimeter-wave HBT oscillator is reported. The oscillator uses a single-emitter 0.3 m15 m InP HBT device with maximum frequency of oscillation greater than 500 GHz. The passive components of the oscillator are realized in a two metal process with benzocyclobutene used as the primary transmission line dielectric. The oscillator is implemented in a common base topology due to its inherent instability. The design includes an on-chip resonator, output matching circuitry, and injection locking port. A free-running frequency of 311.6 GHz has been measured by down-converting the signal. Additionally, injection locking has been successfully demonstrated with up to 17.8 dB of injection-locking gain. This is the first fundamental HBT oscillator operating above 300 GHz.     

Radio Local Distribution System for High-Speed Digital Communications

The radio local distribution system (RLDS) has been proposed to transmit various business information signals. The proposed RLDS uses a 26 GHz band and time division multiple access (TDMA). The main features of the RLDS are the use of radio equipment containing the microwave integrated circuit (MIC) and the adoption of the demand-assigned TDMA (DA/TDMA) technique. The MIC is more suitable than conventional waveguide circuits for mass production because its components are miniaturized. The DA/TDMA system, operating in a fully variable demand-assignment mode, uses simple control systems with a low bit rate. As a result, the RLDS can serve a local distribution system of high-speed digital communications both expeditiously and economically.     

A 10-GHz Optoelectronic Oscillator at 850 nm Using a Single-Mode VCSEL and a Photonic Crystal Fiber

We demonstrate an optoelectronic oscillator using a gain-switched single-mode vertical cavity surface-emitting laser and a single-mode photonic crystal fiber. A 10-GHz optical pulse train at 850 nm with a timing jitter of 1.2 ps was successfully generated.     

40-GHz mode-locked fiber-ring laser using a Mach-Zehnder interferometer with integrated SOAs

A 40-GHz mode-locked fiber-ring laser based on an optically controlled modulator is presented and analyzed in detail. The modulator is a monolithic InGaAsP-InP Mach-Zehnder interferometer with integrated semiconductor optical amplifiers, which allows optical pulse generation synchronized to an external optical clock pulse stream. The laser generates nearly transform-limited Gaussian pulses of 2.5-ps width and up to 9-mW mean output power with less than 130 fs of timing jitter, and it is wavelength tunable over more than 30 nm. The relationship between key laser parameters and the output pulse characteristics is analyzed experimentally and numerically. An improved cavity design permits the generation of shorter pulses of 1.0-ps width.     

A 40-GHz static frequency divider with quadrature outputs in 80-nm CMOS

The implemented static frequency divider provides quadrature (Q) clock outputs and divides frequencies up to 44GHz. The core divider circuit consists of two current-mode logic (CML) latches and consumes 3.2mW from a 1.1-V supply. The divided outputs result in a peak-to-peak and rms jitter of 6.3 and 0.8ps, respectively, and the maximum phase mismatch between the in-phase (I) and Q-outputs amounts to 1ps at an input frequency of 40GHz. The high division frequency is achieved by employing resistive loads, inductive peaking, and optimizing the circuit layout for reduced parasitic capacitances in the latches. The core divider consumes a chip area of 30/spl mu/m/spl times/40/spl mu/m only.