Characterization of n-type β-SiC as a piezoresistor

SiC is currently being investigated for device applications involving high temperatures. The properties of n-type β-SiC relevant to piezoresistive devices, namely the gauge factor (GF) and temperature coefficient of resistivity (TCR), are characterized for several doping levels. The maximum gauge factor observed was -31.8 for unintentionally doped (10¹⁶-10¹⁷/cm³) material. This gauge factor decreases with temperature to approximately half its room-temperature value at 450°C. Unintentionally doped SiC has a roughly constant TCR of 0.72%/°C over the range 25-800°C and exhibits full impurity ionization at room temperature. Degenerately doped gauges (N_d=10²⁰/cm³) exhibited a lower gauge factor (-12.7), with a more constant temperature behavior and a lower TCR (0.04%/°C). The mechanisms of the piezoresistive effect and TCR in n-SiC are discussed, as well as their application towards sensors     

P-type 4H and 6H-SiC high-voltage Schottky barrier diodes

High-voltage Schottky barrier diodes have been successfully fabricated for the first time on p-type 4H- and 6H-SiC using Ti as the barrier metal. Good rectification was confirmed at temperatures as high as 250°C. The barrier heights were estimated to be 1.8-2.0 eV for 6H-SiC and 1.1-1.5 eV for 4H-SiC at room temperature using both I-V and C-V measurements. The specific on resistance (R_on,sp) for 4H- and 6H-SiC were found to be 25 mΩ cm^-2 and 70 mΩ cm^-2 at room temperature. A monotonic decrease in resistance occurs with increasing temperature for both polytypes due to increased ionization of dopants. An analytical model is presented to explain the decrease of R_on,sp with temperature for both 4H and 6H-SiC which fits the experimental data. Critical electric field strength for breakdown was extracted for the first time in both p-type 4H and 6H-SiC using the breakdown voltage and was found to be 2.9×10⁶ V/cm and 3.3×10⁶ V/cm, respectively. The breakdown voltage remained fairly constant with temperature for 4H-SiC while it was found to decrease with temperature for 6H-SiC     

Molecular beam epitaxial GaAs/AlGaAs heterojunction bipolartransistors on (311)A GaAs substrates with all-silicon doping

The authors have investigated the characteristics and reproducibility of Si-doped p-type (311)A GaAs layers for application to heterojunction bipolar transistors (HBTs) grown by molecular beam epitaxy (MBE). The authors obtained p=2.2×10¹⁹ cm^-3 in a layer grown at 670°C. They have used all-Si doping to grow n-p-n transistors. These devices exhibit excellent DC characteristics with β=230 in a device with base doping of p=4×10¹⁸ cm^-3     

Au/Pt/Ti/Ni ohmic contacts to p-ZnTe

Ohmic contacts of Au/Pd/Ti/Ni to p-ZnTe show a minimum specific contact resistance of 10^-6 Ωcm² for a p-type doping level of 3×10¹⁹ cm^-3 and at an annealing temperature of 300°C. The Ni and Ti layers are very effective in improving the electrical properties of these contact     

4H-SiC MOSFETs utilizing the H2 surface cleaningtechnique

The H₂ cleaning technique was examined as the precleaning of the gate oxidation for 4H-SiC MOSFETs. The device had a channel width and length of 150 and 100 μm, fabricated on the p-type epitaxial layer of 3×10¹⁶ cm^-3. The gate oxidation was performed after the conventional RCA cleaning, and H₂ annealing at 1000°C. The obtained channel mobility depends on the pre-cleaning process strongly, and was achieved 20 cm²/N s in the H₂ annealed sample. The effective interface-state density was also measured by the MOS capacitors fabricated on the same chips, resulting 1.8×10¹² cm^-2 from the photo-induced C-V method     

Electrical characterization of annealed Ti/TiN/Pt contacts onN-type 6H-SiC epilayer

We report results of the electrical characteristics of in vacuo deposited Ti/TiN/Pt contact metallization on n-type 6H-SiC epilayer as function of impurity concentration in the range of 3.3×10¹⁷ cm^-3 to 1.9×10¹⁹ cm^-3. The as-deposited contacts are rectifying, except for the highly doped sample. Only the lesser doped remains rectifying after samples are annealed at 1000°C between 0.5 and 1 min in argon. Bulk contact resistance ranging from factors of 10^-5 to 10^-4 Ω-cm² and Schottky barrier height in the range of 0.54-0.84 eV are obtained. Adhesion problems associated with metal deposition on pre-processed titanium is not observed, leading to excellent mechanical stability. Auger electron spectroscopy (AES) reveals the out diffusion of Ti-Si and agglomeration of Ti-C species at the epilayer surface. The contact resistance remains appreciably stable after treatment in air at 650°C for 65 h. The drop in SBH and the resulting stable contact resistance is proposed to be associated with the thermal activation of TiC diffusion barrier layer on the 6H-SiC epilayer during annealing     

Electrical properties of Si p+-n junctions for sub-0.25μm CMOS fabricated by Ga FIB implantation

p⁺-n junction diodes for sub-0.25-μm CMOS circuits were fabricated using focused ion beam (FIB) Ga implantation into n-Si (100) substrates with background doping of N_b=(5-10)×10 ¹⁵ and N_b⁺=(1-10)×10¹⁷ cm^-3. Implant energy was varied from 2 to 50 keV at doses ranging from 1×10¹³ to 1×10¹⁵ cm^-2 with different scan speeds. Rapid thermal annealing (RTA) was performed at either 600 °C or 700°C for 30 s. Diodes fabricated on N_b⁺ with 10-keV Ga⁺ exhibited a leakage current (^I_R) 100× smaller than those fabricated with 50-keV Ga⁺. Tunneling was determined to be the major current transport mechanism for the diodes fabricated on N_b⁺ substrates. An optimal condition for I_R on N_b⁺ substrates was obtained at 15 keV/1×10¹⁵ cm^-2. Diodes annealed at 600°C were found to have an I_R 1000× smaller than those annealed at 700°C. I-V characteristics of diodes fabricated on N_b substrates with low-energy Ga⁺ showed no implant energy dependence. I-V characteristics were also measured as a function of temperature from 25 to 200°C. For diodes implanted with 15-keV Ga ⁺, the cross-over temperatures between I_diff and I_g-r occurred at 106°C for N_b ⁺ and at 91°C for N_b substrates     

High channel mobility in normally-off 4H-SiC buried channel MOSFETs

We have fabricated buried channel (BC) MOSFETs with a thermally grown gate oxide in 4H-SiC. The gate oxide was prepared by dry oxidation with wet reoxidation. The BC region was formed by nitrogen ion implantation at room temperature followed by annealing at 1500°C. The optimum doping depth of the BC region has been investigated. For a nitrogen concentration of 1×10¹⁷ cm^-3, the optimum depth was found to be 0.2 μm. Under this condition, a channel mobility of 140 cm²/Vs was achieved with a threshold voltage of 0.3 V. This channel mobility is the highest reported so far for a normally-off 4H-SiC MOSFET with a thermally grown gate oxide     

Doping level and type of GaInP saturable absorbing layers forrealizing pulsating 650-nm-band AlGaInP laser diodes

On AlGaInP laser diodes, the doping level and type of GaInP saturable absorbing (SA) layers suitable for self sustained pulsation are clarified. Optical properties of n- and p-type GaInP quantum wells (QWs) have been evaluated by means of time-resolved photoluminescence (TRPL) spectroscopy. As the doping level becomes higher, the recombination lifetime becomes shorter, and it can be reduced to 1.1 ns at our highest doping level (1=2×10¹⁸ cm^-3). For highly doped n-type QW, a PL peak energy shift as large as 26 meV is observed by high-density excitation. Highly doped p-type SA layer is suitable for self-sustained pulsating laser diodes, because it offers short recombination lifetime and no Burstein shift under highly excited condition     

Electrical characterisation of Si-dopedGaAs0.5Sb0.5 on InP grown by molecular beamepitaxy

Between the growth temperatures of 490-520°C Si-doped GaAs_0.5Sb_0.5 changes from 1×10¹⁷ cm^-3 n-type to 2×10¹⁷ cm^-3 p-type. The scattering mechanisms of the n and p-type epilayers are investigated. The reproducibility and potential applications of the observed conduction type change are demonstrated by the fabrication of a pn diode     

Avalanche phenomena in 4H-SiC p-n diodes fabricated by aluminum orboron implantation

Characteristics of p-n junction fabricated by aluminum-ion (Al⁺) or boron-ion (B⁺) implantation and high-dose Al⁺-implantation into 4H-SiC (0001) have been investigated. By the combination of high-dose (4×10¹⁵ cm^-2) Al⁺ implantation at 500°C and subsequent annealing at 1700°C, a minimum sheet resistance of 3.6 kΩ/□ (p-type) has been obtained. Three types of diodes with planar structure were fabricated by employing Al+ or B+ implantation. B ⁺-implanted diodes have shown higher breakdown voltages than Al⁺-implanted diodes. A SiC p-n diode fabricated by deep B+ implantation has exhibited a high breakdown voltage of 2900 V with a low on-resistance of 8.0 mΩcm² at room temperature. The diodes fabricated in this study showed positive temperature coefficients of breakdown voltage, meaning avalanche breakdown. The avalanche breakdown is discussed with observation of luminescence     

Deep-level dominated current-voltage characteristics of buriedimplanted oxide silicon-on-insulator

Current-voltage characteristics of Au contacts formed on buried implanted oxide silicon-on-insulator (SOI) structures are discussed, which indicate that the dominant transport mechanism is space-charge-limited current (SCLC) conduction in the presence of deep-level states. The deep-level parameters, determined using a simple analysis, appear to be sensitive to anneal conditions used and subsequent processing. Silicon implanted with 1.7×10¹⁸ cm^-2 oxygen ions at 150 keV following a 1200°C anneal for 3 h shows deep level 0.37 eV below the conduction band edge with a concentration of unoccupied traps of ~ 2×10¹⁵ cm^-3 . In contrast, arsenic ion implantation, in the 1200°C annealed material with a dose of 1.5×10¹² cm^-2 at 60 keV and activated by rapid thermal annealing (RTA), introduces a deep level 0.25 eV below the conduction band edge with an unoccupied trap concentration of ~6×10¹⁷ cm^-2     

Current confinement and leakage currents in planarburied-ridge-structure laser diodes on n-substrate

An electrical device model for the planar buried-ridge-structure laser on n-type substrate is discussed. It takes into account the finite p-type contact resistivity, the two-dimensional current spreading, and the electron leakage current by drift and diffusion. Using this model, the influence of the relevant device parameters on the leakage current in InGaAsP/InP devices emitting at 1.3 μm is investigated. It is shown that leakage currents are negligible at room temperature if the contact stripe width does not exceed the sum of the active region width and the p-type confinement layer thickness, but they increase markedly with broader contact stripes and with contact resistivities above 10^-5 Ω-cm². The most important parameter influencing the leakage currents is the doping level of the P-InP confinement layer. With a p-type doping level of 1×10¹⁸ cm^-3, a p-type contact resistivity below 10^-5 Ω-cm² and a contact stripe width of 6 μm, the model calculations predict a maximum operation temperature exceeding 100°C. This agrees fairly well with experimental data proving that the rather simple planar buried-ridge-structure laser performs as well as more sophisticated devices incorporating current-blocking layers     

Study of interface state density and effective oxide charge inpost-metallization annealed SiO2-SiC structures

A systematic study of post-metallization annealing (PMA) effect on the quality of thermal SiO₂ on p-type 6H- and 4H-SiC has been carried out. A simultaneous quasi-static hi-lo frequency capacitance-voltage method has been employed to measure the total effective oxide charge (N_eff) and interface state density (D _it). To ensure accurate results, D_it was measured at 350°C which, depending on the hole capture cross sections, should enable the measurement of interface states located in the band gap as deep as 1.3-1.5 eV from the valence band edge. The dependence of N_eff and D_it on annealing temperature and ambient as well as the effect of thermal and sputtered gate metal on the oxide quality are reported. It is shown that N_eff values close to the detection limit due to the uncertainty in SiC electron affinities and D_it values below 1×10¹¹ cm^-2/eV deep in the band gap can be reproducibly obtained for both p-type 6H- and 4H-SiC     

3100 V, asymmetrical, gate turn-off (GTO) thyristors in 4H-SiC

A 2-mm×2-mm, 4H-SiC, asymmetrical npnp gate turn-off (GTO) thyristor with a blocking voltage of 3100 V and a forward current of 12 A is reported. This is the highest reported power handling capability of 37 kW for a single device in SiC. The 5-epilayer structure utilized a blocking layer that was 50 μm thick, p-type, doped at about 7-9×10¹⁴ cm^-3. The devices were terminated with a single zone junction termination extension (JTE) region formed by ion-implantation of nitrogen at 650°C. The device was able to reliably turn-on and turn-off 20 A (500 A/cm²) of anode current with a turn-on gain (I_K/I_{G, on}) of 20 and a turn-off gain (I_K/I_{G, off}) of 3.3     

Improved inversion channel mobility for 4H-SiC MOSFETs followinghigh temperature anneals in nitric oxide

Results presented in this letter demonstrate that the effective channel mobility of lateral, inversion-mode 4H-SiC MOSFETs is increased significantly after passivation of SiC/SiO₂ interface states near the conduction band edge by high temperature anneals in nitric oxide. Hi-lo capacitance-voltage (C-V) and ac conductance measurements indicate that, at 0.1 eV below the conduction band edge, the interface trap density decreases from approximately 2×10¹³ to 2×10¹² eV^-1 cm^-2 following anneals in nitric oxide at 1175°C for 2 h. The effective channel mobility for MOSFETs fabricated with either wet or dry oxides increases by an order of magnitude to approximately 30-35 cm²/V-s following the passivation anneals     

Reliability of AlInAs/GaInAs heterojunction bipolar transistors

The reliability of high-performance AlInAs/GaInAs heterojunction bipolar transistors (HBTs) grown by molecular beam epitaxy (MBE) is discussed. Devices with a base Be doping level of 5×10¹⁹ cm^-3 and a base thickness of approximately 50 nm displayed no sign of Be diffusion under applied bias. Excellent stability in DC current gain, device turn-on voltage, and base-emitter junction characteristics was observed. Accelerated life-test experiments were performed under an applied constant collector current density of 7×10⁴ A/cm² at ambient temperatures of 193, 208, and 328°C. Junction temperature and device thermal resistance were determined experimentally. Degradation of the base-collector junction was used as failure criterion to project a mean time to failure in excess of 10⁷ h at 125°C junction temperature with an associated activation energy of 1.92 eV     

Rapid isothermal annealing of high- and low-energy ion-implantedInP and In0.53Ga0.47As

Rapid isothermal annealing (RIA) was performed on 0.5-16-MeV Si ⁺, 1-MeV Be⁺, and 150-keV Ge⁺ implanted InP:Fe and 380-keV Fe⁺ implanted InGaAs. Annealings were performed in the temperature range 800-925°C using an InP proximity wafer in addition to the Si₃N₄ dielectric cap. Dopant activations close to 100% were obtained for 3×10¹⁴ cm^-2 Si⁺ and 2×10¹⁴ cm^-2 Be⁺ implants in InP:Fe. For the elevated temperature (200°C) 1×10¹⁴ cm^-2 Ge⁺ implant, a maximum of 50% activation was obtained. No redistribution of dopant was observed for Si and Ge implants due to annealing. However, redistribution of dopant was seen for Be and Fe implants due to annealing. Phosphorous coimplantation has helped to eliminate the Be in-diffusion problem in InP, but did not help to reduce Fe in-diffusion and redistribution in InGaAs. Using an RIA cycle with low temperature and short duration is the only solution to minimize Fe redistribution in InGaAs     

Drift hole mobility in strained and unstrained doped Si1-xGex alloys

Results of the drift hole mobility in strained and unstrained SiGe alloys are reported for Ge fractions varying from 0 to 30% and doping levels of 10¹⁵-10¹⁹ cm^-3. The mobilities are calculated taking into account acoustic, optical, alloy, and ionized-impurity scattering. The mobilities are then compared with experimental results for a boron doping concentration of 2×10¹⁹ cm^-3. Good agreement between experimental and theoretical values is obtained. The results show an increase in the mobility relative to that of silicon     

High temperature formed SiGe p-MOSFETs with good devicecharacteristics

We have used a simple process to fabricate Si_0.3Ge_0.7/Si p-MOSFETs. The Si_0.3Ge _0.7 is formed using deposited Ge followed by 950°C rapid thermal annealing and solid phase epitaxy that is process compatible with existing VLSI. A hole mobility of 250 cm²/Vs is obtained from the Si_0.3Ge_0.7 p-MOSFET that is ~two times higher than Si control devices and results in a consequent substantially higher current drive. The 228 Å Si_0.3Ge_0.7 thermal oxide grown at 1000°C has a high breakdown field of 15 MV/cm, low interface trap density (D_it) of 1.5×10¹¹ eV^-1 cm^-2, and low oxide charge of 7.2×10¹⁰ cm^-2. The source-drain junction leakage after implantation and 950°C RTA is also comparable with the Si counterpart