A full adder structure without cross-wiring in quantum-dot cellular automata with energy dissipation analysis

Quantum-dot cellular automata (QCA) is the appearance of new technology and can be a suitable alternative to semiconductor transistor technology. In this paper, the new structure of the two-input XOR gate is presented, which is the modified version of the three-input XOR gate. This structure can be used to design various useful QCA circuits. By utilizing this gate, we design and implement a new full adder structure with 90-degree cells. This structure is designed in a single layer without cross-wiring. The operation of the proposed structure has been verified by QCADesigner version 2.0.3 and energy dissipation investigated by QCAPro tool. We also compared the effectiveness of our structure with the two previous structures.     

Novel low power reversible binary incrementer design using quantum-dot cellular automata

This paper demonstrates the design of n-bit novel low power reversible binary incrementer in Quantum-Dot Cellular Automata (QCA). The comparison of quantum cost in quantum gate based approach and in QCA based design agreed the cost efficient implementation in QCA. The power dissipation by proposed circuit is estimated, which shows that the circuit dissipates very low heat energy suitable for reversible computing. All the circuits are evaluated in terms of logic gates, circuit density and latency that confirm the faster operating speed at nano scale. The reliability of the circuit under thermal randomness is explored which describes the efficiency of the circuit.     

Novel efficient full adder and full subtractor designs in quantum cellular automata

In this study, two new full adder/full subtractor designs based on quantum-dot cellular automata technology have been proposed. By means of the presented equation for SUM and SUBTRACT operations, the new high-speed, low power, and cost efficient designs have been achieved. Even if the three-level design has a lower cell count, occupies less area, and operates at a higher speed, the one-layer design is far more feasible. Analysis of the temperature and energy consumption of the proposed design indicates that the proposed approaches are superior to those of previous works.

     

A novel design of 8-bit adder/subtractor by quantum-dot cellular automata

Application of quantum-dot is a promising technology for implementing digital systems at nano-scale. QCA supports the new devices with nanotechnology architecture. This technique works based on electron interactions inside quantum-dots leading to emergence of quantum features and decreasing the problem of future integrated circuits in terms of size. In this paper, we will successfully design, implement and simulate a new full adder based on QCA with the minimum delay, area and complexities. Also, new XOR gates will be presented which are used in 8-bit controllable inverter in QCA. Furthermore, a new 8-bit full adder is designed based on the majority gate in the QCA, with the minimum number of cells and area which combines both designs to implement an 8-bit adder/subtractor in the QCA. This 8-bit adder/subtractor circuit has the minimum delay and complexity. Being potentially pipeline, the QCA technology calculates the maximum operating speed.     

Design and simulation of nano-arbiters using quantum-dot cellular automata

Arbiters are the essential components of the Network-On-Chip (NOC) systems and are used to resolve the contention problem where multiple requests must be handled for shared resources. On the other hand, with the ever-increasing downsizing trend in the fabrication technology, Quantum-dot Cellular Automata (QCA) with its nano scales and very low power consumption is a promising candidate for implementing future NOCs. In the current work, we design and simulate nano-arbiters using QCA with the following contributions: i) The 2-bit Basic Round Robin Arbiter (RRA) and the 2-bit Ping Pong Arbiter (PPA) are designed and simulated; ii) A solution for an erroneous condition found in the original circuit of RRA is reported and fixed; iii) We use Cartesian Genetic Programming (CGP) approach to simplify the RRA and PPA designs; iv) In order to leverage our QCA designs, we apply a more realistic clock distribution (2-DW clocking) and report the results. At the end, a one-to-one comparison of the two arbiters designed with QCA will be presented using such benchmarks as area, latency, etc. Our results show that in the 2-bit input mode, the PPA arbiter has the best overall performance.     

An iterative structure for synthesizing symmetric functions using quantum-dot cellular automata

In recent years, majority-logic received significant attention as a synthesis approach for large Boolean functions. This logic is easily implemented in Quantum-dot cellular automata (QCA) technology which is emerging as an alternative to CMOS technology. In fact, majority logic gate serves as the basic logic unit in the digital design of QCA circuits. This paper introduces a synthesis technique for implementing totally symmetric Boolean functions using majority logic. First, a simple regular module is designed to synthesize unate symmetric functions. The structure uses 3-input majority gates. General symmetric Boolean functions are then realized following a unate decomposition method. We study the synthesis of some well known benchmark symmetric functions using the proposed method. Comparison with existing synthesis approaches confirms the efficacy of our method.     

Computation in reversible cellular automata

A reversible cellular automaton (RCA) is a subclass of a CA such that its global function is injective. It is considered as an abstract spatiotemporal model of a reversible physical system. In spite of the strong constraint of reversibility, an RCA has a high ability of information processing. In this survey, we overview the past studies on RCAs, and discuss how computing is performed in them. We can see even very simple RCAs have computation-universality.     

Towards modular binary to gray converter design using LTEx module of quantum-dot cellular automata

A modular approach to realize the ultra-fast quantum-dot cellular automata (QCA) generic binary to gray converter is presented in this paper. The novel designs here validated fully exploit the intrinsic repetitive capabilities of the Layered T Exclusive OR (LTEx) module in the QCA domain. An efficient logic formulation of QCA design metrics like O-Cost and delay is proposed for the n-bit QCA binary to gray converter designs. The QCA implementation of n-bit LTEx binary to gray converter is compared with the conventional converters. An attempt has been made to enhance the speed of modular binary to gray converter designs. The proposed 4, 8, 16, 32, 64-bit binary to gray converters need 4.35, 15.88, 15.96, 15.7, 16.68% less O-cost and 11.57, 2.61, 9.32, 12.64, 29.25% less effective area, respectively. Thus the proposed layouts offer the smaller feature size, reduced circuit complexity exploiting the modular based design approach. The simulation results have been carried out in the renowned computer aided design tool, namely QCADesigner 2.0.3 with gallium arsenide heterostructure based parameter environment.

     

Design of dual-edge triggered flip-flops based on quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technology has been widely considered as an alternative to complementary metal-oxide-semiconductor (CMOS) due to QCA’s inherent merits.Many interesting QCA-based logic circuits with smaller feature size,higher operating frequency,and lower power consumption than CMOS have been presented.However,QCA is limited in its sequential circuit design with high performance flip-flops.Based on a brief introduction of QCA and dual-edge triggered (DET) flip-flop,we propose two original QCA-based D and JK DET flip-flops,offering the same data throughput of corresponding single-edge triggered (SET) flip-flops at half the clock pulse frequency.The logic functionality of the two proposed flip-flops is verified with the QCADesigner tool.All the proposed QCA-based DET flip-flops show higher performance than their SET counterparts in terms of data throughput.Furthermore,compared with a previous DET D flip-flop,the number of cells,covered area,and time delay of the proposed DET D flip-flop are reduced by 20.5%,23.5%,and 25%,respectively.By using a lower clock pulse frequency,the proposed DET flip-flops are promising for constructing QCA sequential circuits and systems with high performance.     

Block cipher based on reversible cellular automata

We propose a new encryption algorithm relying on reversible cellular automata (CA). The behavior complexity of CA and their parallel nature makes them interesting candidates for cryptography. The proposed algorithm belongs to the class of symmetric key systems. Marcin Seredynski: He is a Ph.D. student at University of Luxembourg and Polish Academy of Sciences. He received his M.S. in 2004 from Faculty of Electronics and Information Technology in Warsaw University of Technology. His research interests include cryptography, cellular automata, nature inspired algorithms and network security. Currently he is working on intrusion detection algorithms for ad-hoc networks. Pascal Bouvry, Ph.D.: He earned his undergraduate degree in Economical & Social Sciences and his Master degree in Computer Science with distinction (’91) from the University of Namur, Belgium. He went on to obtain his Ph.D. degree (’94) in Computer Science with great distinction at the University of Grenoble (INPG), France. His research at the IMAG laboratory focussed on Mapping and scheduling task graphs onto Distributed Memory Parallel Computers. Next, he performed post-doctoral researches on coordination languages and multi-agent evolutionary computing at CWI in Amsterdam. He gained industrial experience as manager of the technology consultant team for FICS in the banking sector (Brussels, Belgium). Next, he worked as CEO and CTO of SDC (Ho Chi Minh city, Vietnam) in the telecom, semi-conductor and space industry. After that, He moved to Montreal Canada as VP Production of Lat45 and Development Director for MetaSolv Software in the telecom industry. He is currently serving as Professor in the group of Computer Science and Communications (CSC) of the Faculty of Sciences, Technology and Communications of Luxembourg University and he is heading the Intelligent & Adaptive Systems lab. His current research interests include: ad-hoc networks & grid-computing, evolutionary algorithms and multi-agent systems.     

Design of reversible logic based full adder in current-mode logic circuits

Demand of Very Large Scale Integration (VLSI) circuits with very high speed and low power are increased due to communication system's transmission speed increase. During computation, heat is dissipated by a traditional binary logic or logic gates. There will be one or more input and only one output in irreversible gates. Input cannot be reconstructed using those outputs. In low power VLSI, reversible logic is commonly preferred in recent days. Information is not lost in reversible gates and back computation is possible in reversible circuits with reduced power dissipation. Reversible full adder circuits are implemented in the previous work to optimize the design and speed of the circuits. Reversible logic gates like TSG, Peres, Feynman, Toffoli, Fredkin are mostly used for designing reversible circuits. However it does not produced a satisfactory result in terms of static power dissipation. In this proposed research work, reversible logic is implemented in the full adder of MOS Current-Mode Logic (MCML) to achieve high speed circuit design with reduced power consumption. In VLSI circuits, reliable performance and high speed operation is exhibited by a MCML when compared with CMOS logic family. Area and better power consumption can be produced implementing reversible logic in full adder of MCML. Minimum garbage output and constant inputs are used in reversible full adder. The experimental results shows that the proposed designed circuit achieves better performance compared with the existing reversible logic circuits such as Feynman gate based FA, Peres gate based FA, TSG based FA in terms of average power, static power dissipation, static current and area.     

多粒度可逆细胞自动机模型的数据加密方法

为了克服以往对细胞自动机的研究局限于单粒度细胞单元的问题,引入了多粒度细胞的概念,并结合可逆细胞自动机提出了一种基于多粒度可逆细胞自动机的加密算法.在该算法中,扩展的可逆细胞自动机具有足够多的规则,从而保证了安全的密钥空间;细胞单元通过"分裂-重组"实现自身粒度大小的动态调整,并依此来提高细胞自动机动力学特性的复杂性,实现了快速加、解密.同构的硬件结构使该算法具有很强的实用性,仿真实验表明,该加密算法具有较高的安全性.     

Representation of reversible cellular automata with block permutations

We demonstrate the structural invertibility of all reversible one- and two-dimensional cellular automata. More precisely, we prove that every reversible two-dimensional cellular automaton can be expressed as a combination of four block permutations, and some shift-like mappings. Block permutations are very simple functions that uniformly divide configurations into rectangular regions of equal size and apply a fixed permutation on all regions.     

Efficient exhaustive listings of reversible one dimensional cellular automata

This paper looks at an algebraic formulation of one dimensional cellular automata. Using the formulation connections to combinatorial structures and graph theory become clear. Strong results about uniqueness and isomorphism allows us to outline effective algorithms for the generation of exhaustive lists of reversible one dimensional cellular automata, and to count the number of distinct examples that exist. These algorithms use the “orderly algorithm” methods to avoid the pitfalls of brute force searches.     

Simulating reversible Turing machines and cyclic tag systems by one-dimensional reversible cellular automata

In this paper, we investigate how 1-D reversible cellular automata (RCAs) can simulate reversible Turing machines (RTMs) and cyclic tag systems (CTSs). A CTS is a universal string rewriting system proposed by M. Cook. First, we show that for any m-state n-symbol RTM there is a 1-D 2-neighbor RCA with a number of states less than (m+2n+1)(m+n+1) that simulates it. It improves past results both in the number of states and in the neighborhood size. Second, we study the problem of finding a 1-D RCA with a small number of states that can simulate any CTS. So far, a 30-state RCA that can simulate any CTS and works on ultimately periodic infinite configurations has been given by K. Morita. Here, we show there is a 24-state 2-neighbor RCA with this property.     

On the impact of the synchronization constraint and interconnections in quantum-dot cellular automata

Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology with remarkable performance and energy efficiency. Computation and information transfer in QCA are based on field forces rather than electric currents. As a consequence, new strategies are required for design automation approaches in order to cope with the arising challenges. One of these challenges is the transport of information, which is affected by two particularities of the QCA technology. First, information flow in QCA is controlled by external clocks, and second, QCA is a planar technology in which gates, as well as interconnections, are mostly located in the same layer. The former demands proper synchronization already during the circuit design phase, while the latter results in high area costs for interconnections. This work focuses on both constraints and discusses its impact on the implementation of QCA circuits. Further, the concept of local and global synchronicity in QCA circuits is explored. The obtained results indicate that relaxing the global synchronicity constraint can reduce design size by about 70% while the throughput performance declines by similar values. Additionally, it can be shown that the impact of interconnections in QCA, like wires, fan-outs, and crossovers, is indeed substantial. That means, up to 75% of the total area is occupied by interconnections.     

基于多子带可逆细胞自动机的二值图像压缩算法

提出一种新颖的基于多子带可逆细胞自动机的二值图像压缩算法。该算法采用可逆细胞自动机可实现信号子带编码的思想, 实现了一个四子带可逆细胞自动机, 并用其将二值图像信号分解为一个低频子带和三个高频子带。然后用改进的跳白块算法对各子带分别进行压缩编码。实验结果表明, 该算法计算复杂度低, 且具有较高的压缩比。     

基于二维X型可逆细胞自动机的加密算法

针对二维传统邻居类型细胞自动机结构和演化复杂、加密效率低,而一维细胞自动机密钥空间小、扩散速度慢、需要多轮迭代才能产生雪崩效应的问题,提出一种新的基于二维X型可逆细胞自动机并引入Arnold变换的加密算法。首先利用提出的细胞自动机对明文序列进行演化;在每一步演化结束后再对序列进行Arnold变换和循环移位变换;最后直到加密的密文满足要求,停止演化和变换。通过实验证明,密钥空间增大16.8%,可以抵抗穷举攻击;另外扩散性和混淆性好,能产生雪崩效应,可抵抗选择明文攻击。     

Pyroclastic flows modelling using cellular automata

Cellular automata (CA) and derived computational paradigms represent an alternative approach to differential equations to model and simulating complex fluid dynamical systems, whose evolution depends on the local interactions of their constituent parts. A new notion of CA was developed according to an empirical method for modelling macroscopic phenomena; its application to PYR, a CA model for simulating pyroclastic flows, generated PYR2, which permitted an improvement of the model and a more efficient implementation. PYR2 was utilised for the 1991 eruption of Mt. Pinatubo in the Philippines islands and for the 1996 eruption of the Soufriere Hills in the Montserrat Island. Results of the simulations are satisfactory if the comparison between real and simulated event is performed, considering the area involved by the event and the variations of thickness of the deposit, as generated by collapsing volcanic columns.