基于四值脉冲参数模型的单粒子瞬态传播机理与软错误率分析方法

随着工艺尺寸的不断缩小,由单粒子瞬态(Single Event Transient, SET)效应引起的软错误已经成为影响宇航用深亚微米VLSI电路可靠性的主要威胁,而SET脉冲的产生和传播也成为电路软错误研究的热点问题。通过研究SET脉冲在逻辑链路中的传播发现：脉冲上升时间和下降时间的差异能够引起输出脉冲宽度的展宽或衰减;脉冲的宽度和幅度可决定其是否会被门的电气效应所屏蔽。该文提出一种四值脉冲参数模型可准确模拟SET脉冲形状,并采用结合查找表和经验公式的方法来模拟SET脉冲在电路中的传播过程。该文提出的四值脉冲参数模型可模拟SET脉冲在传播过程中的展宽和衰减效应,与单参数脉冲模型相比计算精度提高了2.4%。该文应用基于图的故障传播概率算法模拟SET脉冲传播过程中的逻辑屏蔽,可快速计算电路的软错误率。对ISCAS89及ISCAS85电路进行分析的实验结果表明：该方法与HSPICE仿真方法的平均偏差为4.12%,计算速度提升10000倍。该文方法可对大规模集成电路的软错误率进行快速分析。     

PDSOI工艺下单粒子瞬态脉冲宽度分析

单粒子瞬态脉冲宽度是评价电子系统软错误率的重要参数之一。针对0.13 μm、部分耗尽型绝缘体上硅(PDSOI)工艺下的反相器链,解析地计算了反相器中产生的单粒子瞬态脉冲宽度,仿真了产生的单粒子瞬态脉冲在反相器链中传播时的临界脉冲宽度和传输率随级数变化情况。仿真结果表明,单粒子瞬态脉冲宽度的大小在几十皮秒到几百皮秒之间,反相器链的级数对临界脉冲宽度和传输率影响较大。最后仿真得到在输入单粒子瞬态脉冲宽度较小时,建立保持时间与输入脉冲宽度有关。该结果有利于电气掩蔽建模和锁存掩蔽建模准确性的提高。     

单粒子瞬态效应硬件注入模型实现和仿真

基于量化组合逻辑门延迟思想和扫描测试的方法,提出了一种适用于FPGA硬件模拟单粒子瞬态效应的门级注入模型.该模型考虑了电气掩蔽效应对脉冲传输的影响,通过该模型可以对组合电路任意逻辑门进行错误注入.基于该模型对ISCAS’85基准电路进行单粒子瞬态的研究,实验结果表明该脉冲产生方法高效,注入速度达到105 faults/s.     

基于地面加速测试的大气中子软错误率评估方法研究

大气中子单粒子效应导致的集成电路软错误给应用于地面和大气层中的具有高可靠性要求的电子系统带来了严重的失效风险,因此有必要对集成电路的大气中子软错误率进行评估.重点研究了大气中子导致的集成电路软错误的错误率的加速测试技术.首先,分别基于JESD 89A标准和EXPACS仿真工具计算了地球大气层中不同海拔处的中子通量,结果表明大气中子辐射场受海拔高度的影响非常明显;然后,以一款存储器电路为例,探讨了基于单能中子/质子源和散裂中子源的大气中子软错误率加速测试方法;最后,分别利用这两种方法对该存储器电路在海平面和飞机飞行高度处的软错误率进行了计算,飞机飞行高度处更高的软错误率表明航空飞行器面临着更严重的可靠性风险.     

红外焦平面读出电路片上驱动电路设计

线列红外焦平面读出电路在正常工作时需要提供多路数字脉冲和多路直流偏置电压。本文基于0.5 μm CMOS工艺设计了一款驱动电路芯片,为电容负反馈放大型（CTIA）读出电路（ROIC）提供驱动信号。电路芯片采用带隙基准电路产生低噪声低温漂的直流偏置电压,采用数字逻辑电路生成CLK1,CLK2,RESET等八路数字脉冲。仿真及测试结果表明：驱动电路芯片输出的数字脉冲及偏置电压符合设计值,可驱动CTIA型线列红外焦平面读出电路稳定工作。     

数字UWB脉冲发生器设计

讨论了当前UWB发展的形势.结合传统UWB脉冲发生器设计方法,采用数字设计技术,基于0.18μm工艺标准的CMOS技术,利用组合电路的竞争机制和短矩形脉冲的相位组合原理,设计出了低功耗窄宽度的UWB脉冲发生器,其功率谱符合FCC辐射掩蔽标准.经验证获得了很好的效果,得到的脉冲宽度为370 ps,峰值电压为380 mV.在脉冲重复频率为1 MHz和480 MHz时系统功耗分别仅为0.7 mW和17.4 mW.     

PRM、PTM组合调Q钕玻璃激光系统输出特性研究

介绍了脉冲反射式（PRM）、脉冲透射式（PTM）组合电光调Q激光系统的主要工作原理，并对影响其输出特性的主要参数进行了较系统的理论分析，给出了光束中两偏振分量间的相位差与晶体两端听加的电压之间的关系，系统输出能量透过率与所加电压间的关系。通过实验对组合调Q钕玻璃激光系统输出特性进行了测试，得到了较为理想的结果。     

把脉冲宽度转换为电压的电路

图1所示电路起源于无线电控制的模型化应用,在这类应用中要求电压与输入的伺服脉冲宽度成正比。该电路已对1～2ms的正向脉冲宽度进行了优化,重复时间间隔约为17ms。输出端对1ms的脉冲产生0.95V的电压,对2ms脉冲则产生2.25V电压。该电路的工作方式类似于一个PLL电路,但它与PLL电路不同,它锁定在输入信号的脉冲宽度上,而不是在频率上。IC_(IA)是一个单稳态多谐振荡器,其时间常数是R_1、FET导通电及C_1的函     

一种模拟SET的脉冲产生方法

提出一种基于PLL(Phase Locked Loop)的电子脉冲产生方法,利用该方法可以产生最小宽度为325ps的瞬态脉冲并对SRAM型FPGAs(Field Programmable Gate Arrays)中实现的组合逻辑电路进行SET传播特性的研究.实验结果表明该脉冲产生方法实现简单,可以在不改变电路布局布线的前提下,改变注入脉冲宽度,且由PLL相位计算出的理论脉冲宽度与实际测量误差小于3%.     

基于空间矢量调制的三相电压型PWM整流系统仿真

为了解决正弦脉冲宽度调制（SPWM）技术应用于传统电压型PWM整流时过程复杂且直流电压利用率很低等问题,提出了一种在同步参考坐标下的三相电压模型控制策略,这种采用空间矢量脉冲宽度调制（SVPWM）的整流器具有高质量的直流侧电压和功率因数。文中最后还提供了MATLAB/SIMULINK的仿真模型,并用仿真结果证实了模型的正确性及其控制方法。     

Soft error generation analysis in combinational logic circuits

Reliability is expected to become a big concern in future deep sub-micron integrated circuits design.Soft error rate(SER) of combinational logic is considered to be a great reliability problem.Previous SER analysis and models indicated that glitch width has a great impact on electrical masking and latch window masking effects,but they failed to achieve enough insights.In this paper,an analytical glitch generation model is proposed.This model shows that after an inflexion point the collected charge has an...     

Characterizing,modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits

Soft errors, due to cosmic radiations, are one of the major challenges for reliable VLSI designs. In this paper, we present a symbolic framework to model soft errors in both synchronous and asynchronous designs. The proposed methodology utilizes Multiway Decision Graphs (MDGs) and glitch-propagation sets (GP sets) to obtain soft error rate (SER) estimation at gate level. This work helps mitigate design for testability (DFT) issues in relation to identifying the controllable and the observable circuit nodes, when the circuit is subject to soft errors. Also, this methodology allows designers to apply radiation tolerance techniques on reduced sets of internal nodes. To demonstrate the effectiveness of our technique, several ISCAS89 sequential and combinational benchmark circuits, and multiple asynchronous handshake circuits have been analyzed. Results indicate that the proposed technique is on average 4.29 times faster than the best contemporary state-of-the-art techniques. The proposed technique is capable to exhaustively identify soft error glitch propagation paths, which are then used to estimate the SER. To the best of our knowledge, this is the first time that a decision diagram based soft error identification approach is proposed for asynchronous circuits.     

A pre-silicon logic level security verification flow for higher-order masking schemes against glitches on FPGAs

Higher-order masking schemes have been proven in theory to be secure countermeasures against side-channel attacks in the algorithm level. The ISW framework is one of the most acceptable secure models of the existing higher-order masking schemes. However, a gap may exist between scheme and implementation. Several analyses have exhibited the weakness of masking in hardware designs on FPGAs. Firstly, we give the definition of leakage point and introduce three implementation logical flaws: glitch, EDA optimization and intermediate variable of scheme flaw. Secondly, we propose a leakage verification flow for implementing and verifying circuits realized higher-order masking schemes to avoid these leakage points. The flow provides an efficient evaluation method to locate and identify leakage points in masking hardware implementations. With the knowledge of the weaknesses of implementation, the implementation should be modified by corresponding methods to fix flaws, especially for glitch, which has been regarded as the main challenge of masking in hardware designs, we provide a method to remove the leakage point using Dijkstra algorithm with no extra time and area overheads. Finally, the design flow is evaluated on the implementation of Rivain&Prouff masking. Our experiments demonstrate how it automatically locates and protects the implementation. In addition, the experiments are also performed on flawed implementations due to EDA optimization and intermediate variables.     

Ser performance analysis of decode-and-forward cooperative scheme in satellite mobile channel

In this paper, Symbol-Error-Rate (SER) performance analysis is provided for a Decode-and-Forward (DF) cooperative scheme in satellite mobile channel environment. We present a satellite mobile cooperative communication system model and derive two generalized error probability expressions with Cyclical Redundancy Check (CRC) or not. We also derive and simulate SER of the proposed system over different satellite mobile channels. The results show that the analytical results are in great accordance with the ones obtained by simulation. Also, it was shown that, whether or not adopt CRC depends on the channel link quality between the source node and the relay node.     

SER PERFORMANCE ANALYSIS OF DECODE-AND-FORWARD COOPERATIVE SCHEME IN SATELLITE MOBILE CHANNEL

In this paper,Symbol-Error-Rate (SER) performance analysis is provided for a Decodeand-Forward (DF) cooperative scheme in satellite mobile channel environment.We present a satellite mobile cooperative communication system model and derive two generalized error probability expressions with Cyclical Redundancy Check (CRC) or not.We also derive and simulate SER of the proposed system over different satellite mobile channels.The results show that the analytical results are in great accordance with the ones obtained by simulation.Also,it was shown that,whether or not adopt CRC depends on the channel link quality between the source node and the relay node.     

Power estimation method for highly correlated input sequences underrealistic delay model

A new power estimation method is presented which considers spatio-temporal correlations among the primary inputs as well as the glitch effect under a realistic delay model. To deal with the glitch effect, the symbolic simulation technique is employed, and to take the correlations among the primary inputs into account, the authors employ a new technique which transforms correlation information into a logic structure, called `pre-logic'. Experimental results show that the estimation error of the proposed method is ~4% under a realistic delay model with highly correlated input streams     

Sequential Element Design With Built-In Soft Error Resilience

This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in latches and flip-flops. The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design-for-testability and design-for-debug resources to minimize area overheads. Circuit simulations using a sub-90-nm technology show that the presented designs achieve more than a 20-fold reduction in cell-level soft error rate (SER). Fault injection experiments conducted on a microprocessor model further demonstrate that chip-level SER improvement is tunable by selective placement of the presented error-correcting designs. When coupled with error correction code to protect in-pipeline memories, the BISER flip-flop design improves chip-level SER by 10 times over an unprotected pipeline with the flip-flops contributing an extra 7-10.5% in power. When only soft errors in flips-flops are considered, the BISER technique improves chip-level SER by 10 times with an increased power of 10.3%. The error correction mechanism is configurable (i.e., can be turned on or off) which enables the use of the presented techniques for designs that can target multiple applications with a wide range of reliability requirements     

Cosmic-ray soft error rate characterization of a standard 0.6-μmCMOS process

Cosmic-ray soft errors from ground level to aircraft flight altitudes are caused mainly by neutrons. We derived an empirical model for estimation of soft error rate (SER). Test circuits were fabricated in a standard 0.6-μm CMOS process. The neutron SER dependence on the critical charge and supply voltage was measured. Time constants of the noise current were extracted from the measurements and compared with device simulations in three dimensions. The empirical model was calibrated and verified by independent SER measurements. The model is capable of predicting cosmic-ray neutron SER of any circuit manufactured in the same process as the test circuits. We predicted SER of a static memory cell     

酉空时调制系统中最大似然多符号差分检测的性能分析

在酉空时调制系统中,针对连续衰落信道下最大似然多符号差分检测给出了一种误符号率截断联合界的数值计算方法.采用Gauss-Chebyrshev求积公式对成对错误概率进行数值计算,并利用提取主要错误事件技术对误符号率的联合界进行了化简.数值与仿真结果表明,采用该方法计算出的截断联合界可以在低信噪比下提供误符号率的一个上界,在较高信噪比下获得它的良好估计.在性能分析基础上进一步提出了一种近似最大似然度量,分析与仿真说明,采用该度量的多符号差分检测算法的性能非常接近最大似然检测.     

Soft error modeling and remediation techniques in ASIC designs

Soft errors due to cosmic radiations are the main reliability threat during lifetime operation of digital systems. Fast and accurate estimation of soft error rate (SER) is essential in obtaining the reliability parameters of a digital system in order to balance reliability, performance, and cost of the system. Previous techniques for SER estimation are mainly based on fault injection and random simulations. In this paper, we present an analytical SER modeling technique for ASIC designs that can significantly reduce SER estimation time while achieving very high accuracy. This technique can be used for both combinational and sequential circuits. We also present an approach to obtain uncertainty bounds on estimated error propagation probability (EPP) values used in our SER modeling framework. Comparison of this method with the Monte-Carlo fault injection and simulation approach confirms the accuracy and speed-up of the presented technique for both the computed EPP values and uncertainty bounds.Based on our SER estimation framework, we also present efficient soft error hardening techniques based on selective gate resizing to maximize soft error suppression for the entire logic-level design while minimizing area and delay penalties. Experimental results confirm that these techniques are able to significantly reduce soft error rate with modest area and delay overhead.