Threshold voltage and C-V characteristics of SOIMOSFET's related to Si film thickness variation on SIMOX wafers

C-V characteristics of fully depleted SOI MOSFETs have been studied using a technique for measuring silicon-film thickness using a MOSFET. The technique is based on C-V measurements between the gate and source/drain at two different back-gate voltages, and only a large-area transistor is required. Using this technique, SOI film thickness mapping was made on a finished SIMOX wafer and a thickness variation of ±150 Å was found. This thickness variation causes as much as a 100-mV variation in the device threshold voltage. The silicon-film thickness variation and threshold-voltage variation across a wafer shows a linear correlation dependence for a fully depleted device. C-V measurements of the back-gate device yield the buried-oxide thickness and parasitic capacitances. The effects of GIDL (gate-induced drain leakage) current on C-V characteristics are also discussed     

Current-crowding effect in diagonal MOSFET's

Electrical and reliability characteristics of diagonally shaped n-channel MOSFETs have been extensively investigated. Compared with the conventional device structure, diagonal MOSFETs show longer device lifetime under peak I_sub condition (V_g =0.5 V_d). However, in the high-gate-bias region (V_g=V_d), diagonal MOSFETs exhibit a significantly higher degradation rate. From the I_sub versus gate voltage characteristics, this larger degradation rate under high gate bias is concluded to be due mainly to the current-crowding effect at the drain corner. For a cell-transistor operating condition (V_g>V_d), this current-crowding effect in the diagonal transistor can be a serious reliability concern     

Combined effects of hot-carrier stressing and ionizing radiation inSiO2, NO, and ONO MOSFETs

N-channel MOSFETs with different gate dielectrics, such as silicon dioxide, silicon dioxide annealed in nitrous oxide (NO), and reoxidized nitrided oxide (ONO), were first hot-carrier (HC) stressed and then irradiated to a total dose of 1.5 Mrd. For equal substrate current stressing NO devices have the least degradation, whereas the threshold voltage (V_t) shift due to irradiation is maximum for these devices. For all three types of gate dielectrics the V _t shift due to irradiation of HC stressed devices was higher than that of the unstressed device. However, for ONO devices the V _t shift due to irradiation of the hot-electron stressed (stressing with V_d=V_g=6.5 V) device was less than that of the unstressed device     

Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization

Multiple-gate devices, such as the planar double-gate (DG), triple-gate (TG), FinFET, Pi-Gate (PG), and Omega-Gate Silicon-on-Insulator (SOI) MOSFETs are potential candidates for achieving the performance targets of the International Roadmap of the Semiconductor Industry Association. In this paper, wideband experimental and three-dimensional simulation analyses have been carried out to compare the analog/RF performance of DG, TG/FinFET, PG, and single-gate (SG) SOI MOSFETs. The characteristics of the multiple-gate devices were analyzed in the dc and ac regimes from subthreshold region to strong inversion and saturation regions. In both regimes, the advantages and limitations of the multiple-gate devices over the SG structure are discussed for channel length scaling well below 100 nm. To the authors' knowledge, it is the first time that such extensive results and analyses are presented on the potential of these novel devices for high-frequency analog applications.     

Electron velocity overshoot at room and liquid nitrogentemperatures in silicon inversion layers

Effective electron velocities in silicon MOSFETs exceeding the bulk saturation values of 10⁷ cm/s at room temperature and 1.3×10⁷ cm/s at liquid-nitrogen temperature are inferred. This conclusion suggests that electron velocity overshoot occurs over a large portion of the device channel length. To infer this phenomenon, submicrometer-channel-length Si MOSFETs with lightly doped inversion layers were fabricated. These devices have low field mobility of 450 cm²/V-s and showed only slight short-channel effects. Effective carrier velocities are calculated from the saturated transconductance g_m at V_DS=1.5 V after correction for parasitic resistances of source and drain     

A thorough investigation of the degradation induced by hot-carrierinjection in deep submicron N- and P-channel partially and fullydepleted unibond and SIMOX MOSFETs

A thorough investigation of hot-carrier effects in deep submicron N- and P-channel SOI MOSFET's is reported in this paper. First, a comparison of device aging among three types of SOI devices fabricated by various technologies is shown. The carrier type, the quality of oxides, and the device structure are key parameters for the degradation mechanisms in these devices. On the other hand, the worst-case aging (V _d=V_t,V_d/2 or V_d) also depends on these device distinctions. For fully depleted SOI MOSFETs, the variation of the main electrical parameters is determined with and without the influence of defects in the buried oxide. The device lifetime of NMOS/SOI in the worst-case condition is carefully predicted using accurate methods that take into account the degradation saturation and the region of defect creation (Si/SiO₂ interface and/or oxide volume). Finally, an investigation of the aging/recovery mechanisms is carried out in P-channel SOI MOSFETs under an alternating stress     

Quality of gate oxides grown on state-of-the-art SIMOX and ZMR SOIsubstrates

The quality of 25-nm gate oxides formed on state-of-the-art SIMOX and ZMR silicon-on-insulator (SOI) substrates was studied using NMOSFETs. Circular, edgeless, and conventional island isolated devices were used. Devices fabricated on bulk silicon wafers were studied for comparison. I-V characteristics, breakdown voltages, charge trapping, and charge to breakdown were characterized. The results clearly demonstrated that the quality of SIMOX and ZMR wafers and especially of the top Si surface was as good as that of bulk silicon. The quality of the gate oxides formed on island isolated devices was poor due to defective oxide formed on the sidewalls. A comparison of circular, edgeless MOSFETs and island isolated MOSFETs can be used to optimize island etching, sidewall cleaning, and gate oxidation processes     

Two-dimensional analytic modeling of very thin SOI MOSFETs

An analytic solution of the Poisson's equation for MOSFETs on very thin SOI (silicon on insulator) was developed using an infinite series method. The calculation region includes the thin SOI and the gate and buried oxides. The results of this model were found to agree well with a two-dimensional (PISCES) simulation in the subthreshold region and the linear region with small V_DS. This model is used to study the short-channel behavior of very small MOS transistors on thin SOI. It is found that with very thin SOI, short-channel effects are much reduced compared to bulk MOS transistors and depend on the bulk-substrate bias. The model also shows that it is possible to fabricate submicrometer transistors on very thin SOI even if the channel doping is nearly intrinsic     

Operation of SOI CMOS devices at liquid-nitrogen temperature

Liquid-nitrogen-temperature (LNT) operation of silicon-on-insulator (SOI) CMOS devices has been investigated experimentally. The maximum carrier mobilities in these devices increase by factors from 1.25 to 4.5 between room temperature and LNT. At LNT, the increase in depletion-layer width and the resulting threshold-voltage increase are limited by the silicon film thickness. For SOI devices with a body contact, the series resistance between channel and body contact increases at lower temperature, resulting in a current kink in saturation I-V characteristics     

Complimentary single-electron/hole action of nanoscale SOI CMOS transistors

We propose a new device structure for room-temperature single-electron/hole transistors based on nanosize narrow-width fully depleted silicon-on-insulator (SOI) CMOS transistors. The floating body of SOI MOSFETs can become a Coulomb island, whose single charging energy is more than 30 meV, as the gate length and width of MOSFETs is less than 10 nm. As SOI MOSFETs are biased at accumulation, single-electron, or hole tunnels, are sent, one by one, from the source to the floating body and then to the drain via Zener tunneling process. N-channel SOI MOSFETs can have the functions of single-electron transistors (n-SETs) while p-channel MOSFETs can have the functions of single-hole transistors (p-SETs). SOI MOSFETs still behave as typical MOSFETs when biased at inversion. There is a gate voltage margin of 0.9 V to separate Coulomb blockade oscillations from CMOS normal operation.     

Enhanced substrate current in SOI MOSFETs

This letter reports an enhanced substrate current at high gate bias in SOI MOSFETs. A comparison between coprocessed bulk and partially depleted SOI MOSFETs is used to present the enhancement unique to SOI devices and demonstrate the underlying mechanism. Other than electric field, a new source for carrier heating in the channel, i.e., self-lattice heating, is found to be responsible for the excess substrate current observed. The impact of this phenomenon on SOI device lifetime prediction and compact modeling under dynamic operating conditions typical of digital circuit operation is described. This SOI-specific enhancement must be considered in one-to-one comparisons between bulk and SOI MOSFETs regarding hot-carrier effects     

Narrow-width SOI devices: the role of quantum-mechanical size quantization effect and unintentional doping on the device operation

The ultimate limits in scaling of conventional MOSFET devices have led the researchers from all over the world to look for novel device concepts, such as ultrathin-body (UTB) silicon-on-insulator (SOI), dual-gate SOI devices, FinFETs, focused ion beam MOSFETs, etc. These novel devices suppress some of the short channel effects exhibited by conventional MOSFETs. However, a lot of the old issues still remain and new issues begin to appear. For example, in UTB SOI devices, dual-gate MOSFETs and in FinFET devices, quantum-mechanical size quantization effects significantly affect the overall device behavior. In addition, unintentional doping leads to considerable fluctuation in key device parameters. In this work we investigate the role of two-dimensional quantization effects in the operation of a narrow-width SOI device using an effective potential scheme in conjunction with a three-dimensional ensemble Monte Carlo particle-based device simulator. We also investigate the influence of unintentional doping on the operation of this device. We find that proper inclusion of quantization effects is needed to explain the experimentally observed width dependence of the threshold voltage. With regard to the problem of unintentional doping, impurities near the middle portion of the source end of the channel have most significant impact on the device drive current and the fluctuations in the device threshold voltage.     

Anomalous C-V characteristics of implanted polyMOS structure in n+/p+ dual-gate CMOS technology

The C-V characteristics of arsenic-doped polysilicon show a gate-bias dependence of the inversion capacitance and a reduction in the expected value of the inversion capacitance. The characteristics have been investigated with quasistatic and high-frequency C-V as well as conductance measurements of various capacitors that have been subjected to annealing times and temperatures ranging from 900°C/30 min to rapid thermal annealing at 1050°C. The results can be explained by assuming that there is a depletion region forming in the polysilicon due to insufficient activation of the dopant at the polysilicon/oxide surface. The impact of this condition on the device characteristics is shown to be a 20-30% reduction in the G_m of NMOS transistors with 125-Å Gate oxide thickness     

Back-gate bias effect on the subthreshold behavior and theswitching performance in an ultrathin SOI CMOS inverter operating at 77and 300 K

The effect of back-gate bias on the subthreshold behavior and the switching performance in an ultrathin SOI CMOS inverter operating at 300 and 77 K is investigated using a low-temperature device simulator. The simulation results show that the nonzero back-gate bias induces hole pile-up at the back interface, which causes opposite effects on the NMOS and PMOS subthreshold characteristics at 300 and 77 K. Throughout the transient process, at 300 K, for V_B=-5 V operation, hole pile-up at the back interface always exists in the NMOS device. Compared to the zero back-gate bias case, at V_B=-5 V, the risetime of the SOI CMOS inverter is over 5% shorter at 77 and 300 K and the falltime is 5% longer. Prepinch-off velocity saturation in the NMOS device dominates the pull-down transient as a result of the smaller electron critical electric field     

A complete model of the I-V characteristics fornarrow-gate MOSFETs

A unified and process-independent MOSFET model for accurate prediction of the I-V characteristics and the threshold voltages of narrow-gate MOSFETs is discussed. It is based on several enhancements of the SPICE2 LEVEL3 MOS model and the author's previous subthreshold I-V model. The expressions achieved for the drain current hold in the subthreshold, transition, and strong inversion regions. A continuous model is proposed for the transition region, using a scheme that ensures that both the current and conductance are continuous and will not cause convergence problems for circuit simulation applications. All of the modeled parameters are taken from experimentally measured I-V characteristics and preserve physical meaning. Comparisons between the measured and modeled I-V characteristics show excellent agreement for a wide range of channel widths and biases. The model is well suited for circuit simulation in SPICE     

Threshold voltage model for deep-submicrometer MOSFETs

The threshold voltage, V_th, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V_th on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V_th dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined     

Numerical analysis of alpha-particle-induced soft errors in SOI MOSdevices

Alpha-particle-induced soft errors in SOI MOSFETs are examined using a three-dimensional device simulation. A bipolar mechanism induced by the alpha-particle incidence is investigated in detail when an alpha particle penetrates from the drain region toward the source region. In SOI MOSFETs, the drain collected and source injected charges are mainly due to a bipolar mechanism. The bipolar mechanism in SOI MOSFETs is quite different from that which has been so far reported in bulk MOSFETs, and operates with a very small current of less than 1 nA for a very long time of 1 ns to 100 ms. The drain collected and source injected charges are strongly dependent on various device parameters and lifetimes. The results suggest that the bipolar mechanism is a significant cause of soft errors in SOI MOSFETs     

On/off current ratio in P-channel poly-Si MOSFETs: dependence onhot-carrier stress conditions

Stress effects on poly-Si PMOS devices are investigated, and stress is related to the improvement or degradation of PMOS on/off current ratio. P-channel polysilicon MOSFETs have been stressed in the saturation and off-state regimes. Both the drive (on) current and leakage (off) current can be either increased or decreased after particular bias stress. On/off current ratio can be decreased by a factor of 2 for a stress bias of V_GS=V_DS=-11 V, but can be increased by a factor of 50 for a stress bias of V_GS=-2 V, V_DS=-11 V. Two effects of bias stress have been identified in poly-Si PMOS devices for which the on/off current ratio can either be increased or decreased after stress bias depending on the value of stress bias V_GS. These effects of room-temperature stress are proposed to be due to either trapping of hot electrons or hot-hole-induced donor-type interface state generation     

Leakage-current-induced hot-carrier degradation of p-channelMOSFETs

Leakage-current-induced hot-carrier effects have been observed during stressing of p-channel MOSFETs in the OFF state with V _GS>0 V and V_DS<0 V. This mode of stressing results in increased leakage current and a positive shift in the value of V_GS, corresponding to the onset of avalanche breakdown of the drain junction. These effects are related to generation of interface states near the drain in forward-mode operation. By comparison, conventional stressing in the ON state with V _GS<0 V and V_DS<0 V resulted in little change in these p-channel MOSFET characteristics     

A latch phenomenon in buried N-body SOI NMOSFET's

The authors show that a snapback effect resulting in a latching can exist in a buried N-body NMOS device on silicon-on-insulator (SOI). Using numerical simulations, it is demonstrated that when V_GS is less than the flat-band voltage and after triggering, this kind of device behaves as a floating-base n-p-n bipolar transistor, the base hole density of which is controlled by an inversion layer instead of the usual base doping. The latch phenomenon results from the combination of this parasitic quasi-bipolar device, a back surface NMOS transistor, and impact ionization current