Bit error rate experiments in ring-shaped RSFQ circuits

Ring-shaped rapid single flux quantum (RSFQ) circuits composed of segments of Josephson transmission lines (JTLs) and other RSFQ circuits enable permanent SFQ pulse circulation. New ring structures of different designs have been realized which comprise T-flipflop (TFF) and multiplier (MULT) circuits. Reliability in circuit operation has been proven experimentally by a bit error rate BER≅10⁻¹⁶. The fabrication process has been optimized by using PTB-4 μm Nb/Al₂O₃–Al/Nb trilayer technology with externally shunted tunnel junctions of critical current densities of j_c=≅1 kA/cm². Characteristic voltage is V_c=250 μV and Steward–McCumber parameter β_c≤1. A linear dependence of pulse circulation frequency on JTL bias currents has been measured within a bias current interval of 20%.     

RSFQ logic/memory family: a new Josephson-junction technology forsub-terahertz-clock-frequency digital systems

Recent developments concerning the rapid single-flux-quantum (RSFQ) circuit family are reviewed. Elementary cells in this circuit family can generate, pass, memorize, and reproduce picosecond voltage pulses with a nominally quantized area corresponding to transfer of a single magnetic flux quantum across a Josephson junction. Functionally, each cell can be viewed as a combination of a logic gate and an output latch (register) controlled by clock pulses, which are physically similar to the signal pulses. Hand-shaking style of local exchange by the clock pulses enables one to increase complexity of the LSI RSFQ systems without loss of operating speed. The simplest components of the RSFQ circuitry have been experimentally tested at clock frequencies exceeding 100 GHz, and an increase of the speed beyond 300 GHz is expected as a result of using an up-to-date fabrication technology. This review includes a discussion of possible future developments and applications of this novel, ultrafast digital technology     

Characteristics of driver and receiver circuits with a passivetransmission line in RSFQ circuits

We report simulated results of-rapid single flux quantum (SFQ) circuits having driver, receiver, and passive transmission lines for propagating SFQ pulses to investigate the design criteria. We have studied the equivalent input/output resistance of the driver/receiver in various bias conditions and found that the resistance is almost proportional to the bias current of the driver/receiver. Furthermore, we have proposed inserting a series resistor at the end of the superconducting passive transmission line (PTL) for avoiding undesirable flux trapping in the loop and for isolation in regard to the DC current. We also found that the reduction of the bias margin due to the resistance is rather small when the resistance is much smaller than the impedance of the PTL. An operating margin of more than 30% was obtained in the driver/receiver circuits including the PTL and the series resistor     

Self-timing and vector processing in RSFQ digital circuittechnology

As the operating speed of rapid single flux quantum (RSFQ) integrated circuits and systems increases, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, the authors present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. They also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High-speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists of two self-timed shift registers and an on-chip 8-28-GHz clock generator     

Linewidth measurements and phase locking of Josephson oscillatorsusing RSFQ circuits

We present a technique for linewidth measurement and phase-locking of Josephson oscillators using digital rapid single-flux-quantum (RSFQ) circuits. The oscillator consists of a resistively shunted 6 μm×6 μm Nb/AlO_x/Nb Josephson tunnel junction that is integrated with RSFQ input and output circuits. A cascade of RSFQ T flip-flops is used to directly monitor the output of the Josephson oscillator. Spectral characteristics have been measured directly for oscillator frequencies ranging from 10-50 GHz. The linewidth can be reduced by over 100 times by phase-locking the oscillator to an RSFQ pulse train generated by an external sinusoidal signal. These Josephson oscillators can be used as on-chip stable high frequency clocks for RSFQ circuits     

GaAs integrated circuits for error-rate measurement in high-speed digital transmission systems

A high-speed GaAs MSI PRBS generator and an error detector have been built, tested, and applied to bit-error ratio measurements in a fiber-optic transmission link. The generator produces a 1023 bit sequence at 2 Gbit/s data rate. The detector compares, bit-by-bit, the input data with a locally regenerated sequence. With a 2 GHz clock, the direct-coupled generator/detector combination, without an optical link, exhibits less than one error in 10/SUP 14/ clock cycles. The complete fiber-optic link test system incorporates a 1 km multimode fiber, operates at 1.9 Gbits/s, and exhibits a bit-error ratio below 10/SUP -12/.     

Substrate coupling in digital circuits in mixed-signal smart-power systems

This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effects created by high-power analog circuits and affecting sensitive digital circuits on the same integrated circuit. The sources and mechanism of the noise behavior of such digital circuits are identified and analyzed. The results are obtained primarily from a set of dedicated test circuits specifically designed, fabricated, and evaluated for this work. The conclusions drawn from the theoretical and experimental analyses are used to develop physical and circuit design techniques to mitigate the substrate noise problems. These results provide insight into the noise immunity of digital circuits with respect to substrate coupling.     

Error-feedback circuits for digital filters

Criteria are developed for the design of a very general error-feedback circuit whose purpose is to eliminate the presence of nonlinear phenomena, caused by the occurrence of adder overflows, in the forced response of a 2nd-order recursive digital filter.     

Timing verification of dynamic circuits

A complete set of rules is presented for timing verification of domino-style dynamic circuits. These rules include identification of dynamic nodes, generation of accurate timing constraints based on the operating environment of the gate and verification as an enhanced part of a complete timing verification process. This methodology has been implemented in a new static timing verifier and used to verify microprocessor circuits     

Charge-coupled digital circuits

This paper describes the operation and the applications of charge- coupled shift registers for digital signals. Simple signal-regeneration stages for digital charge-coupled shift registers are analyzed and their operation is demonstrated by charge-coupled circuits made by a p-MOS process. A charge-transfer efficiency of about 99.6 percent per electrode at a clock frequency of 1 MHz was obtained in the operation of three-phase 8-bit shift registers made by the p-MOS process. Silicon-gate construction is proposed for achieving high- performance high-density structures and also two-phase charge-coupled devices.     

Statistical RTS model for digital circuits

In this work we study the variation in drain current of MOS transistors due to the capture and emission of electrons at interface states (traps), called random telegraph signal (RTS). Usually, RTS is studied in frequency domain. However, for digital circuits, it is more appropriate to use time-domain representations.The time-domain representation here proposed models the effect of RTS on I_ds as instantaneous Vt shifts. We introduce a statistical numerical approach for computing the total ΔVt of the transistor considering all the traps in the interface. The method analyses the effect of non-uniform charge densities along the channel. To show the applicability of the methodology to circuit analysis on the electrical level, the model is applied to characterize read and write instability failures caused by RTS on a 6T-SRAM cell.     

Built-in test for complex digital integrated circuits

A method for testing the logic function of complex digital integrated circuits is presented. The extra hardware needed is kept minimal by functional conversion of already existing components (e.g., registers). The feasibility of the proposed method is demonstrated by results from both hardware simulation and logic simulation. The method is based on an adapted version of signature analysis, and on circuit partitioning (the structure of VLSI circuits is assumed to be inherently modular).     

Low-power clock-deskew buffer for high-speed digital circuits

An IC containing four clock deskew buffers using the delay-locked-loop technology has been fabricated in a 0.6 μm single poly double metal CMOS process. The core chip area is 0.9×0.9 mm ². The maximum operating frequency is 80 MHz, and the total power dissipation of the four deskew buffers is 59 mW for a 3 V supply voltage. The maximum clock skew after deskewing is less than 300 ps, and the peak-to-peak clock jitter is less than 170 ps. The deskew range is 0.5-3.8 ns     

Adaptively designed test logic for digital circuits

Adaptive n-tuple pattern-recognition techniques in their hardware embodiment may be used to design test circuits for logic systems which indicate the presence of a fault. The principles of this concept are explained and early results obtained with realistically scaled circuits are presented.     

Dual-threshold voltage techniques for low-power digital circuits

Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation. This paper presents several dual-threshold voltage techniques for reducing standby power dissipation while still maintaining high performance in static and dynamic combinational logic blocks. MTCMOS sleep transistor sizing issues are addressed, and a hierarchical sizing methodology based on mutual exclusive discharge patterns is presented. A dual-V_t domino logic style that provides the performance equivalent of a purely low-V _t design with the standby leakage characteristic of a purely high-V_t implementation is also proposed     

Adaptive logic circuits for digital stochastic computers

A theoretical and experimental investigation of adaptive logic elements suitable for use as an output interface for digital stochastic computers is presented. An adaptive digital element using a binary rate multiplier is demonstrated to provide a significant improvement in accuracy without reduction in bandwidth characteristics.     

多阶段编程定制数字电路

硬件描述语言在描述数字电路时面临抽象层次低、难以验证、工作量大等困难。以快速傅立叶变换电路设计为例,提出多阶段编程定制数字电路的方法,规避这些不便。利用高层次描述方法为应用系统建模,消除冗余计算和递归,产生简单函数。从简单函数中提取简化操作序列。最后,选择合适的电路设计方案,转化为硬件描述语言的代码,并自动生成可综合的电路。该方法适于自动定制系列电路。     

Compaction-based concurrent error detection for digital circuits

We present a non-intrusive concurrent error detection (CED) method for combinational and sequential digital circuits. We analyze the optimal solution model and point out the limitations that prevent logic synthesis from yielding a minimal-cost monolithic CED implementation. We then propose a compaction-based alternative approach for restricted error models. The proposed method alleviates these limitations by decomposing the CED functionality into: compaction of the circuit outputs, prediction of the compacted responses, and comparison. We model the fault-free and erroneous responses as connected vertices in a graph and perform graph coloring in order to derive the compacted responses. The proposed method is first discussed within the context of combinational circuits, with zero detection latency, and subsequently extended to Finite State Machines (FSMs), with a constant detection latency of one clock cycle. Experimental results demonstrate that the proposed method achieves significant hardware reduction over duplication-based CED, while detecting all possible errors.