An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributedtrack-and-hold preprocessing

An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology. The presented extension of the well known folding concept has resulted in a 75 MHz maximum full-scale input signal frequency. A signal-to-noise ratio of 44 dB is obtained for this frequency. The 8-b A/D converter achieves a clock frequency of 80 MHz with a power dissipation of 80 mW from a 3.3 V supply voltage. The active chip area is 0.3 mm² in 0.5-μm standard digital CMOS technology     

A wireless implantable multichannel digital neural recording systemfor a micromachined sieve electrode

This paper reports the development of an implantable, fully integrated, multichannel peripheral neural recording system, which is powered and controlled using an RF telemetry link. The system allows recording of ±500 μV neural signals from axons regenerated through a micromachined silicon sieve electrode. These signals are amplified using on-chip 100 Hz to 3.1 kHz bandlimited amplifiers, multiplexed, and digitized with a low-power (<2 mW), moderate speed (8 μs/b) current-mode 8-b analog-to-digital converter (ADC). The digitized signal is transmitted to the outside world using a passive RF telemetry link. The circuit is implemented using a bipolar CMOS process. The signal processing CMOS circuitry dissipates only 10 mW of power from a 5-V supply while operating at 2 MHz and consumes 4×4 mm² of area. The overall circuit including the RF interface circuitry contains over 5000 transistors, dissipates 90 mW of power, and consumes 4×6 mm² of area     

A 1-V 6-b 50-MSamples/s current-interpolating CMOS ADC

CMOS analog-to-digital converters (ADC's) require either bootstrapping techniques or low-threshold devices to function at low supply voltages. A 6-b 50-MSamples/s ADC in normal-threshold CMOS operates with a single battery cell as low as 0.9 V without bootstrapping. A current-interpolation approach is taken to configure a 1-V ADC system that does not allow more than one V_GS plus one V_DSsat between the supply rails. The prototype takes a rail-to-rail input and works with a single system clock. The chip fabricated in 0.35-μm CMOS occupies an area of 2.4×2 mm² and consumes 10 mW each in analog and digital supplies     

A power and area efficient CMOS clock/data recovery circuit forhigh-speed serial interfaces

A power and area efficient CMOS clock/data recovery circuit designed for a wide range of applications in high-speed serial data communications is described. It uses an analog phase-locked loop (PLL) to generate the high-speed clocks with an absolute rms jitter of less than 60 ps and a digital PLL which is designed to minimize chip area and power consumption to recover the clock and data signals from the incoming data stream. Fabricated in a 0.8 μm single-polysilicon, double-metal CMOS process, the digital PLL only consumes 45 mW at 125 Mb/s from a single 5 V supply, while the analog PLL consumes 92 mW. The chip area is 1.7 mm² for the digital PLL and 0.44 mm² for the analog PLL. It can handle an input data rate up to 280 Mb/s     

A total solution for a 9600-b/s modem transmitter chip

A single-chip analog transmitter (TX chip) for a V29-V32 9600-b/s modem has been implemented in a 3-μm CMOS n-well process. A high level of integration permits a low-cost, high-performance modem to be built. The TX chip is composed of analog, switched capacitor, and digital circuits. The important functions realized are the phase-point generator, the cosine roll-off low-pass filter, the modulator, and the programmable equalization filters. The chip occupies 29 mm² and dissipates 300 mW     

A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2

A 10-b current steering CMOS digital-to-analog converter (DAC) is described, with optimized performance for frequency domain applications. For sampling frequencies up to 200 MSample/s, the spurious free dynamic range (SFDR) is better than 60 dB for signals from DC to Nyquist. For sampling frequencies up to 400 MSample/s, the SFDR is better than 55 dB for signals from DC to Nyquist. The measured differential nonlinearity and integral nonlinearity are 0.1 least significant bit (LSB) and 0.2 LSB, respectively. The circuit is fabricated in a 0.35-μm, single-poly, four-metal, 3.3 V, standard digital CMOS process and occupies 0.6 mm². When operating at 500 MSample/s, it dissipates 125 mW from a 3.3 V power supply. This DAC is optimized for embedded applications with large amounts of digital circuitry     

A 10-b 20-Msample/s analog-to-digital converter

A 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-μm CMOS technology is described. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies a 8.7 mm² and dissipates 240 mW     

A low-power 8-PAM serial transceiver in 0.5-μm digital CMOS

An 8-PAM CMOS transceiver is described in this paper. Pre-emphasis is implemented without an increase in DAC resolution or digital computation. The receiver oversamples with three fully differential 3-bit ADCs. The prototype transmits at up to 1.3 Gb/s and has a measured bit error rate of less than 1 in 10¹³ for an 810-Mb/s pseudorandom bit sequence transmission. The device, packaged in a 68-pin ceramic leadless chip carrier, is implemented in 0.5-μm digital CMOS, occupies 2 mm², and dissipates 400 mW from a 3.3-V supply     

A new carry-free division algorithm and its application to asingle-chip 1024-b RSA processor

A carry-free division algorithm is described. It is based on the properties of redundant signed digit (RSD) arithmetic to avoid carry propagation and uses the minimum hardware per bit, i.e. one full adder. Its application to a 1024-b RSA (Rivest, Shamir, and Adelman) cryptographic chip is presented. The features of this new algorithm allowed high performance (8 kb/s for 1024-b words) to be obtained for relatively small area and power consumption (80 mm² in a 2-μm CMOS process and 500 mW at 25 MHz)     

A 5-V CMOS line controller with 16-b audio converters

A 5-V CMOS line controller is presented. The circuit was designed using a 2-μm CMOS technology with two layers of polysilicon and two layers of metal. The total circuit area is 15 mm², of which 6.5 mm² is used for converters, 1.6 mm² for the DC feed controller, and 1.5 mm² for the digital interface; the rest is overhead for periphery. Audio converter performances, such as 16-b dynamic range or 15-b A/D linearity, and their stability over process and operating condition variations point out the efficiency and robustness of the selected design techniques. These are a tone-tolerant second-order delta-sigma modulator design, a matching-independent 2-b D/A conversion scheme, a clock-feedthrough compensation technique, and a two-stage amplifier with a noise bandwidth limited by the switches. Converter performances and DC feed controller absolute accuracy and programmability match the new line card design targets and indicate that this circuit is viable for large volume production     

A monolithic 2-b delta-sigma A/D converter

A monolithic 20-b analog-to-digital (A/D) converter using oversampling techniques which is implemented in standard 3-μm CMOS technology is described. The integrated circuit contains a fourth-order delta-sigma modulator and a digital finite-impulse-response filter and decimator. The modulator consists of a continuous-time chopper-stabilized front end, and a switched-capacitor loop filter and comparator. The dynamic range is 123 dB over a DC-to-500-Hz bandwidth, and the signal-to-noise-harmonic-distortion ratio is 126 dB. The chip consumes 125 mW power and has an area of 29.25 mm²     

A 100-MHz CMOS DAC for video-graphic systems

A 6-b weighted-current-sink video digital-to-analog converter (DAC) with 10-90% rise/fall time of 4 ns, integrated with a double-metal 3-μm CMOS technology, is described. Current-source matching, glitch reduction, and differential switch driving aspects are considered. A circuit solution and a nonconventional layout technique yield a high conversion rate with a standard CMOS technology. Experimental results show that a conversion rate of 100 MHz is achievable. The power consumption is 150 mW and the active chip area is 0.5×1.0 mm² . The differential of 0.1 LSB demonstrates that 8 b of accuracy can be achieved. The integral linearity is 0.5 LSB     

A full Nyquist 15 MS/s 8-b differential switched-current A/Dconverter

This paper describes the architecture and circuit design of an experimental 8-b differential 15 MS/s CMOS A/D converter, implemented using the switched-current (SI) technique. Particular emphasis has been given to maintaining analog bandwidth and hence the effective number of bits right across the input Nyquist band. Individual cells have also been optimized for inherent accuracy to achieve good performance in a simple uncorrected conversion algorithm. The converter is fabricated in a standard 0.8 μm 5 V digital CMOS process and occupies 2.4 mm²      

A 10-b 15-MHz CMOS recycling two-step A/D converter

A two-step recycling technique is applied to implement a 10-b CMOS analog-to-digital (A/D) converter with a video conversion rate of 15 Msample/s. In a prototype digitally corrected converter, one capacitor-array multiplying digital-to-analog converter (MDAC) is used repeatedly as a sample-and-hold (S/H) amplifier, a DAC, and a residue amplifier so that the proposed converter may obtain linearity with the capacitor-array matching. An experimental fully differential A/D converter implemented using a double-poly 1-μm CMOS technology consumes 250 mW with a 5-V single supply, and its active die area, including all digital logic and output buffers, is 1.75 mm² (2700 mil²). Because the conversion accuracy of the proposed architecture relies on a capacitor-array MDAC linearity, high-resolution CMOS A/D conversions are feasible at high frequencies if sophisticated circuit techniques are further developed. For high-speed two-phase versions, the system can be easily modified to use multiplexing and/or pipelining techniques with a separate S/H amplifier and/or two separate flash converters     

A 25 Ms/s 8-b-10 Ms/s 10-b CMOS data acquisition IC for digitalstorage oscilloscopes

A data acquisition IC has been developed for digital storage oscilloscopes (DSOs). The entire DSO front-end except an input attenuator was integrated using 1-μm double-poly, double-metal (DPDM) CMOS process technology. In the analog-to-digital conversion, a time-interleaved successive approximation architecture effectively enables both 25 Ms/s 8-b and 10 Ms/s 10-b operation. The input signal conditioner consists of a variable gain amplifier (VGA) and a second-order programmable low-pass filter (LPF) using folded-cascode structures with current feedback circuits. The overall gain is externally controllable from 12 dB to 38 dB, and the bandwidth is programmable at 500 kHz, 5 MHz, and 25 MHz. The chip consumes 340 mW at the 25 Ms/s operating condition and less than 8 mW in the power-down mode from a single 5 V supply     

A single-chip 5-V 2400-b/s modem

A single-chip split-band 2400-b/s modem has been implemented in a 3-μm CMOS process. A high-level of integration results in a low-cost, high-performance modem. Single-ended analog switched-capacitor circuitry and an application-specific digital signal processor (DSP) combine to perform all modem signal processing. The transmit processing is performed almost entirely in the analog domain. The receiver is performed almost entirely in the analog domain. The IC also supports a number of lower-speed (⩽1200 b/s) split-band modem standards. The chip occupies 68.8 mm² and dissipates 120 mW while operating off a single 5-V supply. System and circuit aspects of the design are discussed, and the measured performance of the IC is summarized     

A 14-b 20-Msamples/s CMOS pipelined ADC

The capacitor error-averaging technique, updated with look-ahead decision and digital correction, is used to demonstrate a 14-b 20-Msamples/s pipelined analog-to digital converter (ADC) with no trimming or calibration. The prototype ADC exhibits a differential nonlinearity (DNL) of +0.23/-0.28 least significant bit (LSB), an integral nonlinearity (INL) of +0.95/-1.06 LSB, a spurious-free dynamic range (SFDR) of 91.6 dB, and a signal-to-noise ratio (SNR) of 74.2 dB with a 1-MHz input and a 20-MHz clock. The prototype in 0.5-μm CMOS occupies an area of 4.5×2.4 mm² and consumes 720 mW at 5 V     

A monolithic CMOS 20-b analog-to-digital converter

The authors present a monolithic 20-b analog-to-digital converter (ADC) based on an oversampling feedback architecture. The converter consists of a time-continuous integrator at the input, a pulsewidth modulator in the forward branch of the loop (corresponding to a 10-b ADC), and a 1-b DAC (digital-to-analog converter) to generate the feedback voltage. The digital evaluation is carried out with a uniformly weighted rectangular window filter. The circuit is implemented in a standard 2-μm CMOS n-well process and requires 14 mm² of silicon, including the pads. Measurement results are presented that demonstrate the feasibility of this architecture for 20-b accuracy. The complete circuit has a power consumption of 6.7 mW     

An analog background calibration technique for time-interleavedanalog-to-digital converters

Analog background calibration using adaptive signal processing, an extra channel, and mixed signal integrators matches the offsets and gains of time-interleaved channels in a 10-b 40-Msample/s pipelined analog-to-digital converter. With monolithic background calibration, the peak signal-to-noise-and-distortion ratio is 58 dR, and power dissipation is 650 mW from 5 V. The active area is 47 mm² in 1 μm CMOS     

A 12-b digital-background-calibrated algorithmic ADC with -90-dBTHD

An analog queue-based architecture and an adaptive digital-calibration algorithm calibrate a 12-b algorithmic analog-to-digital converter in the background. At a sampling rate of 125 ksample/s and with monolithic background calibration, the peak signal-to-(noise+distortion) ratio is 71 dB, and the spurious-free dynamic range is 95 dB. The total power dissipation is 16 mW from 5 V. The active area is 5.9 mm² in 1.5-μm CMOS