<100>沟道方向对高迁移率双轴应变硅p-MOSFET的作用

双轴应变技术被证实是一种能同时提高电子和空穴迁移率的颇有前景的方法;<100>沟道方向能有效地提升空穴迁移率.研究了在双轴应变和<100>沟道方向的共同作用下的空穴迁移率.双轴应变通过外延生长弛豫SiGe缓冲层来引入,其中,弛豫SiGe缓冲层作为外延底板,对淀积在其上的硅帽层形成拉伸应力.沟道方向的改变通过在版图上45°旋转器件来实现.这种旋转使得沟道方向在(001)表面硅片上从<110>晶向变成了<100>晶向.对比同是<110>沟道的应变硅pMOS和体硅pMOS,迁移率增益达到了130%;此外,在相同的应变硅pMOS中,沟道方向从<110>到(100)的改变使空穴迁移率最大值提升了30%.讨论和分析了这种双轴应变和沟道方向改变的共同作用下迁移率增强的机理.     

〈100〉沟道方向对高迁移率双轴应变硅p-MOSFET的作用

双轴应变技术被证实是一种能同时提高电子和空穴迁移率的颇有前景的方法;〈100〉沟道方向能有效地提升空穴迁移率. 研究了在双轴应变和〈100〉沟道方向的共同作用下的空穴迁移率. 双轴应变通过外延生长弛豫SiGe缓冲层来引入,其中,弛豫SiGe缓冲层作为外延底板,对淀积在其上的硅帽层形成拉伸应力. 沟道方向的改变通过在版图上45°旋转器件来实现,这种旋转使得沟道方向在(001)表面硅片上从〈110〉晶向变成了〈100〉晶向. 对比同是〈110〉沟道的应变硅pMOS和体硅pMOS,迁移率增益达到了130%;此外,在相同的应变硅pMOS中,沟道方向从〈110〉到〈100〉的改变使空穴迁移率最大值提升了30%. 讨论和分析了这种双轴应变和沟道方向改变的共同作用下迁移率增强的机理.     

p型Si_(1-x)Ge_x应变层中重掺杂禁带窄变的计算

针对应变Si_(1-x)Ge_x的应变致价带分裂和重掺杂对裂值的影响,提出了该合金价带结构的等价有效简并度模型。模型中考虑了非抛物线价带结构。应用这个模型,计算了赝晶生长在<100>Si衬底上的p型Si_(1-x)Ge_x应变层的重掺杂禁带窄变,发现当杂质浓度超过约2～3×10~(19)cm~(-3)后,它在某一Ge组分下得到极大值,而当掺杂低于此浓度时,它则随Ge组分的增加单调下降。与实验报道的对比证实了本模型的有效性。     

采用SiGe虚拟衬底高迁移率应变硅材料的制备和表征

研究了生长在弛豫Si0.79Ge0.21/梯度Si1-xGex/Si虚拟衬底上的应变硅材料的制备和表征,这一结构是由减压外延气相沉积系统制作的.根据双晶X射线衍射计算出固定组分SiGe层的Ge浓度和梯度组分SiGe层的梯度,并由二次离子质谱仪测量验证.由原子力显微术和喇曼光谱测试结果得到应变硅帽层的表面粗糙度均方根和应变度分别为2.36nm和0.83%;穿透位错密度约为4×104cm-2.此外,发现即使经受了高热开销过程,应变硅层的应变仍保持不变.分别在应变硅和无应变的体硅沟道上制作了nMOSFET器件,并对它们进行了测量.相对于同一流程的体硅MOSFET,室温下观测到应变硅器件中电子的低场迁移率显著增强,约为85%.     

掺杂、扩散、离子注入工艺

Y2001-62791-206 0118524应变 Si_(1-x)Ge_x外延层硼扩散模拟=Simulation of Borondiffusion in strained Si_(1-x)Ge_x epitaxial Layers[会,英]/Rajendran,K.& Schoenmaker,W.//2000 IEEE In-ternational Conference on Simulation of SemiconductorProcesses and Devices.—206～209(EC)Y2001-62791-214 0118525应用分子动力学模拟对 SiO_2溅射成品率预测=Pre-diction of SiO_2 sputtering yield using molecular dynamics     

si/Si_(1-x)Ge_x/Si异质结双极晶体管中基区杂质外扩散与未掺杂Si_(1-x)Ge_x结隔离层的影响

研究了Si/Si_(1-x)Ge_x/Si n-p-n异质结双极晶体管(HBT)的结界面处基区杂质外扩散与标定的未掺杂Si_(1-x)Ge_x隔离层的影响。发现,来自重掺杂基区或非突变界面处少量硼的外扩散会在导带中形成寄生势垒,它严重地影响了HBT中集电极电流的提高。未掺杂界面隔离层能消除这些寄生势垒从而极大地提高了集电极电流。     

采用SiGe虚拟衬底高迁移率应变硅材料的制备和表征

研究了生长在弛豫Si0.79Ge0.21/梯度Si1-xGex/Si虚拟衬底上的应变硅材料的制备和表征,这一结构是由减压外延气相沉积系统制作的.根据双晶X射线衍射计算出固定组分SiGe层的Ge浓度和梯度组分SiGe层的梯度,并由二次离子质谱仪测量验证.由原子力显微术和喇曼光谱测试结果得到应变硅帽层的表面粗糙度均方根和应变度分别为2.36nm和0.83%;穿透位错密度约为4×104cm-2.此外,发现即使经受了高热开销过程,应变硅层的应变仍保持不变.分别在应变硅和无应变的体硅沟道上制作了nMOSFET器件,并对它们进行了测量.相对于同一流程的体硅MOSFET,室温下观测到应变硅器件中电子的低场迁移率显著增强,约为85%.     

SiGe层中载流子迁移率研究简况

近些年来的研究结果认为,用Si_(1-x)Ge_x伪晶作成的异质结晶体管是采用硅工艺制作的高速高频器件的最大竞争对手。它的发展速度很快,在很短的时间内就从实验室内的珍品发展成为以硅工艺为基础的速度最快的双极晶体管,不仅设计制成了n-p-n和p-n-p管,而且制成了Si_(1-x)Ge_x伪晶异质结晶体管(PHBT)的集成电路,并获得满意的结果。采用二维漂移扩散(DD)模拟和一维流体学模拟(HD)来分析这类晶体管的高频性能,证明它们的f_r为70GHz左右。     

薄虚拟SiGe衬底上的应变Si pMOSFETs

成功地试制出薄虚拟SiGe衬底上的应变Si pMOSFETs.利用分子束外延技术在100nm低温Si(LT-Si)缓冲层上生长的弛豫虚拟Si0.8Ge0.2衬底可减薄至240nm.低温Si缓冲层用于释放虚拟SiGe衬底的应力,使其应变弛豫.X射线双晶衍射和原子力显微镜测试表明:虚拟SiGe衬底的应变弛豫度为85%,表面平均粗糙度仅为1.02nm.在室温下,应变Si pMOSFETs的最大迁移率达到140cm2/(V·s).器件性能略优于采用几微米厚虚拟SiGe衬底的器件.     

应变Si沟道异质结NMOS晶体管

通过参数调整和工艺简化,制备了应变Si沟道的SiGe NMOS晶体管.该器件利用弛豫SiGe缓冲层上的应变Si层作为导电沟道,相比于体Si器件在1V栅压下电子迁移率最大可提高48.5%.     

Mechanically strained strained-Si NMOSFETs

The drain-current enhancement of the mechanically strained strained-Si NMOSFET device is investigated for the first time. The improvements of the drain current are found to be /spl sim/3.4% and /spl sim/6.5% for the strained-Si and control Si devices, respectively, with the channel length of 25 /spl mu/m at the external biaxial tensile strain of 0.037%, while the drain-current enhancements are /spl sim/2.0% and /spl sim/4.5% for strained-Si and control Si devices, respectively, with the channel length of 0.6 /spl mu/m. Beside the strain caused by lattice mismatch, the mechanical strain can further enhance the current drive of the strained-Si NMOSFET. The strain distribution due to the mechanical stress has different effect on the current enhancement depending on the strain magnitude and channel direction. The smaller current enhancement for strained-Si device as compared to the control device can be explained by the saturation of mobility enhancement at large strain.     

SiGe薄膜材料电阻率与掺杂浓度的关系研究

目前，应变Si1-xGex薄膜材料杂质浓度尚未有准确且简便易行的测试方法。为了快速准确地确定应变Si1-xGex薄膜材料的掺杂浓度，在研究应变Si1-xGex材料多子迁移率模型的基础上，采用Matlab编程模拟仿真，求解并建立了不同Ge组分下应变Si1-xGex薄膜材料掺杂浓度与其电阻率的关系曲线，讨论了轻、重掺杂两种情况下该关系曲线的变化趋势。通过Si1-xGex薄膜材料样品的四探针电阻率测试及电化学C-V掺杂浓度测试的对比实验，对本关系曲线进行了验证。     

SiGe/Si HBT低频噪声特性研究

对Si/Si1-xGexHBT的低频噪声进行了模拟。频率、基极电流、集电极电流、发射极几何尺寸(面积、条长)、Ge组份x、温度等诸多因素都对低频噪声有影响。模拟结果表明,Si/SiGeHBT具有优异的低频噪声特性。     

The role of carbon on performance of strained-Si:C surface channel NMOSFETs

Carbon incorporation in strained-Si surface channel NMOSFET is investigated. Due to the ～52% lattice mismatch between silicon and carbon, the channel is expected to have higher strain than strained-Si, indicating that the carrier mobility can be enhanced significantly. There is a ～40% electron mobility enhancement for incorporated carbon content of 0.25% in strained-Si NMOSFETs compared to unstrained Si channels. The performance of channels with increased strain is not as high as theoretical predictions. This is due to the large D_it at the oxide/strained-Si:C interface and alloy scattering, which degrades carrier mobility enhancement.     

A logic nanotechnology featuring strained-silicon

Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si/sub 1-x/Ge/sub x/ in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSFET. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work: 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies.     

A 90-nm logic technology featuring strained-silicon

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.     

高频大功率SiGe/Si HBT的设计

详细地阐述了高频大功率SiGe/Si异质结双极晶体管(HBT)设计中的一些主要问题,主要包括器件的纵向设计中发射区、基区以及收集区中掺杂浓度、形貌分布、层厚的选择以及横向布局设计中的条宽、间隔的选择等.并对这些主要参数的选择给出了一些实用的建议.     

Advanced SOI p-MOSFETs with strained-Si channel onSiGe-on-insulator substrate fabricated by SIMOX technology

We have newly developed an advanced SOI p-MOSFET with strained-Si channel on insulator (strained-SOI) structure fabricated by SIMOX (separation-by-implanted-oxygen) technology. The characteristics of this strained-SOI substrate and electrical properties of strained-SOI MOSFETs have been experimentally studied. Using strained-Si/relaxed-SiGe epitaxy technology and usual SIMOX process, we have successfully formed the layered structure of fully-strained-Si (20 nm)/fully-relaxed-SiGe film (290 nm) on uniform buried oxide layer (85 nm) inside SiGe layer. Good drain current characteristics have been obtained in strained-SOI MOSFETs. It is found that the hole mobility is enhanced in strained-SOI p-MOSFETs, compared to the universal hole mobility in an inversion layer and the mobility of control SOI p-MOSFETs. The enhancement of the drive current has been kept constant down to 0.3 μm of the effective channel length     

A physically based analytical model for the threshold voltage of strained-Si n-MOSFETs

A physically based analytic model for the threshold voltage V/sub t/ of long-channel strained-Si--Si/sub 1-x/Ge/sub x/ n-MOSFETs is presented and confirmed using numerical simulations for a wide range of channel doping concentration, gate-oxide thicknesses, and strained-Si layer thicknesses. The threshold voltage is sensitive to both the electron affinity and bandgap of the strained-Si cap material and the relaxed-Si/sub 1-x/Ge/sub x/ substrate. It is shown that the threshold voltage difference between strained- and unstrained-Si devices increases with channel doping, but that the increase is mitigated by gate oxide thickness reduction. Strained Si devices with constant, high channel doping have a threshold voltage difference that is sensitive to Si cap thickness, for thicknesses below the equilibrium critical thickness for strain relaxation.     

SiGe/Si HBT高频噪声特性研究

基于器件Y参数,对Si/Si1-xGexHBT的高频噪声进行了模拟。Si/Si1-xGexHBT的高频最小噪声系数随Ge组份x的增加而减小。与Si BJT相比,Si/SiGe HBT具有优异的高频噪声特性。