基于LEON2处理器的SoC设计

SoC已逐渐成为集成电路设计的主流发展趋势,而其中的微处理器部分尤为重要.选用LEON2处理器核,是一款可合成的VHDL模型,是基于SPARC V8结构的32位处理器,具有高度的可配置性,尤其适用于SoC设计,设计者可为其特定应用选择不同的外围设备IP核.本文介绍了LEON2处理器核的基本特征及其外围设备的IP核,主要讨论了基于LEON2处理器的SoC设计.     

SoC设计链中的可配置IP

本文简要介绍了SoC设计链面临的挑战以及对可配置IP提出的新的要求。重点分析了如何利用Improv系统公司开发的VLIW架构和包括Jazz DSP平台的工具套件进行快速、低成本、高性能的终端设计。[编者按]     

可配置处理器在SoC设计中的应用

可配置处理器的出现使得SoC设计工程师可以建立起一种崭新的,而且非常灵活的硬件模块构建方法。同传统的固定指令集架构ISA处理器相比,可配置处理器通过添加用户定制的执行功能部件、寄存器和寄存器堆以及专用通信接口能够获得很高的系统性能。     

SiBEAM选择Tensilica可配置处理器IP核

Tensilica公司日前宣布，开发领先的毫米波解决方案和高速无线通信平台的SiBEAM公司选择了Xtensa可配置处理器IP核进行芯片设计项目。Xtensa处理器IP核为他们提供了选择框和下拉式菜单选项，使其可根据需要配置相应功能。另外，设计工程师能够添加多周期执行单元、寄存器文件或者更多的功能以优化指令，使其更符合应用的要求。     

SoC设计链中的可配置IP

本文简要介绍了SoC设计链面临的挑战以及对可配置IP提出的新的要求。重点分析了如何利用Improv系统公司开发的VLIW架构和包括Jazz DSP平台的工具套件进行快速、低成本、高性能的终端设计。     

开放核协议--IP核在SoC设计中的接口技术

本文介绍了IP核的概念及其在SoC设计中的应用，讨论了为提高IP核的复用能力而采用的IP核与系统的接口技术。     

可配置系统级验证环境加速SoC开发

利用嵌入式硅IP可以缩短SoC设计所需的开发时间，这已成为众所公认的事实。但要从完工后的整个系统角度出发，整合及验证来自多家厂商的元件，需要相当的时间和努力，然而它们却常被忽略。这会对嵌入式软件开发人员造成额外负担，因为他们需要SoC的外围和接口以及处理器的精确模型，才能     

MIPS科技改变SoC的IP模式

在收购模拟和混合信号IP供应商Chipidea公司后,MIPS科技现已成为全球第二大半导体设计IP公司和全球第一大模拟IP公司。通过此次收购,MIPS可以为客户提供强大的处理器IP及丰富的模拟IP,以加快新一代的SoC设计。     

基于可配置架构的数据域处理器设计

在过去几年中,设计平台正向着提供高性能、多功能产品且能在快速更替中推向市场这一方向持续演变。在所有市场上,消费者正倾向于选择功能丰富的产品。在寻求进一步个性差异的公司产品中,高端的音频、图像与视频质量逐渐融合进来。     

IP核工具合作——勾画可配置处理器“燎原”路线图

任何新技术的产生和推广都有其驱动力所在, "渐行渐近"的可配置处理器也是如此.市场方面,随着竞争压力的日益增加,产品个性化和上市时间的需求越来越严格,产品方面,随着制造商对性能,功能,功耗、成本日益苛刻的要求,通用的硬IP核已无法完全满足其产品设计要求;宣传方面,随着可配置处理器IP供应商在全球尤其是在中国市场的积极宣传,可配置处理器的概念已经逐步深入人心.     

SoC可重配置处理器平台

随着供应商的功能强劲多处 理器和并行处理器解决方案的不断发布,一个基于平台设计的潮流正在日益高涨。就在最近,几个供应商发布了尚未完全包装的解决方案,其中某些产品还配置了构建有竞争力SoC(系统级芯片）所必需的全部硬件与软件。2000年10月,一家致力于多处理器平台并处于起步阶段的公司Improv Systems推出了首款专用产品-Acappella,一个基于该公司PSA(可编程系统结构)与Jazz处理器结构的VoP(分组语音传输)解决方案。Jazz处理器是一个既可配置又能编程的VLIW(甚长指令字)处理器。Philips是Acappella包的第一位用户。该方…     

多核CPU在HDTV SoC上的实现

以多核CPU在HDTV SoC上的应用为例,简述了HDTV SoC的功能模块划分.探讨了以同核异构方式互连的CPU之间的通信问题,同时还介绍了以此结构为基础的一次完整CPU通信过程.     

SOC设计面对的技术挑战

片上系统设计技术作为当今超大规模集成电路的发展趋势,是21世纪集成电路技术的主流,但是这种新技术的产生面临着一些设计问题和挑战。本文介绍了SOC的主要设计技术,并阐述了SOC设计中存在的一些技术挑战等。     

Design of a system software based on a Java SoC processor

Java technology is spreading rapidly all over the world in recent years. It is a popular application development language for its well-encapsulation, platform-independent and high security. There are great amounts of Java games and other gadgets on mobile platforms, as well as on set-up-box systems. As Java applications become more sophisticated, the Java Virtual Machine (JVM) middle-wares in embedded systems are not satisfying, Java-specific chips extend in the market. All existing Java-based system software or Operating System (OS) are used on JVM, they cannot be used on Java processors. It is important to develop a pure Java system software or OS so that embedded systems using Java processors will have great performance in Java applications. This paper presents a set of system software designed for a Java-specified processor VP6K, which is also a System-on-Chip (SoC). This system software includes real-time multitask dispatching, file management, device management, hardware drivers, and infrastructural Application Programming Interface (APIs). According to experimental results, the system software provides interfaces for Java programs to fully handle CPU resource, so that all applications can be executed properly and efficiently. VP6K embedded platform shows its good performance for Java applications when the system software is implemented.     

浅谈SoC 设计中的软硬件协同设计技术

集成电路制造技术的迅速发展已经可以把一个完整的电子系统集成到一个芯片上即所谓的系统级芯片（System-on-chip,简称SoC)，传统的设计方法是将硬件和软件分开来设计的，在硬件设计完成并生产出样片后才能调试软件，本文介绍了针对于系统级芯片设计的软硬件协同设计技术（co-design)的概念和设计流程，同时借鉴实际设计经验讨论了软硬件协同设计中所需注意的技术问题。     

Automatic DC operating point computation and design plan generation for analog IPs

DC operating point computation is inescapable for both knowledge-based and simulation-based analog synthesis. In this perspective, this article presents the automatic computation of DC operating point and the?generation of suitable design plans for analog IPs. The analog IP is built as a hierarchy of subcircuits inside our dedicated framework CAIRO+. Leaf subcircuits are known as devices and higher-level subcircuits are known as modules. Each subcircuit is represented by a dependency graph. The?dependency graph expresses electrical dependencies of circuit parameters on a selected set of design parameters. The dependency graph of the analog IP is constructed, in a hierarchical bottom-up approach, by merging graphs of children devices and modules. The graph is converted to a directed acyclic graph (DAG) by detecting and removing existing directed cycles. The resulting DAG is the design plan for the analog IP. Upon construction, the DAG is executed, in a top-down approach, to compute the DC operating point and the dimensions of the transistors. The computed DC operating point is compared to a DC simulation to ensure its correctness. The proposed methodology has been successfully applied to size and bias two analog IPs: a single-ended two-stage operational amplifier and a?differential cascode current-mode integrator. The results prove the efficiency and accuracy of the proposed methodology.     

可编程单片系统将成为Cypress公司另一市场亮点

为了消除公司目标与数据通信市场所能提供的收入之间的差距,Cypress决定在数字通信之外的其它高速成长的市场增加投资,Cypress公司的子公司微系统公司(CMS)的PSoC产品(可编程单片系统)将成为Cypress开辟另一市场的主打产品。 Cypress微系统公司是专为消费类产品、工业、办公自动化、电信和汽车领域应用提供大量具有嵌入式控制功能的高性能现场可编程单片系统器件的公     

Multiprocessor SoC design methods and tools

With the continuous evolution of semiconductor process technology, it is now possible to integrate tens or hundreds of processors in a single chip and make an multiprocessor systems-on-chip (MPSoC), or a multicore platform. There are many dual or quad-core CPUs and 100+-core graphics processing units (GPUs) on the desktop computer market, and many MPSoC solutions are also in the embedded computing markets. A key benefit of multicore platforms is scalability in performance and power.     

Low-power network-on-chip for high-performance SoC design

An energy-efficient network-on-chip (NoC) is presented for possible application to high-performance system-on-chip (SoC) design. It incorporates heterogeneous intellectual properties (IPs) such as multiple RISCs and SRAMs, a reconfigurable logic array, an off-chip gateway, and a 1.6-GHz phase-locked loop (PLL). Its hierarchically-star-connected on-chip network provides the integrated IPs, which operate at different clock frequencies, with packet-switched serial-communication infrastructure. Various low-power techniques such as low-swing signaling, partially activated crossbar, serial link coding, and clock frequency scaling are devised, and applied to achieve the power-efficient on-chip communications. The 5 /spl times/5 mm/sup 2/ chip containing all the above features is fabricated by 0.18-/spl mu/m CMOS process and successfully measured and demonstrated on a system evaluation board where multimedia applications run. The fabricated chip can deliver 11.2-GB/s aggregated bandwidth at 1.6-GHz signaling frequency. The chip consumes 160 mW and the on-chip network dissipates less than 51 mW.