Tunneling-assisted IMPATT operation

The influence of tunneling on the efficiency of millimeter-wave IMPATT diodes is investigated. For a reliable estimation of this influence, the tunnel generation rate coefficients are measured from silicon p-i-n diodes. The Read equation is solved taking a time-dependent tunnel current into account. The phase distortion, which is responsible for the efficiency degradation caused by tunneling, is calculated analytically and numerically. It is shown that for an exact solution the injected current density should be calculated numerically. The results suggest that for efficient silicon IMPATT diode operation, the maximum electric field should be below 1×10⁶ V/cm. Due to the current and field dependent representation of the injection phase, there are direct consequences on the design of millimeter- and submillimeter-wave transit time diodes for high power generation as well as for low-noise operation     

Extraction and evolution of Fowler-Nordheim tunneling parameters of thin gate oxides under EEPROM-like dynamic degradation

A new method is presented for the extraction of the Fowler-Nordheim (FN) tunneling parameters of thin gate oxides from experimental current-voltage characteristics of Metal-Oxide-Semiconductor (MOS) capacitors. In this technique, the classical low temperature FN current model is considered but an improved numerical procedure has been implemented for the calculation of the oxide electric field — gate voltage relationship. It is shown that this iterative method leads to an excellent fit of experimental data with theoretical curves for both p-type and n-type substrates, even in the case of high doping levels. The procedure allows the determination of both FN tunneling parameters and potential barrier heights at silicon and polysilicon interfaces with a systematic estimation of the statistical fitting errors on each parameter. It is applied here to the study of the variations of the FN tunneling parameters of thin oxides submitted to EEPROM-like dynamic degradation.     

Tunneling in a metal-semiconductor-semiconductor thin-film diode

By incorporation of a thin layer of near intrinsic semiconductor, one can change a metal-semiconductor ohmic contact into a retifying junction. This concept is demonstrated by inserting an amorphous silicon film of less than 40 A between aluminum and silicon. The resulting diode's forward current is found to be controlled by majority carrier tunneling, and its reverse current is governed by minority carrier diffusion. From experimental data of I-V and C-V measurements, we find a flat-band condition at zero bias and deduce a tunneling barrier height of 0.67 eV at room temperature. The energy band diagram is presented to illustrate the operation principle of the tunnel diode.     

Mechanism of oxide thickness and temperature dependent current conduction in n+-polySi/SiO2/p-Si structures — a new analysis

The conduction mechanism of gate leakage current through thermally grown silicon dioxide (SiO₂) films on (100) p-type silicon has been investigated in detail under negative bias on the degenerately doped n-type polysilicon (n⁺-polySi) gate. The analysis utilizes the measured gate current density J_G at high oxide fields E_ox in 5.4 to 12 nm thick SiO₂ films between 25 and 300℃. The leakage current measured up to 300℃ was due to Fowler–Nordheim (FN) tunneling of electrons from the accumulated n⁺-polySi gate in conjunction with Poole Frenkel (PF) emission of trapped-electrons from the electron traps located at energy levels ranging from 0.6 to 1.12 eV (depending on the oxide thickness) below the SiO₂ conduction band (CB). It was observed that PF emission current I_PF dominates FN electron tunneling current I_FN at oxide electric fields E_ox between 6 and 10 MV/cm and throughout the temperature range studied here. Understanding of the mechanism of leakage current conduction through SiO₂ films plays a crucial role in simulation of time-dependent dielectric breakdown (TDDB) of metaloxide–semiconductor (MOS) devices and to precisely predict the normal operating field or applied gate voltage for lifetime projection of the MOS integrated circuits.     

Thin active layer a-Si:H thin-film transistors

We show that hydrogenated amorphous silicon thin-film transistors (TFT's) with active layer thickness less than 50 nm have improved performance for display applications. Using two-dimensional (2-D) modeling, we find previously observed degradation for thin active layers is due to electric field effects in the contact regions of staggered inverted devices and affects only the saturation characteristics; linear region performance actually improves with decreasing thickness. We have fabricated devices with extremely thin active layer (10 nm), and indeed find excellent linear region characteristics. In addition, direct tunneling across the undoped regions at device contacts reduces electric field effects, resulting in excellent saturation region characteristics, and gate-induced channel accumulation reduces the Schottky barrier width at direct metal contacts so that even devices without doped contact regions (i.e., tunneling contacts) are possible     

金属—氮氧化硅—硅电容在本征击穿前的漏电特性

本文的实验结果表明，从６ＭＶ／ｃｍ到１４ＭＶ／ｃｍ的外加电场范围内，在氮氧化硅膜的漏电机理与常规方法生长的氧化硅的不同，氮氧化硅膜漏电机理可分为三种，当电小于８ＭＶ／ｃｍ时，漏电是由于注入电子的直接隧穿填充绝缘体中的浅陷阱而引起的。在高场范围（＞１０ＭＶ／ｃｍ）Ｆｏｗｌｅｒ－Ｎｏｒｄｈｅｉｍ（ＦＮ）效应占支配地位。这些机理与介质膜的制备条件有关。在中等电场区域，注入电子能通过ＦＮ电流和直接隧穿到达     

Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET

This paper present, the modeling and estimation of edge direct tunneling current of metal gate (Hf/AlN_x) symmetric double gate MOSFET with an intrinsic silicon channel. To model this leakage current, we use the surface potential model obtained from 2D analytical potential model for double gate MOSFET. The surface potential model is used to evaluate the electric field across the insulator layer hence edge direct tunneling current. Further, we have modeled and estimated the edge direct tunneling leakage current for high-k dielectric. In this paper, from our analysis, it is found that dual metal gate (Hf/AlN_x) material offer the optimum leakage currents and improve the performance of the device. This feature of the device can be utilized in low power and high performance circuits and systems.     

A simple technique to determine barrier height change in gate oxide caused by electrical stress

Charge trapping in the gate oxide and at the interfaces caused by electrical stress may lead to changes of both the oxide field and the shape of tunneling barrier. In this study, a simple technique based on the analysis of a small change in the Fowler-Nordheim (FN) tunneling current has been developed to quantitatively examine the changes of the effective barrier height and the electric field at the tunneling interface. A power-law dependence of the changes of both the barrier height and the electric field on the stress time is observed.     

First-principles study of the effects of oxygen vacancy on hole tunneling current

The effects of oxygen vacancies on the electronic structure of silicon dioxide and the hole tunneling current were investigated using first-principles calculations. A level related to oxygen vacancy was obtained to be nearly 2.0 eV from the top of valence band within the bandgap of the α-quartz supercell with one oxygen vacancy. And therefore the defect assisted hole (electron) tunneling currents were calculated. The results shows that the hole tunneling current will be dominant for a thinner oxide thickness at low oxide field and the contribution of trap assisted hole tunneling to the total tunneling current decreases with oxide thickness and oxide field increasing. It is concluded that the effects of the oxygen vacancies on the hole tunneling current become smaller with larger oxide thickness and higher electric field.     

GaN基肖特基势垒二极管的漏电流传输与退化机制

通过比较反向偏压下AlGaN/GaN异质结肖特基势垒二极管(SBD)和GaN SBD的电流特性、电场分布和光发射位置,研究了GaN基SBD的漏电流传输与退化机制。结果表明,AlGaN/GaN SBD退化前后漏电流均由Frenkel-Poole(FP)发射机制主导,而GaN SBD低场下为FP发射电流,高场下则为Fowler-Nordheim(FN)隧穿电流。电场模拟和光发射测试结果表明,引起退化的主要原因是高电场,由于结构不同,两种SBD的退化机制和退化位置并不相同。根据实验结果,提出了一种高场FN隧穿退化模型,该模型强调应力后三角势垒变薄导致FN隧穿增强是GaN SBD退化的内在机制。     

Tunneling into interface states as reliability monitor for ultrathin oxides

This paper reports experimental data and simulations of low-voltage tunneling in ultrathin oxide MOS devices. When the substrate is very heavily doped, a thermionic barrier is present that opposes the direct tunneling of gate electrons when the applied gate voltage is between 0 V and the flatband voltage. In such conditions, we show that the measured gate current cannot be explained by direct tunneling, but features an additional, dominant component. The temperature dependence of this extra component indicates that it is due to gate electrons tunneling into the anode interface states. By comparing measurements and simulations, it is possible to exploit this extra current to estimate the interface state density within the silicon band gap. In addition, it is shown that this tunneling current component is very sensitive to electrical stress and allows a clear detection of oxide wear out even for stress at very low field. Therefore, it can be adopted as monitor of oxide degradation in ultrathin oxides where the traditional stress induced leakage current due to bulk-oxide traps is not detectable.     

Amorphous-crystalline silicon heterojunction: Theoretical studies of the dark current and spectral response

All the terms contributing to the dark current for an n-amorphous/p-crystalline silicon heterojunction have been evaluated. The abrupt heterojunction model with the presence of interface states has been adopted and flat quasi-Fermi levels have been assumed across both depletion regions. The gap density of states in amorphous silicon has been approximated by a V-distribution. The dominant current mechanisms at forward and reverse biases have been determined and the zero-bias spectral response has been calculated.     

Low-pressure chemical-vapor-deposited silicon-rich oxides fornonvolatile memory applications

The electrical and reliability characteristics of ultrathin nonstoichiometric silicon oxide (SiO_x, x<2) films deposited by the low-pressure chemical vapor deposition (LPCVD) technique using silane and nitrous oxide were studied. It has been found that these oxides exhibit enhanced current conduction at low electric field for both voltage polarities due to reduced conduction barrier height and a conduction mechanism that involves direct tunneling between dispersed silicon crystallites in the oxide. The current characteristics are controlled by adjusting the SiH₄/N₂O gas ratio. These nonstoichiometric films exhibit lower charge trapping, have an extremely large charge to breakdown, and there is negligible interface state generation in comparison to ultrathin thermal oxides. The results indicate that these highly reliable dielectrics can be promising candidates for nonvolatile memory applications     

A 2-dimensional fully analytical model for design of high voltage junction barrier Schottky (JBS) diodes

A physics-based closed form analytical model for the reverse leakage current of a high voltage junction barrier Schottky (JBS) diode is developed and shown to agree with experimental results. Maximum electric field “seen” by the Schottky contact is calculated from first principles by a 2-dimensional method as a function of JBS diode design parameters and confirmed by numerical simulations. Considering thermionic emission under image force barrier lowering and quantum mechanical tunneling, electric field at the Schottky contact is then related to reverse current. In combination with previously reported forward current and resistance models, this gives a complete I-V relationship for the JBS diode. A layout of interdigitated stripes of P-N and Schottky contacts at the anode is compared theoretically with a honeycomb layout and the 2-D model is extended to the 3-D honeycomb structure. Although simulation and experimental results from 4H-Silicon Carbide (SiC) diodes are used to validate it, the model itself is applicable to all JBS diodes.     

Compact LDD nMOSFET degradation model

In this paper, we present a compact degraded I-V model for submicron lightly-doped drain (LDD) MOSFET's. The analytical and physics-based model was developed using the drift equation and considering the nonuniform spatial hot-carrier-induced interface states and the detailed LDD structure. It can be used to calculate fresh channel electric field and drain current by turning off the effect of hot-carrier-induced interface states. Using the fresh electric field in conjunction with a simplified energy balance equation, the nonuniform spatial distribution of induced interface states ran be calculated. By incorporating this distribution into the degraded current model, we can describe the damaged I-V characteristics and channel electric fields as a function of stress time. The model includes the effects of series resistances and carrier velocity saturation. It can be used to calculate time-dependent degraded drain current, and is a time-saving CAD model     

Current transport in boeing (Cd, Zn)/CuInSe2solar cells

The current versus voltage (I-V) and capacitance characteristics of Boeing (Cd, Zn)S/CuInSe2solar cells are investigated and a model for the current transport is proposed. The current transport appears to involve tunneling and interface recombination in series. A mathematical model for current transport is formulated as a linear transition between the well known tunneling and interface recombination transport equations. This model is found to explain observed I-V characteristics under various temperature and illumination conditions. In particular, the nontranslation of the I-V characteristics from dark to illuminated conditions and the temperature dependences of the diode factor and the reverse saturation current can be explained. In addition, capacitance analyses have corroborated assumptions concerning the band structure and have provided independent demonstration of tunneling transport.     

Modeling of the I–V characteristics of high-field stressed MOS structures using a Fowler–Nordheim-type tunneling expression

The gate current–voltage characteristic of a high-field stressed metal-oxide-semiconductor structure with trapped charge within the insulator barrier is consistent with a Fowler–Nordheim-type tunneling expression. Instead of considering a correction for the cathode electric field as usual, we use an effective local electric field that takes into account the distortion of the oxide conduction band profile caused by the trapped charge. An energy level at the injecting interface, introduced as an optimization parameter of the model, controls the tunneling distance used for calculating the effective field. Trap generation in the oxide is induced by high-field constant current stress and subsequent electron trapping at different injection levels is monitored by measuring the associated flat band voltage shift. The model applies for positive gate injection regardless the stress polarity and the involved parameters are obtained by fitting the experimental data without invoking any particular theoretical model for the trapping dynamics. In addition, it is shown how the presented model accounts for consistently both the current–voltage and voltage–current characteristics as a function of the injected charge through the oxide.     

温度和电场对a-SiC; H TFLED发光亮度的影响

通过载流子注入和复合输运模型 ,分析比较了温度和电场对 pin注入型非晶硅碳薄膜发光二极管 (a -SiC :HTFLED)发光亮度的影响。分析表明发光有源i层内大电场尤其是大电流引起的高温度决定着大电流下二极管的发光亮度。     

Base current relaxation transient in reverse emitter-base biasstressed silicon bipolar junction transistors

The base current relaxation transient following reverse emitter-base (EB) bias stress and its effect on time-to-failure (TTF) determination are examined in self-aligned and nonself-aligned silicon bipolar junction transistors (BJTs) with thermal and deposited base oxide. A quantitative model indicates that the transient is due to a reduction of the stress-generated positive charge trapped in the oxide layer near the emitter-base junction due to holes tunneling from oxide hole traps to silicon band states or SiO₂/Si interface traps. The neutral oxide hole traps may be quickly recharged through hole tunneling or hole injection into the oxide during further reverse-bias stress. A delay time of ~10^-3 s was observed after the termination of stress before base current relaxation begins, which affects the extraction of the ac operation TTF from dc stress measurements     

Observation of very high peak-to-valley current ratio (⩾9.4) inamorphous silicon/silicon-carbide double barrier structure with barrierenhancement layer

A negative differential resistance current/voltage (I/V) curve with a very high peak-to-valley current (PTV) ratio (⩾9.4) has been obtained in the a-Si:H/a-SiC:H double barrier structure with added amorphous silicon barrier enhancement layers. Although similar phenomena have been reported in the crystalline AlGaAs/GaAs double barrier diodes, the effect of the added barrier enhancement layers on the PTV ratio is not so significant as the amorphous silicon. A primary model is proposed to explain this anomalous result. Based on the model, the parameters to lower the leakage current and enhance the resonant tunneling current are suggested