Linear control of inverter output voltage in overmodulation

A novel overmodulation strategy for space-vector pulsewidth modulated (PWM) inverters is proposed. The method, which increases the range of linear control of the output voltage by 10%, is based on Fourier series representation of the reference voltage     

数字调制信号开环解调的DSP实现

随着微电子技术和计算技术的发展，尤其是DSP处理速度的提高，解调器的全数字化实现已成为现实。重点讨论了软件无线电中数字调制信号解调的DSP实现方案。     

Multiprocessor implementation of real-time DSP algorithms

In this paper, we consider multiprocessor implementation of real-time recursive digital signal processing algorithms. The objective is to devise a periodic schedule, and a fully static task assignment scheme to meet the desired throughput rate while minimizing the number of processors. Toward this goal, we propose a notion called cutoff time. We prove that the minimum-processor schedule can be found within a finite time interval bounded by the cutoff time. As such the complexity of the scheduling algorithm and the allocation algorithm can be significantly reduced. Next, taking advantage of the cutoff time, we derive efficient heuristic algorithms which promise better performance and less computation complexity compared to other existing algorithms. Extensive benchmark examples are tested which yield most encouraging results     

一种输出电压可调带隙基准源设计

设计了一种输出电压可调的带隙基准源,其基于TSMC 0.18μm工艺,采用Cadence进行仿真验证。仿真结果显示,带隙基准源电压源在–25~+100℃内,温度系数为29×10–6/℃,电源抑制比PRSS在低频下为63 d B。在1.8 V的电源工作电压下,其输出电压为750 m V,电压可调节范围约20%,即从600 m V至900 m V,其输出电压可调的特性,使得其使用范围扩大。     

基于DSP开发系统设计与实现

为了设计一个性能稳定的DSP开发系统,利用TI公司最新推出的TMS320F28335作为微处理器,该芯片为32位浮点型DSP。在采用浮点DSP设计系统时,不需要考虑处理的动态范围和精度,比定点DSP在软件编写方面更容易,更适合采用高级语言编程。外围电路主要包含电源电路、RAM扩展电路、晶振电路和复位电路,用来辅助DSP的工作。利用电源管理芯片设计电源电路,可以有效解决其他型号的DSP对上电顺序的要求;扩展的外部RAM可以使程序的调试与下载更加方便。利用外部时钟源作为时钟输入,使其输入时钟更加稳定的同时,也可为具有相同时钟的多个DSP使用。利用三端监控芯片来实现系统的手动复位和自动复位,使系统的稳定性大大提高。     

DSP指令集仿真器的设计与实现

介绍几种常用的仿真器的设计方案,通过比较分析各自原理的优缺点,结合硬件性能,设计了基于ZWFcore的指令集仿真器ZWISS。通过对其CPU、多级存储单元、陷阱、内存管理单元（MMU）、存储保护系统（MPS）以及物理内存属性（PMA）的仿真,较完善地完成对ZWFcore的仿真。为DSP硬件评估、DSP算法实现提供了良好的软件模拟平台。     

基于DSP的FQPSK/CEFQPSK调制器实现

首先介绍了适用于深空通信的费赫尔正交移相键控（FQPSK）调制技术。为了改善其包络起伏特性,又介绍了一种严格的恒包络调制技术——恒包络正交移相键控（CEFQPSK）,它不但保持了FQPSK较高的带宽效率、无干扰和抖动的优点,而且实现了严格的恒包络,能够将发射机射频功率放大器效率发挥到最大。最后采用了一系列简化运算的处理方法,在TI公司的DSP中实现了这2种调制,达到信号高速输出的目的。     

动态控制开关稳压器的输出电压

随着半导体行业遵循摩尔定律不断发展,处理器对电源的需求也正以惊人的速率在增长。在电源管理至关重要的电池供电应用中,处理器会根据时钟速率的增加或减少,调节其相应的内核工作电压,从而在需要高速处理的时候全功率供电,在处理器空闲的时候避免浪费剩余功率。但是,为处理器寻找有控制输出电压功能的开关稳压器集成电路（IC）是很困难的,而且价格通常比普通的开关稳压器高很多。     

基于DSP Builder的数字滤波器设计与实现

现场可编程门阵列（FPGA）器件广泛用于数字信号处理领域,而使用VHDL或VerilogHDL语言进行设计比较复杂。提出一种采用FDATOOL工具和DSP Builder实现FIR滤波器的设计方案,按照MATLAB/Simulink/DSP Builder/QuartusII设计流程,使用FDATOOL工具可以实时调整滤波器的参数,采用DSP Builder设计了一个16阶FIR低通滤波器模型,并完成了仿真与验证,将模型转换生成VHDL代码,实现了基于FPGA的数字滤波器的设计。结果表明,该方法简单易行,易修改与移植,可满足设计要求,它验证了采用DSP Builder实现数字滤波器设计的独特优势。     

Inverter output voltage synthesis using novel dead timecompensation

In this paper, a novel dead time compensation method is presented that produces inverter output voltages equal to reference voltages. An experimental result is also presented to demonstrate the validity of the proposed method. It shows that the compensation of the dead time is possible up to a sub-microsecond range. Also, the reference voltage can be used as a feedback value, which is essential for sensorless vector control and flux estimation. The method is based on space vector pulsewidth modulation (PWM) strategy and it can be carried out automatically by an inverter controller for initial setup without any extra hardware     

Frequency/voltage convertor with low output ripple

A circuit is desdribed which performs linear frequency-to-voltage conversion with nominally zero output ripple and, at one frequency, ideal step response. This is in contrast to conventional convertors which have large output ripple, the removal of which necessarily produces slow response.     

CMOS micro-power output stage for integrated voltage references

A CMOS micro-power, class-AB output stage with high current-drive capability for integrated voltage references is presented. A weak-inversion MOS translinear-loop ensures that the harmonic mean of the push and pull currents equals a constant bias current. It can source/sink 20 mA with only 15 /spl mu/A quiescent current, thus achieving very high power efficiency. It operates from a 2.5 V power supply and is stable for capacitive loads up to 2 nF.     

Single-stage single-switch PFC converter with low output voltage

A new type of single-stage single-switch converter with low output voltage and power factor correction is proposed. The lower turns ratio for the isolation transformer is the main feature. The proposed converter is suitable for designing high efficiency, high power factor and low cost power supplies for new generation high-speed integrated circuits     

Enhancing output voltage swing in low-voltage micro-power OTA using self-cascode

It is shown how a self-cascode configuration can be profitably used in a micro-power operational transconductance amplifier (OTA), to enhance the output voltage swing, which eventually results in a power consumption reduction. A practical design example is proposed and used in order to discuss and quantify the circuit performance.     

三端集成稳压器扩流方法分析

以LM317K进行电流扩展为例介绍了三端集成稳压器的3种扩流方法,即晶体管扩流、电阻扩流和并联扩流。通过扩流解决了三端集成稳压器输出电流由于受限而不能满足设计要求的问题。给出了3种扩流方法的具体电路连接及原理分析。对LM317K设计的不同方案的扩流电路均使用Multisim V10软件进行了仿真,从仿真结果可以看出3种扩流方法的可行性和正确性。通过对3种扩流方法的分析和比较,给出了各自适用的场合和使用的注意事项。在实际应用中,可根据扩流的大小和使用的三端集成稳压器的型号来选择合适的扩流方法。     

Viterbi译码在TD-SCDMA测试平台中的应用

根据3GPP的规定提出了TD-SCDMA网络测试平台中的Viterbi译码器的DSP实现方案。该方案兼顾了资源消耗和译码效率,提高了译码器的硬件结构和整体性能.通过对TD-SCDMA终端维特比译码的理解,设计出相应网络测试平台中的译码器。并给出了其DSP实现程序,利用CCS集成环境平台和TMS320C55XDSP芯片进行仿真分析。由仿真和测试结果表明,该实现方法在实际应用中检测效果很好。     

Modeling of voltage output charge-pump phase frequency detector in tuning loops

Resonant inverters mostly employ tuning loops based on a phase-locked-loop (PLL) circuit. Some commercially available PLL chips, frequently used in this application, include a voltage output charge-pump phase frequency detector (CP/PFD) rather than well-known current output CP/PFD, which complicates the analysis of the loop. We present a new model for voltage output CP/PFD and an analysis of a tuning loop using this model. The proposed model employs the resistance multiplication approach, which is applicable for the circuits containing periodically operated switches. It is shown that a voltage output CP/PFD in conjunction with a simple RC low-pass filter can be modeled using a dc voltage source, a phase error controlled resistor, and a capacitor. The theoretical study is verified by experimental results.     

多路高压放大器输出直流电压监测与显示系统设计

在自适应光学系统中,自适应控制器AD输出控制信号需要通过高压放大器放大成高压电驱动压电陶瓷变形镜,从而实现波前实时校正.在实际系统中,往往需要对高压放大器输出电压进行实时监测.本系统采用小体积单片机C8051F310作为控制器,采用专用电表芯片CS5460A作为核心测量芯片,实现了单板对20路0～500 V直流电压的实时监测与显示,线性度优于0.2％.     

Low supply voltage high-performance CMOS current mirror with low input and output voltage requirements

This paper presents a scheme for the efficient implementation of a low supply voltage continuous-time high-performance CMOS current mirror with low input and output voltage requirements. This circuit combines a shunt input feedback and a regulated cascode output stage to achieve low input resistance and very high output resistance. It can be used as a high-precision current mirror in analog and mixed signal circuits with a power supply close to a transistor's threshold voltage. The proposed current mirror has been simulated and a bandwidth of 40 MHz has been obtained. An experimental chip prototype has been sent for fabrication and has been experimentally verified, obtaining 0.15-V input-output voltage requirements, 100-/spl Omega/ input resistance, and more than 200-M/spl Omega/ (G/spl Omega/ ideally) output resistance with a 1.2-V supply in a standard CMOS technology.     

改进的图像增强算法及DSP实现

文中基于图像增强方法及其实现进行了研究。首先阐述了传统的直方图均衡化方法存在的问题．进而提出了改进的自适应直方图均衡化图像增强算法。采用空闲灰度级动态分配的自适应直方图均衡化增强算法,并将该算法移植到本文搭建的DSP硬件实验平台上进行验证,实验表明,该算法显著的改善了图像的视觉效果,使图像更清晰,且算法计算简单,硬件实现容易,在图像处理应用中十分可行有效。