基于HEVC的多长度DCT变换的VLSI设计

为了满足下一代视频压缩标准HEVC中定义的四种不同长度DCT变换的要求,提出了一种灵活的DCT变换的VLSI架构。从DCT系数矩阵分解算法推导出可用于不同长度的一维DCT变换的硬件架构,在保持数据吞吐量不变的情况下,能够支持4,8,16,32点等不同长度的DCT变换。采用130 nm工艺库综合后,得到电路的最高工作频率为131 MHz,能够支持HEVC标准的4 k(4 096×2 048)高清视频进行60帧每秒的编码处理。     

DCT快速算法及其VLSI实现

现在离散余弦变换（DCT）发展很快，本文概述了DCT的各种快速算法及其发展，将DCT算法进行了分类。文中详细地综述了适合于VLSI实现的各种DCT算法结构，并对这一领域的发展及应用前景进行了探讨。     

基于脉动阵列的二维DCT算法及其VLSI设计

本文介绍了一种基于脉动阵列算法的二维离散余弦变换 (2 -DDCT)电路设计。该电路结构不需要复杂的转移存储器 ,而是采用平行输入平行输出的结构 ,完成一次N×N个DCT变换只需要N个周期 ,因此吞吐率是传统DCT的N倍。这种电路结构具有模块化、布线简单、芯片占用面积小等优点 ,十分适合VLSI的实现     

适用于VLSI的一种并行乘法器结构

本文给出了二进制补码和无符号乘法器的通用表达式。对VLSI乘法器的结构进行了讨论。     

基于NEDA算法的二维DCT硬件加速器的设计实现

应用二维DCT的图像压缩系统,DCT的运算量较大,为了突破该瓶颈,设计了基于NEDA算法的DCT硬件加速器,该设计方案采用移位相加代替乘法运算,并用RAM代替ROM,有效地节省了硬件资源.给出了Verilog仿真结果,结果表明该加速器可以在使用资源非常少的情况下,正确地实现二维DCT运算,适合于各种视频图像压缩方面的应用.     

二维DWT／IDWT处理器的VLSI设计

在本文中，我们设计了基于多分辨分析，适合于硬件实现的二维ＤＷＴ和ＩＤＷＴ实时系统，采用了ｔｏｐ－ｄｏｗｎ的ＶＬＳＩ设计方法，用硬件描述语言ＶＨＤＬ，在Ｓｙｎｏｐｓｙｓ系统中进行了验证和综合，综合结果表明：系统的规模为７１４０单元面积，对于四层信小波变换，数据处理速度约可达到４Ｍｐｉｘｅｌ／ｓ。     

二维DCT快速算法及FPGA实现

本文提出了一种二维OCT快速算法的FPGA实现结构,采用行列快速算法将二维DCT分解成两个一维DCT实现,其中一维DCT借鉴Loeffler DCT算法,采用并行的流水线结构,提高电路的数据吞吐率和运算速度,通过系数矩阵的简化和蝶形运算结构的等价减少乘法器的消耗,一维DCT核消耗16个乘法器.转置RAM采用8片双口RAM,一个时钟可以完成 8个数据读写.实验结果验证了二维DCT核设计的正确性,该电路结构消耗资源少,布线简单,功耗小,适合图像的实时处理.     

一种计算机快速二维DCT算法

二维离散余弦变换（２Ｄ－ＤＣＴ）广泛用于数字图像处理中，特别是图像的数据压缩，二维ＤＣＴ的常规算法是行一列法，对于计算（Ｎ×Ｎ）ＤＣＴ，需要计算２Ｎ个一维ＤＣＴ。本文利用三角函数的公式，并将二维输入数据划分为Ｎ个不同的数据集，提出了一种快速算法。该算法对于计算（Ｎ×Ｎ）ＤＣＴ只需要计算Ｎ个一维ＤＣＴ，运算量是常规算法的一半。该算法的计算结构具有高度规则性，只要求执行实数运算。     

一种适于VLSI实现的并行乘法器结构

本文首先讨论了数据格式与改进Booth算法的关系。用简化部分积的扩展符号位所在全加器的连接的方法提出了一种适于VLSI实现的并行乘法器结构。该结构已用于16×16和12×12高速乘法累加器的全定制设计中。     

A Low Power 8 x 8 Direct 2-D DCT Chip Design

This paper presents the design and implementation of a low power 8 × 8 2-D DCT chip based on a computation-effective algorithm. Computational complexity can be reduced by simplifying the direct 2-D algorithm. Thus, the low power consumption is achieved due to complexity reduction. Besides, the parallel distributed-arithmetic (DA) technique is used to realize constant multiplication due to the low-power consideration. Additionally, the 2 V-power supply is practiced in circuit implementation for now and future battery operated applications. By using the TSMC 0.6 m single-poly double-metal technology, 133 mW power consumption at 100 MHz and the 133 MHz maximum operation speed are achieved by critical path simulation.     

基于DCT子空间失真测度的矢量量化VLSI结构设计

本文提出了一种实现离散余弦变换子空间失真测度矢量编码算法的ＶＬＳＩ结构。     

二维DCT图像处理器的低功耗实现

本文提出了一种基于矩阵向量乘法器的低功耗二维DCT结构,该结构通过最大限度地共享矩阵向量乘法中的乘积因子降低二维DCT中的乘法计算量,实现低功耗计算.此外,该二维DCT设计支持对矩阵向量乘法器的计算精度控制,从而实现对二维DCT处理器的低功耗调整.FPGA硬件平台的实际验证结果表明,与传统的基于移位累加乘法器的二维DCT设计相比,本设计可以节省35%以上的功耗.     

简化的模(2n-1)乘运算算法及其VLSI结构

文章提出了一种有效的模(2n-1)余数乘法器实现的算法及其VLSI结构, 其输入为通常的二进制表示, 因此无需另外的输入数据转换电路即可用于数字信号处理.通过利用模(2n-1)运算的周期性,简化其乘积项,并重组求和项优化结构,以减少路径延时和硬件复杂度.较之同类设计, 该结构更加规则,且具有更好的面积和速度性能.     

一种用于实时视频处理的高速二维DCT的电路设计和实现

绝大多数的国际图像和视频压缩标准都采用DCT(离散余弦变换)进行传输编码。本文介绍了一种基于矩阵分解算法的高速实时二维DCT处理器。为了满足视频处理的实时性，整个电路设计中广泛采用了流水线技术，文中详细介绍了二维DCT处理器的电路结构，最后给出了它的FPGA实现。     

Coefficient Elimination Algorithm for Low Energy Distributed Arithmetic DCT Architectures

An energy aware DCT (Discrete Cosine Transform) architecture based on the distributed arithmetic concept is proposed. Architectures based on the distributed arithmetic concept are inherently low power as they are multiplication free algorithms. One characteristic of the DCT is that upon transformation signal energies are concentrated in only a few coefficients (less than 25%) with the rest (75%) of the coefficients being insignificant and negligible. One can skip the computation of these terms without seriously affecting the output signal quality. Exploiting this idea, we propose a low energy DCT architecture that can achieve 55% savings in the energy dissipation and 28 db in signal quality. In addition, we propose an adaptive energy aware DCT architecture that trades off energy consumption for signal quality. Using this adaptive architecture, we present a study of the effect of coefficient elimination on energy consumption and signal quality.Tarek K. Darwish received the B.S. and the M.S. degrees in computer engineering from the University of Balamand, Lebanon, and the M.S. degree, also in computer engineering, from the University of Louisiana at Lafayette, in 1996, 1998, and 2001, respectively. He received the Ph.D. degree from The Center for Advanced Computer Studies (CACS) at the University of Louisiana in Dec. 2003.From 2000–2003, he has been a research assistant in the CACS, in the VLSI Research group of M. Bayoumi, University of Louisiana. He has one patent pending. Since 2004 he is working as a senior component design engineer with Intel Corporation. His research interests include low power VLSI system design, Digital signal processing with special interest in image and video processing, computer architecture, and CAD-tools.Magdy A. Bayoumi received the B.Sc. and M.Sc. degrees in electrical engineering from Cairo University, Cairo, Egypt, and the M.Sc. degree in computer engineering from Washington University in St. Louis, MO, and the Ph.D. degree in electrical engineering from the University of Windsor, Windsor, ON, Canada.Currently, he is the Director of the Center for Advanced Computer Studies (CACS), Department Head of the Computer Science Department, the Edmiston Professor of Computer Engineering, and the Lamson Professor of Computer Science at The Center for Advanced Computer Studies, University of Louisiana at Lafayette, where he has been a faculty member since 1985. He has edited and co-edited three books in the area of VLSI Signal Processing. He was an Associate Editor of the Circuits and Devices Magazine and is currently an Associate Editor of Integration, the VLSI Journal, and the Journal of VLSI Signal Processing Systems. He is a Regional Editor for the VLSI Design Journal and on the Advisory Board of the Journal on Microelectronics Systems Integration. He has one patent pending. His research interests include VLSI design methods and architectures, low power circuits and systems, digital signal processing architectures, parallel algorithm design, computer arithmetic, image and video signal processing, neural networks, and wideband network architectures.Dr. Bayoumi received the 2003 IEEE Circuit and Systems Education Award, the 1993 Distinguished Professor Award and the University of Louisiana at Lafayette 1988 Researcher of the Year Award. He was an Associate Editor of the IEEE CIRCUITS AND DEVICES MAGAZINE, the IEEE TRANSACTIONS ON VLSI SYSTEMS, the IEEE TRANSACTIONS ON NEURAL NETWORKS, and the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. From 1991 to 1994, he served on the Distinguished Visitors Program for the IEEE Computer Society, and he was on the Distinguished Lecture Program of the Circuits and Systems Society. He was the Vice President for the technical activities of the IEEE Circuits and Systems Society. He is the general chair of The IEEE International Symposium on Circuits and Systems—ISCAS in 2007. He was the Co-chairman of the Workshop on Computer Architecture for Machine Perception in 1993. He was the General Chairman of the 1994 MWSCAS and Co-chair of 22003 MWSCAS. He was the General Chairman for the 8th Great Lake Symposium on VLSI in 1998. He has been on the Technical Program Committee for ISCAS for several years and he was the Publication Chair for ISCAS99. He was also the General Chairman of the 2000 Workshop on Signal Processing Design and Implementation. He was a founding member of the VLSI Systems and Applications Technical Committee and was its Chairman. He is currently the Chairman of the Technical Committee on Circuits and Systems for Communication, and he was the chair of the Technical Committee on Signal Processing Design and Implementation. He is a member of the Neural Network and the Multimedia Technology Technical Committees. Currently, he is the faculty advisor for the IEEE Computer Student Chapter at the University of Louisiana at Lafayette. He is a fellow IEEE.     

二维正交子波变换的VLSI并行计算

本文提出一个二维离散正交子波变换的ＶＬＳＩ并行结构，该结构将二维输入信号分解成不重叠的若干行组，从而使每组中的所有行被并行处理，而不同组的行的处理、不同级上的计算，以至不同信号的计算可以在此结构上流水线地进行。     

一种低存储需求的二维DWT VLSI结构设计方法

为了减少基于提升的二维离散小波变换(DWT)VLSI结构设计中的片内存储需求,采用了一种新颖的调度方法,通过读取少量数据进行行滤波操作,并实现和列滤波的并行处理,有效地减少了片内存储容量.此外,行滤波和列滤波变换内部结构采用流水线设计方法,加快了运算速度,提高了硬件资源利用率,减小了电路的规模,并且这种基于提升的9/7离散小波变换二维结构很方便兼容5/3滤波器.经过Verilog HDL仿真验证,结果表明,在50MHz系统时钟下,采用9/7滤波器经3级分解,每秒钟可处理21帧大小为1280×1024×8bit的灰白图像.