一种高稳定性高精度低压差线性稳压器的分析与设计

提出了LDO,其基于缓慢滚降式频率补偿方法,通过在电路中引入三个极零对(极零对的产生没有增加静态功耗),不仅克服了常规LDO不能使用低等效串联电阻、低成本陶瓷输出电容的缺点,而且确保了系统在整个负载和输入电压变化范围内稳定工作.由于LDO通常给高性能模拟电路供电,因此其输出电压精度至关重要;而该补偿方法能满足高环路增益、高单位增益带宽的设计要求,从而大幅提高LDO的精度.该LDO基于0.5μm CMOS工艺实现.后仿结果表明,即使在低压满负载条件下,其开环DC增益仍高于70dB,满载时单位增益带宽可达3MHz,线性调整率和负载调整率分别为27μV/V和3.78μV/mA,过冲和欠冲电压均小于30mV,负载电流为150mA时的漏失电压(dropout电压)仅为120mV.     

一种高稳定性高精度低压差线性稳压器的分析与设计

提出了LDO,其基于缓慢滚降式频率补偿方法,通过在电路中引入三个极零对（极零对的产生没有增加静态功耗）,不仅克服了常规LDO不能使用低等效串联电阻、低成本陶瓷输出电容的缺点,而且确保了系统在整个负载和输入电压变化范围内稳定工作。由于LDO通常给高性能模拟电路供电,因此其输出电压精度至关重要； 而该补偿方法能满足高环路增益、高单位增益带宽的设计要求,从而大幅提高LDO的精度，该LDO基于0.5μm CMOS工艺实现，后仿结果表明,即使在低压满负载条件下,其开环DC增益仍高于70dB,满载时单位增益带宽可达3MHz,线性调整率和负载调整率分别为27μV/V和3.78μV/mA,过冲和欠冲电压均小于30mV,负载电流为150mA时的漏失电压（dropout电压）仅为120mV。     

适用于3D NAND的高稳定度的Capacitor-free LDO

文中设计一种应用于3D NAND的无片外补偿电容的LDO,该电路在传统嵌套米勒补偿的基础上,增加"gm减小电路"和"轻重载控制电路",实现在空载(电流负载为零)且有大负载电容条件下的稳定。此设计应用YMTC 0.18μm工艺实现,仿真结果显示,在2.5～3.6 V电源供电下,整个电路消耗的静态电流为50μA,总补偿电容为7 pF,电路稳定的时间小于6μs,输出线性调整率小于2.2 mV/V,负载调整率小于0.9 mV/mA。     

基于高压摆率误差放大器和摆率增强电路的无片外电容LDO

基于0.35μm CMOS工艺设计了一款无片外电容低压差线性稳压器(cap-free LDO),通过误差放大器组成的环路控制稳态误差,通过摆率增强电路构成的环路改善瞬态响应。该LDO输出电压为1.72V,压差80mV,最大输出电流50mA。测试结果显示:负载电流(IL)在0.5μs内瞬变50mA时,俯冲电压和过冲电压均为80mV左右,重回稳态的时间均小于1.5μs。     

用于无源RFID标签的拓展PSRR带宽无片外电容LDO

经过调制的射频信号整流后会为无源射频识别(RFID)标签引入数万到几十万赫兹的电源纹波.为了抑制这种电源纹波,设计了一款1 MHz带宽内高电源电压抑制比(PSRR)、超低功耗、无片外电容低压差线性稳压器(LDO).利用超级源跟随器结构改变传统LDO环路的极点分布,将输出极点作为环路主极点,将低频PSRR带宽有效拓展到1 MHz.利用动态偏置技术和双零点补偿结构保证环路稳定性.该LDO采用TSMC 0.18 μm CMOS工艺实现,芯片面积约0.017 mm2.测试结果表明:LDO在1 MHz频率范围内的PSRR小于-46 dB,轻负载下的PSRR可达-57 dB;电路消耗0.33～3.4 μA的静态电流;在工作电压为1.1～3 V时输入电压调整率为4.6 mV/V;在负载电流为0～25 μA时负载调整率为0.3 mV/μA;该LDO仅采用35 pF片上电容.     

一种低功耗无电容型LDO的设计

提出了一种片上集成的低功耗无电容型LDO(low drop out)电路。该电路采用折叠型cascode运放作为误差放大器,通过消除零点的密勒补偿技术提高了环路稳定性;并在电路中加入了一种新的限流保护结构以保证输出电流过大时对LDO的输出进行保护。此外,在电路中加入了省电模式,可在保持LDO输出1.8 V情况下节省大于70%的功耗。该设计采用HHNEC 0.13μmCMOS工艺,仿真结果显示:在2.5~5.5 V电源供电、各个工艺角及温度变化条件下,LDO输出的线性调整率小于2.3 mV/V,负载调整率小于14μV/mA,温度系数小于27×10-6/℃;在正常工作模式下,整个LDO消耗85μA电流;在省电模式下仅消耗23μA电流。     

一种新颖的BiCMOS高精度LDO线性稳压电路

设计了一种改进结构的用于锂离子和锂聚合物电池充电管理芯片的高精度、宽电源电压范围LDO线性稳压电路,电路采用0.8μm N阱BiCMOS高压工艺制作。Hspice仿真结果表明,在温度从-20℃到100℃变化时,其温度系数约为±28 ppm/℃;电源电压从4.5 V到25 V变化时,最坏情况下其线性调整率为0.038 mV/V;负载电流从0到满载2 mA变化时,其负载调整率仅为1.28 mV/mA。     

一种低温漂的高精度带隙基准源的设计与分析

根据基准源产生的基本原理、特性,综合温度补偿及电阻分压技术,设计出了一款能广泛应用于开关电源PWM控制器、隔离反馈发生器等的带隙基准源。该基准源电路基于6μm标准BJT工艺实现,仿真结果表明,当电源电压为15 V时,当温度为25℃时,VREF输出为5 V;当12 V≤VCC≤25 V时,线性调整率为0.16 mV;当1 mA≤I0≤20 mA时,负载调整率为1.61 mV左右;温度稳定性良好,大约为0.05 mV/℃。     

一款采用超前相位补偿技术的低压差线性稳压器

设计了一种具有高稳定性、能够驱动较大负载电流的低压差线性稳压器(LDO)电路,输入电压为3.0~6.0 V,输出电压为2.8 V。采用超前相位补偿技术,产生一组零极点对,零点补偿前面环路中的极点,使得LDO电路具有稳定的环路结构,得到稳定的输出电压。基于CSMC 0.25μm EN BCDMOS工艺完成电路和版图的设计。电路仿真结果表明电路的负载调整率为0.03%/A,线性调整率为0.13%/V,最大驱动的负载电流为10 mA。在不同负载条件下,LDO环路的最差相位裕度能够达到64.1°。     

一种低温漂的高精度带隙基准源的设计与分析

根据基准源产生的基本原理、特性,综合温度补偿及电阻分压技术,设计出了一款能广泛应用于开关电源PWM控制器、隔离反馈发生器等的带隙基准源。该基准源电路基于6μm标准BJT工艺实现,仿真结果表明,当电源电压为15 V时,当温度为25℃时,VREF输出为5 V;当12 V≤VCC≤25 V时,线性调整率为0.16 mV;当1 mA≤I0≤20 mA时,负载调整率为1.61 mV左右;温度稳定性良好,大约为0.05 mV/℃。     

一种动态补偿、高稳定性的LDO设计

设计并实现了一种动态补偿、高稳定性的LDO.针对LDO控制环路稳定性随负载电流变化的特点,给出一种新颖的动态补偿电路.这种补偿电路能很好地跟踪负载电流的变化,从而使控制环路的稳定性几乎与负载电流无关.设计采用CSMC 0.5μm标准CMOS工艺,利用Cadence的EDA工具完成电路设计、版图绘制和流片测试,最终芯片面...     

一种快速瞬态响应的无片外电容LDO的设计

基于上华0.5μm工艺,设计了输入电压范围为3.5～6.5V,输出电压为3.3V,最大输出电流为100mA的CMOS无片外电容的低压差线性稳压器.提出了一种自动检测网络用来快速感应负载电流的变化,抑制输出电压的跳变,改善了负载瞬态响应.在稳定性方面,采用miller补偿,加之第二级采用了输出电阻很小的buffer结构[1],这样主极点和次极点分离很远使得系统稳定.仿真表明,该LDO在VIN=6.5V和VIN=3.5V下under-shoot分别为156mV和135mV,overshoot分别为145mV和60mV,线性调整率和负载调整率分别为0.023%和0.5%.     

250 mV Supply Voltage Digital Low‐Dropout Regulator Using Fast Current Tracking Scheme

This paper proposes a 250 mV supply voltage digital low‐dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a 0.11 μm CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over‐voltage and under‐voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at 20 μA to 200 μA load current.     

一种1.2V,80mA,5μF快速瞬态响应、高稳定性LDO的设计

基于上华0.5μm工艺,设计了输入电压为1.5V,输出电压为1.2V,最大输出电流为80mA,用于DC/DC里的CMOS低压差线性稳压器(Low-dropout regulator),作为带隙基准输出端的后续模块,以达到滤波和提高参考电压精度的目的。提出了一种补偿网络,可以保证负载电流发生变化时,相位裕量不发生变化;在补偿网络的基础上添加一个感应电容能够快速跟踪极点的变化,从而保证在负载电流跳变瞬间稳定性保持不变,防止了输出电压发生振荡的情形。此外,设计了一种瞬态响应提高电路结构来改善负载瞬态响应。仿真结果表明,在tt corner下该LDO线性稳压器在负载电流为1mA和80mA时的相位裕度均为83°,环路增益为80dB,流片测试结果显示过冲电压和欠冲电压均不超过100mV。     

一种用于LDO稳压器的共享预稳压电路

提出了一种用于LDO稳压器的共享预稳压电路.该共享预稳压电路中包含一个电源抑制减法电路以提高基准源的电源抑制,应用电流负反馈结构以降低基准源的温度系数和电源抑制随工艺阈值电压变化的敏感度,还可以降低LDO稳压器的输出噪声.仿真结果表明在阈值电压发生士20％变化的情况下,基准源的温度系数变化只有0.11×10-6/℃,电...     

A fully on-chip area-efficient CMOS low-dropout regulator with fast load regulation

Fully integrated voltage regulators with fast transient response and small area overhead are in high demand for on-chip power management in modern SoCs. A fully on-chip low-dropout regulator (LDO) comprised of multiple feedback loops to tackle fast load transients is proposed, designed and simulated in 90?nm CMOS technology. The LDO also adopts an active frequency compensation scheme that only needs a small amount of compensation capacitors to ensure stability. Simulation results show that, by the synergy of those loops, the LDO improves load regulation accuracy to 3???V/mA with a 1.2?V input and 1?V output. For a 100?mA load current step with the rise/fall time of 100?ps, the LDO achieves maximum output voltage drop and overshoot of less than 95?mV when loaded by a 600?pF decoupling capacitor and consumes an average bias current of 408???A. The LDO also features a magnitude notch in both its PSRR and output impedance that provides better suppression upon the spectral components of the supply ripple and the load variation around the notch frequency. Monte Carlo simulations are performed to show that the LDO is robust to process and temperature variations as well as device mismatches. The total area of the LDO excluding the decoupling capacitor is about 0.005?mm². Performance comparisons with existing solutions indicate significant improvements the proposed LDO achieves.     

Current buffer compensation topologies for LDOs with improved transient performance

The goal of internal frequency compensation of a low dropout voltage regulator (LDO) is the selection of a small-value, ESR-independent output capacitor. Cascode compensation formed by a common-gate transistor acting as a current buffer, an optional series resistor, and a compensation capacitor creates a dominant pole and a left-half-plane (LHP) zero, allowing adequate phase margin and stable LDO design. To this end, a 1.21?V output, 100?mA, 0.1?C10???F output capacitor, ESR-independent, low voltage LDO using cascode compensation with replica bias is designed and fabricated in a 0.5???m CMOS process with an area of 0.22?mm². A line regulation of 0.05% V/V, load regulation of 0.001% V/mA and dropout voltage of 220?mV were measured. LDO-specific pole-zero analysis is detailed. In addition to this design, two improved transient response LDO architectures using cascode compensation with split-length transistors are also explored. A Power Good feature is discussed, which enables direct interface between the LDO and a micro-processor.     

An ultra-low power output capacitor-less low-dropout regulator with slew-rate-enhanced circuit

An ultra-low power output-capacitorless low-dropout (LDO) regulator with a slew-rate-enhanced (SRE)circuit is introduced.The increased slew rate is achieved by sensing the transient output voltage of the LDO and then charging (or discharging) the gate capacitor quickly.In addition,a buffer with ultra-low output impedance is presented to improve line and load regulations.This design is fabricated by SMIC 0.18 μm CMOS technology.Experimental results show that,the proposed LDO regulator only consumes an ultra-low quiescent current of 1.2 μA.The output current range is from 10 μA to 200 mA and the corresponding variation of output voltage is less than 40 mV.Moreover,the measured line regulation and load regulation are 15.38 mV/V and 0.4 mV/mA respectively.     

0.13μm BiCMOS低压差线性稳压器

设计了一种0.13μm BiCMOS低压差线性稳压器(LDO),包括BiCMOS误差放大器、带软启动的BiCMOS带隙基准源、"套筒式"共源-共栅补偿电路等。为了改善线性瞬态响应性能,在BiCMOS误差放大器的前级设置了动态电流偏置电路。由于所设计的BiCMOS带隙基准源对温度的敏感性较小,故能为LDO提供高精度的基准电压。对所设计的LDO进行了工艺流片。流片测试结果表明,该LDO可提供60 mA的输出电流且最小压差只有100 mV。测试同时验证了所设计LDO的负载和瞬态响应都得到改善:负载调整率为0.054 mV/mA,线性调整率为0.014%,而芯片面积约为0.094 mm2,因此特别适用于高精度、便携式片上电源系统。