共查询到20条相似文献,搜索用时 15 毫秒
1.
High-performance EEPROMs using n- and p-channel polysilicon thin-film transistors (poly-Si TFTs) with electron cyclotron resonance (ECR) N2O-plasma oxide have been demonstrated. Both programming and erasing were accomplished by Fowler-Nordheim (F-N) tunneling within 1 ms regardless of programming and erasing voltages. The poly-Si TFT EEPROMs have a threshold voltage shift of 4 V between programmed and erased states; furthermore, they maintain a large threshold voltage shift of 2.5 V after 1×105 program and erase cycles. This is attributed to the excellent charge-to-breakdown (Qbd) up to 10 C/cm2 of ECR N2O-plasma oxide 相似文献
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Kim Y.-S. Okada Y. Chang K.-M. Tobin P.J. Morton B. Choe H. Bowers M. Kuo C. Chrudimsky D. Ajuria S.A. Yeargain J.R. 《Electron Device Letters, IEEE》1993,14(7):342-344
The superior characteristics of floating-gate electron tunneling MOS (FETMOS) EEPROMs fabricated using a furnace N2O oxynitridation process are described. These devices exhibited about eight times better endurance and good data retention characteristics while maintaining defect density comparable to that of the control thermal oxide devices. These devices also showed very good thickness uniformity across the wafer and wafer-to-wafer 相似文献
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Vogel E.M. Suehle J.S. Edelstein M.D. Wang B. Chen Y. Bernstein J.B. 《Electron Devices, IEEE Transactions on》2000,47(6):1183-1191
An experimental investigation of breakdown and defect generation under combined substrate hot-electron and tunneling electrical stress of silicon oxide ranging in thickness from 2.0 nm to 3.5 nm is reported. Using independent control of the gate current for a given substrate and gate bias, the time-to-breakdown of ultrathin silicon dioxide under substrate hot-electron stress is observed to be inversely proportional to the gate current density. The thickness dependence (2.0 nm to 3.5 nm) of substrate hot-electron reliability is reported and shown to be similar to constant voltage tunneling stress. The build-up of defects measured using stress-induced-leakage-current and charge-pumping for both tunneling and substrate hot-electron stress is reported. Based on these and previous results, a model is proposed to explain the time-to-breakdown behavior of ultrathin oxide under simultaneous tunneling and substrate hot-electron stress. The results and model provide a coherent understanding for describing the reliability of ultrathin SiO2 under combined substrate hot-electron injection and constant voltage tunneling stress 相似文献
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Ghetti A. Sangiorgi E. Bude J. Sorsch T.W. Weber G. 《Electron Devices, IEEE Transactions on》2000,47(12):2358-2365
This paper reports experimental data and simulations of low-voltage tunneling in ultrathin oxide MOS devices. When the substrate is very heavily doped, a thermionic barrier is present that opposes the direct tunneling of gate electrons when the applied gate voltage is between 0 V and the flatband voltage. In such conditions, we show that the measured gate current cannot be explained by direct tunneling, but features an additional, dominant component. The temperature dependence of this extra component indicates that it is due to gate electrons tunneling into the anode interface states. By comparing measurements and simulations, it is possible to exploit this extra current to estimate the interface state density within the silicon band gap. In addition, it is shown that this tunneling current component is very sensitive to electrical stress and allows a clear detection of oxide wear out even for stress at very low field. Therefore, it can be adopted as monitor of oxide degradation in ultrathin oxides where the traditional stress induced leakage current due to bulk-oxide traps is not detectable. 相似文献
5.
Wang T. Chang T.-E. Chiang L.-P. Wang C.-H. Zous N.-K. Huang C. 《Electron Devices, IEEE Transactions on》1998,45(7):1511-1517
We proposed a new measurement technique to investigate oxide charge trapping and detrapping in a hot carrier stressed n-MOSFET by measuring a GIDL current transient. This measurement technique is based on the concept that in a MOSFET the Si surface field and thus GIDL current vary with oxide trapped charge. By monitoring the temporal evolution of GIDL current, the oxide charge trapping/detrapping characteristics can be obtained. An analytical model accounting for the time-dependence of an oxide charge detrapping induced GIDL current transient was derived. A specially designed measurement consisting of oxide trap creation, oxide trap filling with electrons or holes and oxide charge detrapping was performed. Two hot carrier stress methods, channel hot electron injection and band-to-band tunneling induced hot hole injection, were employed in this work. Both electron detrapping and hole detrapping induced GIDL current transients mere observed in the same device. The time-dependence of the transients indicates that oxide charge detrapping is mainly achieved via field enhanced tunneling. In addition, we used this technique to characterize oxide trap growth in the two hot carrier stress conditions. The result reveals that the hot hole stress is about 104 times more efficient in trap generation than the hot electron stress in terms of injected charge 相似文献
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Enhanced Hole Gate Direct Tunneling Current in Process-Induced Uniaxial Compressive Stress p-MOSFETs 总被引:1,自引:0,他引:1
《Electron Devices, IEEE Transactions on》2009,56(8):1667-1673
9.
Dynamic oxide voltage relaxation spectroscopy 总被引:3,自引:0,他引:3
Mingzhen Xu Changhua Tan Yandong He Xiaowei Liu Yangyuan Wang 《Electron Devices, IEEE Transactions on》1996,43(4):628-635
A new method for trap characterization of oxidized silicon is described. The Dynamic Oxide Voltage Relaxation Spectroscopy (DOVRS) is an improved version of the formerly proposed Oxide Voltage Relaxation Spectroscopy (OVRS) technique which applies a periodic long duration constant current for tunneling injection. It has been demonstrated that the new technique can be used not only to separate and identify the oxide trap from interface trap, but also to separate and determine the centroid from the oxide trap density generated in the MOS system by the tunneling current stress. In the pulse constant current mode, the OVRS measurement can be completed instead of using the double current-voltage technique. Thus the new method results in more accurate and quicker measurements of the oxide trap centroid. Analytical expressions for computing the paramaters of the interface and oxide traps are derived. The effect of the channel carrier mobility on the spectroscopy is also considered. Two types of oxide and two types of interface traps were observed at a pulse constant Fowler-Nordheim current stress by the new method of DOVRS 相似文献
10.
超薄栅MOS结构恒压应力下的直接隧穿弛豫谱 总被引:1,自引:1,他引:0
随着器件尺寸的迅速减小 ,直接隧穿电流将代替 FN电流而成为影响器件可靠性的主要因素 .根据比例差值算符理论和弛豫谱技术 ,针对直接隧穿应力下超薄栅 MOS结构提出了一种新的弛豫谱——恒压应力下的直接隧穿弛豫谱 (DTRS) .该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点 ,能够分离和表征超薄栅 MOS结构不同氧化层陷阱 ,提取氧化层陷阱的产生 /俘获截面、陷阱密度等陷阱参数 .直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅 MOS结构中陷阱的产生和复合 ,为超薄栅 MOS结构的可靠性研究提供了一强有力工具 . 相似文献
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Neugroschel A. Chih-Tang Sah Carroll M.S. Pfaff K.G. 《Electron Devices, IEEE Transactions on》1997,44(5):792-800
The base current relaxation transient following reverse emitter-base (EB) bias stress and its effect on time-to-failure (TTF) determination are examined in self-aligned and nonself-aligned silicon bipolar junction transistors (BJTs) with thermal and deposited base oxide. A quantitative model indicates that the transient is due to a reduction of the stress-generated positive charge trapped in the oxide layer near the emitter-base junction due to holes tunneling from oxide hole traps to silicon band states or SiO2/Si interface traps. The neutral oxide hole traps may be quickly recharged through hole tunneling or hole injection into the oxide during further reverse-bias stress. A delay time of ~10-3 s was observed after the termination of stress before base current relaxation begins, which affects the extraction of the ac operation TTF from dc stress measurements 相似文献
13.
Tahui Wang Nian-Kai Zous Jia-Long Lai Chimoon Huang 《Electron Device Letters, IEEE》1998,19(11):411-413
The mechanisms and transient characteristics of hot hole stress induced leakage current (SILC) in tunnel oxides are investigated. Positive oxide charge assisted tunneling is found to be a dominant SILC mechanism in a hot hole stressed device. The SILC transient is attributed to oxide hole detrapping and thus annihilation of positive charge assisted tunneling centers. Our characterization shows that the leakage current transient in a 100-Å oxide obeys a power law time dependence f-n with the power factor n significantly less than one. An analytical model accounting for the observed time dependence is proposed 相似文献
14.
The effects of oxygen vacancies on the electronic structure of silicon dioxide and the hole tunneling current were investigated using first-principles calculations. A level related to oxygen vacancy was obtained to be nearly 2.0 eV from the top of valence band within the bandgap of the α-quartz supercell with one oxygen vacancy. And therefore the defect assisted hole (electron) tunneling currents were calculated. The results shows that the hole tunneling current will be dominant for a thinner oxide thickness at low oxide field and the contribution of trap assisted hole tunneling to the total tunneling current decreases with oxide thickness and oxide field increasing. It is concluded that the effects of the oxygen vacancies on the hole tunneling current become smaller with larger oxide thickness and higher electric field. 相似文献
15.
Hsu B.-C. Chen K.-F. Lai C.-C. Lee S.W. Liu C.W. 《Electron Devices, IEEE Transactions on》2002,49(12):2204-2208
Two-dimensional (2-D) device simulation is used to investigate the tunneling current of metal ultra-thin-oxide silicon tunneling diodes with different oxide roughness. With the conformal nature of ultrathin oxide, the tunneling current density is simulated in both direct tunneling and Fowler-Nordheim (FN) tunneling regimes with different oxide roughness. The results show that oxide roughness dramatically enhances the tunneling current density and the 2-D electrical effect is responsible for this increment of tunneling current density. Furthermore, a set of devices with controlled oxide roughness is fabricated to verify the simulation results and our model qualitatively agrees with the experiment results. 相似文献
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Charge trapping in the gate oxide and at the interfaces caused by electrical stress may lead to changes of both the oxide field and the shape of tunneling barrier. In this study, a simple technique based on the analysis of a small change in the Fowler-Nordheim (FN) tunneling current has been developed to quantitatively examine the changes of the effective barrier height and the electric field at the tunneling interface. A power-law dependence of the changes of both the barrier height and the electric field on the stress time is observed. 相似文献
18.
Gu S.-H. Hsu C.-W. Wang T. Lu W.-P. Ku Y.-H. J. Lu C.-Y. 《Electron Devices, IEEE Transactions on》2007,54(1):90-97
In this paper, bottom-oxide thickness (Tbo) and program/erase stress effects on charge retention in SONOS Flash memory cells with FN programming are investigated. Utilizing a numerical analysis based on a multiple electron-trapping model to solve the Shockley-Read-Hall rate equations in nitride, we simulate the electron-retention behavior in a SONOS cell with Tbo from 1.8 to 5.0 nm. In our model, the nitride traps have a continuous energy distribution. A series of Frenkel-Poole (FP) excitation of trapped electrons to the conduction band and electron recapture into nitride traps feature the transitions between the conduction band and trap states. Conduction band electron tunneling via oxide traps created by high-voltage stress and trapped electron direct tunneling through the bottom oxide are included to describe various charge leakage paths. We measure the nitride-charge leakage current directly in a large-area device for comparison. This paper reveals that the charge-retention loss in a high-voltage stressed cell, with a thicker bottom oxide (5 nm), exhibits two stages. The charge-leakage current is limited by oxide trap-assisted tunneling in the first stage and, then, follows a 1/t time dependence due to the FP emission in the second stage. The transition time from the first stage to the second stage is related to oxide trap-assisted tunneling time but is prolonged by a factor 相似文献
19.
Hu Shigang Hao Yue Cao Yanrong Ma Xiaohua Wu Xiaofeng Chen Chi Zhou Qingjun 《半导体学报》2009,30(4):044004-044004-4
The degradation of device under GIDL(gate-induced drain leakage current)stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides.Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg.The characteristics of the GIDL current are used to analyze the damage generated during the stress.It is clearly found that the change of GIDL current before and after stress can be divided into two stages.The trapping of holes in the oxide is dominant in the first stage,but that of electrons in the oxide is dominant in the second stage.It is due to the common effects of edge direct tunneling and band-to-band tunneling.SILC(stress induced leakage current)in the NMOSFET decreases with increasing stress time under GIDL stress.The degradation characteristic of SILC also shows saturating time dependence.SILC is strongly dependent on the measured gate voltage.The higher the measured gate voltage,the less serious the degradation of the gate current.A likely mechanism is presented to explain the origin of SILC during GIDL stress. 相似文献
20.
应用直接隧道比例差分(DTPDO)谱技术研究了深亚微米MOS器件超薄栅氧化层的应力诱生缺陷。实验结果发现超薄栅氧化层直接隧道栅电流的比例差分谱存在明显的三个谱峰。这意味着在超薄栅氧化层退化的过程中有三种氧化层高场诱生缺陷共存。研究结果表明,三种缺陷的饱和缺陷密度均随着应力电压和应力温度的增加而增加。三种缺陷的特征产生时间常数与器件的实验温度、所加的应力电压和氧化层的失效时间相关。 相似文献