MeV energy sulfur implantation in GaAs and InP

Room temperature and elevated temperature sulfur implants were performed into semi-insulating GaAs and InP at variable energies and fluences. The implantations were performed in the energy range 1–16 MeV. Range statistics of sulfur in InP and GaAs were calculated from the secondary ion mass spectrometry atomic concentration depth profiles and were compared with TRIM92 values. Slight in-diffusion of sulfur was observed in both InP and GaAs at higher annealing temperatures for room temperature implants. Little or no redistribution of sulfur was observed for elevated temperature implants. Elevated temperature implants showed higher activations and higher mobilities compared to room temperature implants in both GaAs and InP after annealing. Higher peak electron concentrations were observed in sulfur-implanted InP (n ≈ 1 × 10¹⁹ cm⁻³) compared to GaAs (n ≈ 2 × 10¹⁸ cm⁻³). The doping profile for a buried n⁺ layer (n ≈ 3.5 × 10¹⁸ cm⁻³) of a positive-intrinsic-negative diode in GaAs was produced by using Si/S coimplantation.     

MOCVD grown CdZn Te/GaAs/Si substrates for large-area HgCdTe IRFPAs

Large-area HgCdTe 480×640 thermal-expansion-matched hybrid focal plane arrays were achieved by substituting metalorganic chemical vapor deposition (MOCVD)-grown CdZnTe/GaAs/Si alternative substrate in place of bulk CdZnTe substrates for the growth of HgCdTe p-on-n double-layer heterojunctions by controllably-doped mercury-melt liquid phase epitaxy (LPE). (100) CdZnTe was grown by MOCVD on GaAs/Si using a vertical-flow high-speed rotating disk reactor which incorporates up to three two-inch diameter substrates. Layers having specular surface morphology, good crystalline structure, and surface macro defect densities <50 cm⁻² are routinely achieved and both the composition uniformity and run-to-run reproducibility were very good. As the composition of the CdZnTe layers increases, the x-ray full width at half maximum (FWHM) increases; this is a characteristic of CdZnTe grown by VPE techniques and is apparently associated with phase separation. Despite a broader x-ray FWHM for the fernary CdZnTe, the FWHM of HgCdTe grown by LPE on these substrates decreases, particularly for [ZnTe] compositions near the lattice matching condition to HgCdTe. An additional benefit of the ternary CdZnTe is an improved surface morphology of the HgCdTe layers. Using these silicon-based substrates, we have demonstrated 78K high-performance LWIR HgCdTe 480×640 arrays and find that their performance is comparable to similar arrays fabricated on bulk CdZnTe substrates for temperatures exceeding approximately 78K. The performance at lower temperatures is apparently limited by the dislocation density which is typically in the low-mid 10⁶ cm⁻² range for these heteroepitaxial materials.     

Ohmic contacts to n-type GaSb and n-type GalnAsSb

An investigation with the objective of improving n-type ohmic contacts to GaSb-based devices is described. This study involves a series of n-GaInAsSb and n-GaSb samples with varying doping, grown on semi-insulating (SI) GaAs substrates. These samples were fabricated into mesa-etched, transfer-length method (TLM) structures, and the specific-contact resistivity and sheet resistance of these layers as a function of majority electron concentration were measured. Extremely low specific-contact resistivities of about 2 × 10⁻⁶ Ω-cm² and sheet resistances of about 4 Ω/▭ are found for n-type GaInAsSb doped at about 3 × 10¹⁸ cm⁻³.     

Halogen lamp rapid thermal annealing of Si- and Be-implanted In0.53Ga0.47As

Halogen lamp rapid thermal annealing was used to activate 100 keV Si and 50 keV Be implants in In_0.53Ga_0.47As for doses ranging between 5 × 10¹²−4 × 10¹⁴ cm⁻². Anneals were performed at different temperatures and time durations. Close to one hundred percent activation was obtained for the 4.1 × 10¹³ cm⁻² Si-implant, using an 850° C/5 s anneal. Si in-diffusion was not observed for the rapid thermal annealing temperatures and times used in this study. For the 5 × 10¹³ cm⁻² Be-implant, a maximum activation of 56% was measured. Be-implant depth profiles matched closely with gaussian profiles predicted by LSS theory for the 800° C/5 s anneals. Peak carrier concentrations of 1.7 × 10¹⁹ and 4 × 10¹⁸ cm⁻³ were achieved for the 4 × 10¹⁴ cm⁻² Si and Be implants, respectively. For comparison, furnace anneals were also performed for all doses.     

Capacitance-Voltage characteristics of metal-insulator-semiconductor diodes with S passivation and Si interface control layers on GaAs and InP

GaAs and InP surfaces have been prepared by gas-phase and liquid-phase polysulfide passivation techniques followed by the deposition of Si interface control layers (ICLs) by e-beam evaporation. For GaAs surfaces, the performance of an ICL consisting of 1.5 nm Si on top of 0.5 nm of Ge has also been evaluated. Metal-insulator-semiconductor diodes with aluminum top electrodes were fabricated on these surfaces using silicon nitride deposited by a remote plasma-enhanced chemical vapor technique or silicon dioxide deposited by a conventional direct plasma-enhanced chemical vapor deposition technique. The quality of the interfaces was analyzed by capacitance-voltage (C-V) measurements and the interface state densities D_it were deduced from the C-V data using the high-low method. Values as low as 1.5 × 10¹² eV⁻¹cm⁻² were obtained for polysulfide-passivated GaAs surfaces with a Ge-Si or Si ICL, the lowest ever demonstrated using the high-low method for an ex-situ technique not involving GaAs epitaxy. For InP, the Si ICL does not reduce D_it below that of 2 × 10¹² eV⁻¹ cm ⁻² that was obtained for the polysulfide passivated surface. The Si ICL produces an interface that degrades more slowly on exposure to air for both GaAs and InP.     

Highly conductive buried n+ layers in lnp:fe created by MeV energy Si,S, and Si/S implantation for application to microwave devices

To obtain highly conductive buried layers in InP:Fe, MeV energy Si, S, and Si/ Simplantations are performed at 200°C. The silicon and sulfer implants gave 85 and 100 percent activation, respectively, for a fluence of 8 × 10¹⁴ cm⁻². The Si/S co-implantation also gave almost 100 percent donor activation for a fluence of 8 × 10¹⁴ cm⁻² of each species. An improved silicon donor activation is observed in the Si/S co-implanted material compared to the material implanted with silicon alone. The peak carrier concentration achieved for the Si/S co-implant is 2 × 10¹⁹ cm³. The lattice damage on the surface side of the profile is effectively removed after rapid thermal annealing. Multiple-energy silicon and sulfur implantations are performed to obtain thick and buried n⁺ layers needed for microwave devices and also hyper-abrupt profiles needed for varactor diodes.     

High purity InxGa1−xSb single crystals with cutoff wavelength of 7–8 µm grown by melt epitaxy

For the first time, InGaSb single crystals with a cutoff wavelength of 7–8 μm were successfully grown on GaAs substrates by a new growth technique named melt epitaxy. The band gap of InGaSb layers obviously narrowed compared with those with the same compositions grown by ordinary methods and the longest cutoff wavelength reached 8.3 μm. High electron mobility of 8.05×10⁴ cm²/Vs and low carrier density of 1×10¹⁵ cm⁻³ at 77 K were obtained indicating high purity of InGaSb epilayers.     

Application of low temperature GaAs to GaAs/Si

Low Temperature grown GaAs (LT-GaAs) was incorporated as a buffer layer for GaAs on Si (GaAs/Si) and striking advantages of this structure were confirmed. The LT-GaAs layer showed high resistivity of 1.7 × 10⁷ ω-cm even on a highly defective GaAs/Si. GaAs/Si with the LT-GaAs buffer layers had smoother surfaces and showed much higher photoluminescence intensities than those without LT-GaAs. Schottky diodes fabricated on GaAs/Si with LT-GaAs showed a drastically reduced leakage current and an improved ideality factor. These results indicate that the LT-GaAs buffer layer is promising for future integrated circuits which utilize GaAs/Si substrates.     

Activation of silicon ion-implanted gallium nitride by furnace annealing

Ion implantation into III–V nitride materials is animportant technology for high-power and high-temperature digital and monolithic microwave integrated circuits. We report the results of the electrical, optical, and surface morphology of Si ion-implanted GaN films using furnace annealing. We demonstrate high sheet-carrier densities for relatively low-dose (n_atoms=5×10¹⁴ cm⁻²) Si implants into AlN/GaN/sapphire heteroepitaxial films. The samples that were annealed at 1150°C in N₂ for 5 min exhibited a smooth surface morphology and a sheet electron concentration n_s ∼9.0×10¹³ cm⁻², corresponding to an estimated 19% electrical activation and a 38% Si donor activation in GaN films grown on sapphire substrates. Variable-temperature Hall-effect measurem entsindicate a Si donor ionization energy ∼15 meV.     

High-efficiency,thin-film InP concentrator solar cells

High-efficiency, thin-film InP solar cells grown heteroepitaxially on GaAs and Si single-crystal bulk substrates are being developed as a means of eliminating the problems associated with using single-crystal InP substrates (e.g., high cost, fragility, high mass density and low thermal conductivity). A novel device structure employing a compositionally graded Ga _x In_1−x As layer (∼8 μm thick) between the bulk substrate and the InP cell layers is used to reduce the dislocation density and improve the minority carrier properties in the InP. The structures are grown in a continuous sequence of steps using computer-controlled atmospheric-pressure metalorganic vapor-phase epitaxy (AP-MOVPE). Dislocation densities as low as 3×10⁷ cm⁻² and minority carrier lifetimes as high as 3.3 ns are achieved in the InP layers with this method using both GaAs or Si substrates. Structures prepared in this fashion are also completely free of microcracks. These results represent a substantial improvement in InP layer quality when compared to heteroepitaxial InP prepared using conventional techniques such as thermally cycled growth and post-growth annealing. The present work is concerned with the fabrication and characterization of thin-film InP solar cells designed for operation at high solar concentration (∼100 suns) which have been prepared from similar device structures grown on GaAs substrates. The cell performance is characterized as a function of the air mass zero (AM0) solar concentration ratio (1–100 suns) and operating temperature (25°–80° C). From these data, the temperature coefficients of the cell performance parameters are derived as a function of the concentration ratio. Under concentration, the cells exhibit a dramatic increase in efficiency and an improved temperature coefficient of efficiency. At 25° C, a peak conversion efficiency of 18.9% (71.8 suns, AM0 spectrum) is reported. At 80° C, the peak AM0 efficiency is 15.7% at 75.6 suns. These are the highest efficiencies yet reported for InP heteroepitaxial cells. Approaches for further improving the cell performance are discussed.     

Progress in the Molecular Beam Epitaxy of HgCdTe on Large-Area Si and CdZnTe Substrates

This paper presents the progress in the molecular beam epitaxy (MBE) growth of HgCdTe on large-area Si and CdZnTe substrates at Raytheon Vision Systems. We report a very high-quality HgCdTe growth, for the first time, on an 8 cm × 8 cm CdZnTe substrate. This paper also describes the excellent HgCdTe growth repeatability on multiple 7 cm × 7 cm CdZnTe substrates. In order to study the percentage wafer area yield and its consistency from run to run, small lots of dual-band long-wave infrared/long-wave infrared triple-layer heterojunction (TLHJ) layers on 5 cm × 5 cm CdZnTe substrates and single-color double-layer heterojunction (DLHJ) layers on 6-inch Si substrates were grown and tested for cutoff wavelength uniformity and micro- and macrovoid defect density and uniformity. The results show that the entire lot of 12 DLHJ-HgCdTe layers on 6-inch Si wafers meet the testing criterion of cutoff wavelength within the range 4.76 ± 0.1 μm at 130 K and micro- and macrovoid defect density of ≤50 cm⁻² and 5 cm⁻², respectively. Likewise, five out of six dual-band TLHJ-HgCdTe layers on 5 cm × 5 cm CdZnTe substrates meet the testing criterion of cutoff wavelength within the range 6.3 ± 0.1 μm at 300 K and micro- and macrovoid defect density of ≤2000 cm⁻² and 500 cm⁻², respectively, on the entire wafer area. Overall we have found that scaling our HgCdTe MBE process to a 10-inch MBE system has provided significant benefits in terms of both wafer uniformity and quality.     

Highly strained ln0.35Ga0.65As/GaAs layers grown by molecular beam epitaxy for high hole mobility transistors

We have grown highly strained In_0.35Ga_0.65As layers on GaAs substrates by molecular beam epitaxy to improve the performance of high hole mobility transistors (HHMTs). The mobility and sheet hole concentration of double side doped pseudomorphic HHMT structures at room temperature reached 314 cm2/V-s and 1.19 × 10¹² cm⁻², respectively. Photoluminescence measurements at room temperature show good crystalline quality of the In^0.35Ga_0.65As layers. This study suggests that the performance of HHMTs can be improved by using high-quality In_0.35Ga_0.65As layers for the channel of double side doped heterostructures pseudomorphically grown on GaAs substrates.     

Effects of S,Si, or Fe dopants on the diffusion of Zn in InP during MOCVD

Diffusion of Zn in InP during growth of InP epitaxial layers has been investigated in layer structures consisting of Zn-InP epilayers grown on S-InP and Fe-InP substrates, and on undoped InP epilayers. The layers were grown by metalorganic chemical vapour deposition (MOCVD) atT = 625° C andP = 75 Torr. Dopant diffusion profiles were measured by secondary ion mass spectrometry (SIMS). At sufficiently high Zn doping levels ([Zn] ≥8 × 10¹⁷ cm⁻³) diffusion into S-InP substrates took place, with accumulation of Zn in the substrate at a concentration similar to [S]. Diffusion into undoped InP epilayers produced a diffusion tail at low [Zn] levels, probably associated with interstitial Zn diffusion. For diffusion into Fe-InP, this low level diffusion produced a region of constant Zn concentration at [Zn] ≈ 3 × 10¹⁶ cm⁻³, due to kick-out of the original Fe species from substitutional sites. We also investigated diffusion out of (Zn, Si) codoped InP epilayers grown on Fe-InP substates. The SIMS profiles were characterised by a sharp decrease in [Zn] at the epilayer-substrate interface; the magnitude of this decrease corresponded to that of the Si donor level in the epilayer. For [Si] ≫ [Zn] in the epilayer no Zn diffusion was observed; Hall measurements indicated that the donor and acceptor species in those samples were electrically active. All these results are consistent with the presence of donor-acceptor interactions in InP, resulting in the formation of ionised donor-acceptor pairs which are immobile, and do not contribute to the diffusion process.     

Indium-tin oxide/Si contacts with In- and Sn-diffusion barriers in polycrystalline Si thin-film transistor liquid-crystal displays

Indium and tin were used as the diffusion barrier between indium-tin oxide (ITO) and polycrystalline-silicon layers to reduce the contact resistance. The ITO/Si contacts may be adopted in thin-film transistor liquid-crystal displays (TFT-LCD) to reduce the number of fabrication steps. With In and Sn layers, contact-resistance values of 5 × 10⁻³−4×10⁻³ Ωcm² were obtained. These values were higher than those of the conventional ITO/Mo/Al/Si contacts (3×10⁻⁵−4 × 10⁻⁴ Ωcm²) but lower than the values obtained from ITO/Si contacts (about 1×10⁻² Ωcm²). The Sn was stable after annealing, but In diffused into Si and lost its function as the diffusion barrier.     

P- and N-type doping of GaN and AlGaN epitaxial layers grown by metalorganic chemical vapor deposition

Mg- and Si-doped GaN and AlGaN films were grown by metalorganic chemical vapor deposition and characterized by room-temperature photoluminescence and Hall-effect measurements. We show that the p-type carrier concentration resulting from Mg incorporation in GaN:Mg films exhibits a nonlinear dependence both on growth temperature and growth pressure. For GaN and AlGaN, n-type doping due to Si incorporation was found to be a linear function of the silane molar flow. Mg-doped GaN layers with 300K hole concentrations p ∼2×10¹⁸ cm⁻³ and Si-doped GaN films with electron concentrations n∼1×10¹⁹ cm⁻³ have been grown. N-type Al_0.10Ga_0.90N:Si films with resistivities as low as p ∼6.6×10⁻³ Ω-cm have been measured.     

MWIR DLPH HgCdTe photodiode performance dependence on substrate material

Mid wavelength infrared p-on-n double layer planar heterostructure (DLPH) photodiodes have been fabricated in HgCdTe double layers grown in situ by liquid phase epitaxy (LPE), on CdZnTe and for the first time on CdTe/sapphire (PACE-1). Characterization of these devices shed light on the nature of the material limits on device performance for devices performing near theoretical limits. LPE double layers on CdZnTe and on PACE-1 substrates were grown in a horizontal slider furnace. All the photodiodes are p-on-n heterostructures with indium as the n-type dopant and arsenic the p-type dopant. Incorporation of arsenic is via implantation followed by an annealing step that was the same for all the devices fabricated. The devices are passivated with MBE CdTe. Photodiodes have been characterized as a function of temperature. R₀A_imp values obtained between 300 and 78K are comparable for the two substrates and are approximately a factor of five below theoretical values calculated from measured material parameters. The data, for the PACE-1 substrate, indicates diffusion limited performance down to 110K. Area dependence gives further indications as to the origin of diffusion currents. Comparable R₀A_imp for various diode sizes indicates a p-side origin. R₀A and optical characteristics for the photodiodes grown on lattice-matched CdZnTe substrates and lattice mismatched PACE-1 are comparable. Howover, differences were observed in the noise characteristics of the photodiodes. Noise was measured on 50 × 50 μm devices held under a 100 mV reverse bias. At 110K, noise spectrum for devices from the two substrates is in the low 10⁻¹⁵ A/Hz^1/2 range. This value reflects the Johnson noise of the room temperature 10¹⁰ Ω feedback resistor in the current amplifier that limits the minimum measurable noise. Noise at 1 Hz, −100 mV and 120K for the 4.95 μm PACE-1 devices is in the 1–2 × 10⁻¹⁴ A/Hz^1/2, a factor of 5–10 lower than previously grown typical PACE-1 n⁺-on-p layers. Noise at 120K for the 4.60 μm PACE-1 and LPE on CdZnTe was again below the measurement technique limit. Greatest distinction in the noise characteristics for the different substrates was observed at 163K. No excess low frequency noise was observed for devices fabricated on layers grown by LPE on lattice-matched CdZnTe substrates. Photodiode noise measured at 1Hz, −100 mV and 163K in the 4.60 μm PACE-1 layer is in the 1–2×10⁻¹³ A/Hz^1/2, again a factor of 5–10 lower than previously grown PACE-1 n⁺-on-p layers. More variation in noise (4×10⁻¹³−2×10⁻¹² A/Hz^1/2) was observed for devices in the 4.95 μm PACE-1 layer. DLPH devices fabricated in HgCdTe layers grown by LPE on lattice-matched CdZnTe and on lattice-mismatched PACE-1 have comparable R₀A and quantum efficiency values. The distinguishing feature is that the noise is greater for devices fabricated in the layer grown on lattice mismatched substrates, suggesting dislocations inherent in lattice mismatched material affects excess low frequency noise but not zero bias impedance.     

High-Quality (211)B CdTe on (211)Si Substrates Using Metalorganic Vapor-Phase Epitaxy

High-quality (211)B CdTe buffer layers are required during Hg_1−x Cd _x Te heteroepitaxy on Si substrates. In this study, direct metalorganic vapor-phase epitaxy (MOVPE) of (211)B CdTe on Si, as well as CdTe on Si using intermediate Ge and ZnTe layers, has been achieved. Tertiary butyl arsine was used as a precursor to enable As surfactant action during CdTe MOVPE on Si. The grown CdTe/Si films display a best x-ray diffraction rocking-curve full-width at half-maximum of 64 arc-s and a best Everson etch pit density of 3 × 10⁵ cm⁻². These values are the best reported for MOVPE-grown (211)B CdTe/Si and match state-of-the-art material grown using molecular-beam epitaxy.     

Low resistivep-type ZnSe: A key for an efficient blue electroluminescent device

Highly conductivep-type ZnSe layers have been grown on GaAs substrates by vapor phase epitaxy in an open system. Iodine and hydrogen were used as transport agents. The ZnSe layers exhibited a conductivity up to 50 (Ωcm)⁻¹ and a carrier concentration of 4 × 10¹⁸ cm⁻³ together with a Hall mobility of 100 cm²/Vs. These values are the highest ones reported so far. Low-temperature photoluminescent spectra indicated new bound excitons. Electroluminescent metal/p-ZnSe/n-GaAs heterojunctions exhibited blue emission at 2.68 eV dominating the spectra.     

Control of Hole Concentration in Liquid-Phase Epitaxial Layers of PbTe by As Doping

Liquid-phase epitaxial layers of PbTe grown at ⋍55O‡C have been doped p-type over the concentration range 5 × 10¹⁶ − 5 × 10¹⁸cm^-3by adding from 0.004 − 10 at.% arsenic to the melts. The hole concentrations of the layers, which were grown on p+ substrates, were obtained from plasma reflectivity and thermoelectric probe measurements. The latter assessment technique is shown to be a reliable and simple method for determining the hole concentration in epitaxial layers with thicknesses greater than ≃ 5ym, provided the damage introduced by the probe is controlled. Damage can cause negative thermoelectric power signals to be obtained from p-type PbTe, showing that dislocations introduce donor centres in this material.     

High C-doping of MOVPE grown thin AlxGa1−xAs layers for AlGaAs/GaAs interband tunneling devices

High hole concentrations in LP-MOVPE grown GaAs and AlGaAs layers can be achieved by intrinsic C-doping using TMGa and TMAl as carbon sources. Free carrier concentrations exceeding 10²⁰ cm⁻³ were realised at low growth temperatures between 520–540°C and V/III ratios <1.2. The C-concentration increases significantly with the Al-content in Al_xGa_1−xAs layers. We observed an increase in the atom- and free carrier concentration from 5·10¹⁹ cm⁻³ in GaAs to 1.5·10²⁰ cm⁻³ in Al_0.2Ga_0.8As for the same growth conditions. Interband tunneling devices with n-type Si and p-type C-doped AlGaAs layers and barriers made of Al_0.25Ga_0.26In_0.49P have been investigated.