A high-frequency CMOS multi-modulus divider for PLL frequency synthesizers

A high-frequency divide-by-256–271 programmable divider is presented with the improved timing of the multi-modulus divider structure and the high-speed embedded flip-flops. The D flip-flop and logic flip-flop are proposed by using a fast pipeline technique, which contains single-phase, edge-triggered, ratioed, and high-speed technologies. The circuits achieve high-speed by reducing the capacitive load and sharing the delay between the combination logic blocks and the storage elements. By the way, it is suitable for realizing high-speed synchronous counters. The programmable divider using proposed flip-flops is measured in 0.25-μm CMOS technology with the operating clock frequency reaching as high as 4.7 GHz under the supply voltage of 3V.     

A high-speed frequency divider using n+-Ge Gate AlGaAs/GaAs MISFET's

A high-speed divide-by-four static frequency divider is fabricated using n+ -Ge gate AlGaAs/GaAs heterostructure MISFET's. The divider circuit consists of two master-slave T-type flip-flops (T-FF's) and an output buffer based on source-coupled FET logic (SCFL). A maximum toggle frequency of 11.3 GHz with a power dissipation of 219 mW per T-F/F is obtained at 300 K using 1.0-µm gate FET's.     

A New Field Programmable Gate Array: Architecture and Implementation

A new architecture of field programmable gate array for high-speed datapath applications is presented. Its implementation is facilitated by a configurable interconnect technology based on a onetime, two-terminal programmable, very low-impedance anti-fuse and by a configurable logic module optimized for datapath applications. The configurable logic module can effectively implement diverse logic functions including sequential elements such as latches and flip-flops, and arithmetic functions such as one-bit full adder and two-bit comparator. A novel programming architecture is designed for supplying large current through the anti-fuse element, which drops the on-resistance of anti-fuse below 20 Ω. The chip has been fabricated using a 0.8-μm n-well complementary metal oxide semiconductor technology with two layers of metalization.     

高速线性反馈移位寄存器的实现

线性反馈移位寄存器（ＬＦＳＲ）被广泛用于扩频通信，内建自测试和数字加密等许多领域。文中针对这一类电路的物理实现，提出了利用动态双边沿触发器实现高速线性反馈移位寄存器的一种新型结构。在不增加电路代价的前提下，获得了两倍于传统主－从铁速度，在此基础上，提出双相并行结构，从理论上分析，可得到最高的移位速度。     

TWO-INPUT PRESETTING TECHNIQUE AND DESIGN OF CMOS FLIP-FLOPS WITH A HIGH RADIX

By analysing the difficulty of previous flip-flops with a high radix, this paper proposes a logic design scheme with two presetting inputs. The circuit of a quaternary CMOS flip-flop is designed by using the transmission function theory. The result shows that its structure is simpler and its processing speed is higher than that of two binary flip-flops which store the equal information.     

Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor

The Cell Broadband Engine (Cell BE) is a multicore system-on-chip (SoC), implemented in a 90-nm high-performance silicon-on-insulator (SOI) technology, and optimized, within the triple constraints of area, power, and performance, to run at frequencies in excess of 3 GHz. The large scale of the design ($sim$75 million logic transistors, and about 750 000 latches and flip-flops), high-volume requirements, and the desire to support multiple manufacturing facilities dictated a need for very robust circuit practices, but at the same time, the high-frequency goal drove the use of more aggressive styles in certain critical regions of the design. This paper describes the local clock design, along with the various latches and flip-flops deployed, followed by a discussion of the circuit techniques used for the digital logic implementation, including special considerations for high-speed synthesized control logic, semi-custom and full-custom static circuit design and full-custom dynamic logic circuits. In addition, the synergistic processor element (SPE) circuit design is described, followed by the techniques and issues associated with the SRAM design. Finally, the methods used for electrical verification are described, these being an important part of the strategy for ensuring overall design robustness and first-silicon success.     

双端置数技术与高值CMOS触发器设计

在分析以往高值触发器困难的基础上本文提出了双端予置的逻辑设计方案。应用传输函数理论对四值CMOS触发器进行了电路设计。结果表明,与存贮相同信息量的二个二值触发器相比,它有较简单的结构与较快的工作速度。     

基于数据选择器和D触发器的多输入时序电路设计

为了探索多输入时序逻辑电路的简便实现方法,介绍了基于数据选择器和D触发器的多输入时序逻辑电路设计技术。即将D触发器和数据选择器进行组合,用触发器的现态作为数据选择器选择输入变量、数据选择器的输出函数作为触发器的D输入信号,构成既有存储功能又有数据选择功能的多输入端时序网络。由触发器的现态选择输入变量、所选择的输入变量决定触发器的次态转换方向。该方法适合实现互斥多变量时序逻辑电路,且在设计过程中不需要进行函数化简。     

基于集成门电路的三值单稳态触发器研究

通过对二值单稳态触发器设计原理的重新归纳,本文从三值三稳态触发器的正确设计出发,提出了二种三值单稳态触发器的设计方案。以ＲＣ微分电路为定时电路的设计已用ＰＳＰＩＣＥ程序进行计算机验证。     

A novel high-speed latching operation flip-flop (HLO-FF) circuitand its application to a 19-Gb/s decision circuit using a 0.2-μm GaAsMESFET

This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs Low-power Source-Coupled FET Logic (LSCFL). We reveal the high-speed operation mechanism of the HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series-gated master slave flip-flops and HLO-FF's based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision IC's confirm the accuracy of our analytical method and the high-speed operation of a HLO-FF decision circuit at 19 Gb/s     

触发器的广义特性方程及其应用

本文建立了触发器的广义特性方程，并介绍了它在时序逻辑电路分析中的应用     

A novel high-speed sense-amplifier-based flip-flop

A new sense-amplifier-based flip-flop is presented. The output latch of the proposed circuit can be considered as an hybrid solution between the standard NAND-based set/reset latch and the NC-/sup 2/MOS approach. The proposed flip-flop provides ratioless design, reduced short-circuit power dissipation, and glitch-free operation. The simulation results, obtained for a 0.25-/spl mu/m technology, show improvements in the clock-to-output delay and the power dissipation with respect to the recently proposed high-speed flip-flops. The new circuit has been successfully employed in a high-speed direct digital frequency synthesizer chip, highlighting the effectiveness of the proposed flip-flop in high-speed standard cell-based applications.     

A 20-Gb/s flip-flop circuit using direct-coupled FET logic

A new type of direct-coupled FET logic (DCFL) flip-flop called the memory cell type flip-flop (MCFF) is presented. The MCFF operates faster than conventional DCFL flip-flops and enhances the DCFL's advantages, such as low power consumption and high packing density. A D-flip-flop IC and a 1/8 divider IC were developed using the MCFF. These ICs were fabricated using 0.2-μm-gate pseudomorphic inverted HEMTs. The D-flip-flop IC is confirmed to operate up to 20 Gb/s. The 1/8 divider is toggled up to a maximum frequency of 25 GHz. These results prove that the MCFF enables DCFL circuits applicable not only to large-scale integration but to small-scale and medium-scale integration operating up to 20 Gb/s as well     

A 9-GHz frequency divider using Si bipolar super self-aligned process technology

A very high-speed 1/8 frequency divider is fabricated, using Si bipolar super self-aligned process technology (SST), and tested. The circuit consists of three T-connected D-type master-slave flip-flops and buffers. A low voltage swing (225 mV) differential circuit technique is adopted for the first stage T-type flip-flop. The divider is capable of operating at up to 9 GHz with a power dissipation of 554 mW.     

Injection-coupled synchronous logic

A novel injector structure used in conjunction with an I/SUP 2/L gate is proposed and its application to the design of current comparators and synchronous logic is described. The operation and fabrication of basic gates as well as current comparators, SR and T flip-flops are discussed. The new gate structures exhibit similar power/spl times/delay products, but lead to a considerable increase in functional density when compared to standard I/SUP 2/L in synchronous logic applications.     

A 1-V 2.5-mW 5.2-GHz frequency divider in a 0.35-/spl mu/m CMOS process

A 1-V low-power high-speed dynamic-loading frequency divider is proposed using novel D flip-flops with a common-gate topology and with a single clock phase. A simple and accurate small-signal analysis model is provided to estimate the operating frequencies of the divider. Implemented in a standard digital 0.35-/spl mu/m CMOS process and at 1-V supply, the proposed frequency divider measures a maximum operating frequency up to 5.2 GHz with a power consumption of 2.5 mW.     

A digital library for a flexible low-voltage organic thin-film transistor technology

This paper presents the design, fabrication and characterization of digital logic gates, flip-flops and shift registers based on low-voltage organic thin-film transistors (TFTs) on flexible plastic substrates. The organic transistors are based on the p-channel organic semiconductor dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) and have channel lengths as short as 5 μm and gate-to-contact overlaps of 20 μm. The organic TFT is modeled which allows us to simulate different logic gate architectures prior to the fabrication process. In this study, the zero-VGS, biased-load and pseudo-CMOS logic families are investigated, where their static and dynamic operations are modeled and measured. The inverter and NAND gates use channel length of 5 μm and operate with a supply voltage of 3 V. Static and dynamic master-slave flip-flops based on biased-load and pseudo-CMOS logic are designed, fabricated and characterized. A new design for biased-load dynamic flip-flops is proposed, where transmission gate switches are implemented using only p-channel transistors. 1-stage shift registers based on the new design and fabricated using TFTs with a channel length of 20 μm operate with a maximum frequency of about 3 kHz.     

In-memory designing of Delay and Toggle flip-flops utilizing Memristor Aided loGIC (MAGIC)

‘Computations inside Memory’ has become a latest area of research as ‘memory with computing skills’ accelerates the chances of developing ‘beyond-Von Neumann machines’, that is believed to be advantageous in terms of performance and energy-efficiency. ‘Memristors’ are considered as potential devices for building such memories, as they are highly dense, non-volatile scalable devices with faster switching times and lower energy dissipation and are also compatible with the existing CMOS-technology. Additionally, memristors fit in crossbar structure and can perform logic-computations, when different voltages are applied across them. Previously, various synthesis works have been reported for logic realization using memristors. But logic blocks, implemented using synthesis tools, are not always completely optimized. In this context, we present the alternative memristive-designs for the two most commonly used digital units—Delay (D) and Toggle (T) flip-flops. The proposed designs are based on Memristor Aided loGIC (MAGIC) design style and are specific to crossbar-based pure memristive-memories. A relevant simulation methodology is presented for simulating the proposed MAGIC-designs of D and T flip-flops in Cadence Virtuoso. Comparison with the existing designs of D, T flip-flops (using IMPLY) revealed that both the proposed D, T flip-flops are more performance-efficient (by 28.571%, 20% respectively) and more energy-efficient (by 83.873%, 82.905% respectively) than their corresponding IMPLY-peers. Also, the proposed D, T flip-flops are found to use reduced crossbar areas (by 46.667%, 45% respectively) relative to their counterparts generated using a recent synthesis technique, which makes the designs suitable for massive parallel executions inside memristive-memories of any size.     

Partial scan flip-flop selection by use of empirical testability

Partial serial scan as a design for testability technique permits automatic generation of high fault coverage tests for sequential circuits with less hardware overhead and less performance degradation than full serial scan. The objective of the partial scan flip-flop selection method proposed here is to obtain maximum fault coverage for the number of scan flip-flops selected. Empirical Testability Difference (ETD), a measure of potential improvement in the testability of the circuit, is used to successively select one or more flip-flops for addition or deletion of scan logic. ETD is calculated by using testability measures based on empirical evaluation of the circuit with the acutal automatic test pattern generation (ATPG) system. In addition, once such faults are known, ETD focuses on the hard-to-detect faults rather than all faults and uses heuristics to permit effective selection of multiple flip-flops without global optimization. Two ETD algorithms have been extensively tested by using FASTEST ATPG [1, 2] on fourteen of the ISCAS89 [3] sequential circuits. The results of these tests indicate that ETD yields, on average, 35% fewer uncovered detectable faults for the same number of scanned flip-flops or 27% fewer scanned flip-flops for comparable fault coverage relative to cycle-breaking methods.This work was performed while the author was with the University of Wisconsin-Madison.     

Design and Application of Power Optimized High-Speed CMOS Frequency Dividers

Frequencies in the gigahertz range translate switching activity and internal node capacitance quickly to high power values. Therefore, the power optimized design of high-speed CMOS logic-based frequency dividers is sensitive to circuit partitioning and selection of flip-flop-type and logic family. On the basis of two circuit examples, the design of highly power optimized dividers based on conventional CMOS logic is demonstrated. First, a divide-by-15 circuit based on sense-amplifier and master-slave flip-flops is discussed. A 5.5-GHz demonstrator implemented in a 90-nm low-power CMOS technology consumes only 190 $mu$W/GHz for a supply voltage of 1.1 V. Second, an even faster CMOS divider concept without static power consumption, except leakage power, is proposed. The circuit divides an input signal by two and generates four phases with highly accurate phase skew of 90 deg. The maximum operation frequency is 11.6 GHz for a supply voltage of 1.5 V, slow process and worst case operation parameters. Higher frequencies can be achieved by a hybrid approach where the signal is first divided by a factor of two in a single current mode logic (CML) stage and then by the proposed circuit by another factor of two for the generation of the four phases. The divider is applied to dual modulus pre-scalers and IQ receivers. A variant of the circuit contains an intrinsic phase-rotator, allowing pre-scalers without any phase synchronization. Therewith, the power consumption is not only reduced due to the efficient divider implementation but also by a simplified architecture of the overall pre-scaler.