Analytical models and algorithms for the efficient signal integrity verification of inductance-effect-prominent multicoupled VLSI circuit interconnects

Novel signal integrity verification models and algorithms for inductance-effect- prominent RLC interconnect lines are developed by using a traveling-wave-based waveform approximation (TWA) technique. The multicoupled line responses are decoupled into the eigenmodes of the system in order to exploit the TWA technique. Then, the response signals are mathematically represented by the linear combination of each eigenmode response based on TWA, followed by reporting the signal integrity models and algorithms for the multicoupled lines. The signal integrity of VLSI circuit interconnects is complicatedly correlated with input signal switching-patterns, layout geometry, and termination conditions. It is shown that the technique can be efficiently employed for complicated multicoupled interconnect lines with various termination conditions and the signal transients based on the technique have excellent agreement with SPICE simulations. Thus, with the proposed technique, the switching-dependent signal delay, crosstalk, ringing, and glitches of the inductance-effect-prominent RLC interconnect lines can be accurately as well as efficiently determined.     

A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect

Due to decreasing device sizes and increasing clock speed, interconnect inductance is becoming an important factor in the on-chip delay analysis of deep submicrometer technologies. This delay has been represented as an RC model in the available electric design automation tools. In this paper, we model the on-chip interconnect as a RLC for systems running at multigigahertz frequencies. A static-extraction analysis method optimized for ASICs is detailed. It considers all the lines within the vicinity of the target signal line as return paths.     

An improved sensorless driving method for SRM using a phase-shift circuit technique

This paper presents an improved sensorless driving method for switched reluctance motor (SRM) using a phase-shift circuit technique. The conventional method consists of impressing short voltage pulses during unenergized phases, measuring the phase current pulses, and finding the correlation between the filtered current signals and rotor position. However, the filtering process causes a signal phase delay which varies with motor speed. This delay must be compensated for in providing the sensorless signal which is proper to the rotor position. A solution for this phase delay compensation, based on a simple analog and digital circuit, is proposed in this paper.     

Oscillation Ring Delay Test for High Performance Microprocessors

This paper proposes a new test scheme, oscillation ring test, and its associated test circuit organization for delay fault testing for high performance microprocessors. For this test scheme, the outputs of the circuit under test are connected to its inputs to form oscillation rings and test vectors which sensitize circuit paths are sought to make the rings oscillate. High speed transition counters or oscillation detectors can then be used to detect whether the circuit is working normally or not. The sensitizable paths of oscillation rings cover all circuit lines, detecting all gate delay faults, a large part of hazard free robust path delay faults and all the stuck-at faults. It has the advantage of testing the circuit at the working speed of the circuit. Also, with some modification, the scheme can also be used to measure the maximum speed of the circuit. The scheme needs minimal simple added hardware, thus ideal for testing, embedded circuits and microprocessors.     

A high-speed sensing scheme for 1T dynamic RAMs utilizing theclamped bit-line sense amplifier

A clamped-bit-line sense amplifier (CBLSA) capable of very high-speed operation in one-transistor (1T) DRAM applications has been developed. Results from an experimental test chip demonstrate that the speed of the new circuit is insensitive to bit-line capacitance. Circuit speed is also found to be insensitive to the initial bit-line difference voltage. The CBLSA maintains a low impedance fixed potential on the bit lines during sensing, virtually eliminating sensitivity to inter-bit-line noise coupling and minimizing power supply bounce during sensing. The new sense amplifier operates at higher speeds than conventional circuits and still dissipates less power     

A high-speed clamped bit-line current-mode sense amplifier

A clamped bit-line current-mode sense amplifier that maintains a low-impedance fixed potential on the bit lines is introduced. Using a general model for active-drive memory cells that include the two-transistor (2T) and three-transistor (3T) dynamic cells and the four-transistor/two-resistor (4T-2R) and six-transistor (6T) static cells, the new sense amplifier is shown to have a response speed that is insensitive to bit-line capacitance. This is achieved by relocating the large bit-line capacitance to a node within the sense amplifier that has only a minimal effect on the speed of the circuit. Bit-line clamping also minimizes inter-bit-line voltage noise coupling     

Design methodology for synthesizing clock distribution networksexploiting nonzero localized clock skew

An integrated top-down design methodology is presented in this brief for synthesizing high performance clock distribution networks based on application dependent localized clock skew. The methodology is divided into four phases: (1) determining an optimal clock skew schedule composed of a set of nonzero clock skew values and the related minimum clock path delays; (2) designing the topology of the clock distribution network with delays assigned to each branch based on the circuit hierarchy, the aforementioned clock skew schedule, and minimizing process and environmental delay variations; (3) designing circuit structures to emulate the delay values assigned to the individual branches of the clock tree; and (4) designing the physical layout of the clock distribution network. The clock distribution network synthesis methodology is based on CMOS technology. The clock lines are transformed from distributed resistive capacitive interconnect lines into purely capacitive interconnect lines by partitioning the RC interconnect lines with inverting repeaters. Variations in process parameters are considered during the circuit design of the clock distribution network to guarantee a race-free circuit. Nominal errors of less than 2.5% for the delay of the clock paths and 7% for the clock skew between any two registers belonging to the same global data path as compared with SPICE Level-3 are demonstrated     

Analysis of the Impacts of Signal Slew and Skew on the Behavior of Coupled RLC Interconnects for Different Switching Patterns

This paper presents an in-depth analysis of signal slew and skew variations in coupled inductive lines for different switching patterns. It is revealed that variations of rise/fall time and skew alter the behavior of coupled inductive lines under different switching patterns. We observe that crosstalk noise reduces with increasing signal skew, and the impact of skew variation on crosstalk noise is more prominent for lines with strong capacitive coupling. A performance comparison is done between power supply and ground line as inductive shield, and it is found that ground lines work better than power lines in inductive crosstalk minimization. The 100%-delay measurement technique has been proposed as opposed to the conventional 50%-delay method, and we notice that the 50%-delay technique underestimates the propagation delay for an inductive dominant line with varying signal slew times. Closed-form equations for propagation delay in terms of signal slew time have been derived, which are within 9% of HSPICE-simulated results for a set of interconnect structures. These expressions are simple, and accuracy increases with growing number of interconnect lines.      

Capacitance coupling immune, transient sensitive accelerator forresistive interconnect signals of subquarter micron ULSI

This paper presents a new circuit scheme called a transient sensitive accelerator (TSA) circuit for highly resistive interconnects. The TSA can reduce both delay time and crosstalk voltage. Using the TSA with an interconnect length of 30 mm reduces delay time and crosstalk voltage by 29% and 20%, respectively. A further advantage is that the TSA operates in self-time and thus can be applied to bidirectional signal communication     

Fast low-power decoders for RAMs

Decoder design involves choosing the optimal circuit style and figuring out their sizing, including adding buffers if necessary. The problem of sizing a simple chain of logic gates has an elegant analytical solution, though there have been no corresponding analytical results until now which include the resistive effects of the interconnect. Using simple RC models, we analyze the problem of optimally sizing the decoder chain with RC interconnect and find the optimum fan-out to be about 4, just as in the case of a simple buffer chain. As in the simple buffer chain, supporting a fan-out of 4 often requires noninteger number of stages in the chain. Nevertheless, this result is used to arrive at a tight lower bound on the delay of a decoder. Two simple heuristics for sizing of real decoder with integer stages are examined. We evaluate a simple technique to reduce power, namely, reducing the sizes of the inputs of the word drivers, while sizing each of the subchains for maximum speed, and find that it provides for an efficient mechanism to trade off speed and power. We then use the RC models to compare different circuit techniques in use today and find that decoders with two input gates for all stages after the predecoder and pulse mode circuit techniques with skewed N to P ratios have the best performance     

Evaluating the effects of temperature gradients and currents nonuniformity in on-chip interconnects

The paper provides a compact but accurate electro-thermal model of a long wiring on-chip interconnect embedded in the complex layout of a ULSI digital circuit. The proposed technique takes into account both the effect of temperature gradients over the chip substrate and the interconnect self-heating due to current flow. The proposed compact model is well suited to be interfaced with commercially available CAD tools employed for interconnect parasitic extraction and signal integrity verification. The paper also investigates the electro-thermal effects that arise in a long wiring on-chip interconnect in which current flow is dominated by displacement currents and thus is not uniform along the line.     

Design and implementation of a delay-optimized universal programmable routing circuit for FPGAs

This paper presents a universal field programmable gate array (FPGA) programmable routing circuit,focusing primarily on a delay optimization. Under the precondition of the routing resource's flexibility and routability, the number of programmable interconnect points (PIP) is reduced, and a multiplexer (MUX) plus a BUFFER structure is adopted as the programmable switch. Also, the method of offset lines and the method of complementary hanged end-lines are applied to the TILE routing circuit and the I/O routing circuit, respectively. All of the above features ensure that the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. Meanwhile, the BUFFER driver is optimized to decrease the signal delay by up to 5%. The proposed routing circuit is applied to the Fudan programmable device (FDP) FPGA, which has been taped out with an SMIC 0.18-μm logic 1P6M process. The test result shows that the programmable routing resource works correctly, and the signal delay over the chip is highly uniform and predictable.     

Modeling and electrical analysis of seamless high off-chipconnectivity (SHOCC) interconnects

Scaling down on-chip interconnect cross-sectional dimensions results not only in higher circuit wiring density, but also in the long lossy line problem, wherein the long lines become highly resistive and have unacceptable delays. One possible solution to the problem of long lossy lines is to transfer these lines off-chip using seamless high off-chip connectivity (SHOCC) technology. In this work, me modeled and studied the electrical performance of SHOCC signal lines. The performance of SHOCC interconnects was compared with that of typical on-chip interconnerts. Modeling and simulation results, along with recommendations with regards to driver sizes and the type of interconnect that should be used, are presented     

Transient analysis of lossy transmission lines: an efficient approach based on the method of Characteristics

This paper is devoted to transient analysis of lossy transmission lines characterized by frequency-dependent parameters. A public dataset of parameters for three line examples (a module, a board, and a cable) is used, and a new example of on-chip interconnect is introduced. This dataset provides a well established and realistic benchmark for accuracy and timing analysis of interconnect analysis tools. Particular attention is devoted to the intrinsic consistency and causality of these parameters. Several implementations based on generalizations of the well-known method-of-characteristics are presented. The key feature of such techniques is the extraction of the line modal delays. Therefore, the method is highly optimized for long interconnects characterized by significant propagation delay. Nonetheless, the method is also successfully applied here to a short high/loss on-chip line, for which other approaches based on lumped matrix rational approximations can also be used with high efficiency. This paper shows that the efficiency of delay extraction techniques is strongly dependent on the particular circuit implementation and several practical issues including generation of rational approximations and time step control are discussed in detail.     

S-parameter-measurement-based high-speed signal transientcharacterization of VLSI interconnects on SiO2-Si substrate

A new S-parameter-based signal transient characterization method for very large scale integrated (VLSI) interconnects is presented. The technique can provide very accurate signal integrity verification of an integrated circuit (IC) interconnect line since its S-parameters are composed of all the frequency-variant transmission line characteristics over a broad frequency band. In order to demonstrate the technique, test patterns are designed and fabricated by using a 0.35 μm complementary metal-oxide-semiconductor (CMOS) process. The time-domain signal transient characteristics for the test patterns are then examined by using the S-parameters over a 50 MHz to 20 GHz frequency range. The signal delay and the waveform distortion presented in the interconnect lines based on the proposed method are compared with the existing interconnect models. Using the experimental characterizations of the test patterns, it is shown that the silicon substrate effect and frequency-variant transmission line characteristics of IC interconnects can be very crucial     

DEPACT: delay extraction-based passive compact transmission-line macromodeling algorithm

With the continually increasing operating frequencies, signal integrity and interconnect analysis in high-speed designs is becoming increasingly important. Recently, several algorithms were proposed for macromodeling and transient analysis of distributed transmission line interconnect networks. The techniques such as method-of-characteristics (MoC) yield fast transient results for long delay lines. However, they do not guarantee the passivity of the macromodel. It has been demonstrated that preserving passivity of the macromodel is essential to guarantee a stable global transient simulation. On the other hand, methods such as matrix rational approximation (MRA) provide efficient macromodels for lossy coupled lines, while preserving the passivity. However, for long lossy delay lines this may require higher order approximations, making the macromodel inefficient. To address the above difficulties, this paper presents a new algorithm for passive and compact macromodeling of distributed transmission lines. The proposed method employs delay extraction prior to approximating the exponential stamp to generate compact macromodels, while ensuring the passivity. Validity and efficiency of the proposed algorithm is demonstrated using several benchmark examples     

X-Calibration: A Technique for Combating Excessive Bitline Leakage Current in Nanometer SRAM Designs

In an SRAM circuit, the leakage currents on the bit lines are getting increasingly prominent with the dwindling of transistors' threshold voltages as the technology scales down to 90 nm and beyond. Excessive bit-line leakage current results in slower read operations or even functional failure. In this paper, we present a new technique, called X-calibration, to combat this phenomenon. Unlike the previous method that attempts to compensate the leakage current directly, this scheme first transforms the bit-line leakage current into an equilibrium offset voltage across the bit-line pair, and then simple circuitry is utilized to cancel this offset accurately at the input of the sense amplifier so that the sensing is not affected by the bit-line leakage. SPICE simulation of a 1 Kbit SRAM macro shows that this X-calibration scheme can handle 83% higher bit-line leakage current than the previous bit-line leakage compensation scheme. Measurement results of the test chip show that the SRAM macro adopting X-calibration scheme can cope with up to 320 $mu{hbox{A}}$ bit-line leakage current.      

Modelling of coupled interconnect lines for integrated circuits

A coupled interconnect model is developed using even mode and odd mode capacitance analysis. Signal coupling is presented in terms of interconnect width, substrate thickness, interconnect line spacing, and frequency. Picosecond photoconductor based measurements of coupled transmission lines on the integrated circuit support the even and odd mode signal transmission simulation results. SPICE circuit simulation is used to demonstrate the model utility and explore the sensitivity of the self- and mutual capacitances and inductances in signal crosstalk.     

Effects of inductance on the propagation delay and repeaterinsertion in VLSI circuits

A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale     

Designing fast on-chip interconnects for deep submicrometer technologies

This paper proposes a solution to the problem of improving the speed of on-chip interconnects, or wire delay, for deep submicron technologies where coupling capacitance dominates the total line capacitance. Simultaneous redundant switching is proposed to reduce interconnect delays. It is shown to reduce delay more than 25% for a 10-mm long interconnect in a 0.12-/spl mu/m CMOS process compared to using shielding and increased spacing. The paper also proposes possible design approaches to reduce the delay in local interconnects.