低压CMOS带隙电压源

介绍了CMOS带隙电压源的基本原理,并根据目前CMOS集成电路工艺发展对低电源电压的要求,详细地分析了几种能产生低输出电压且能兼容标准CMOS工艺的CMOS带隙电压源电路.这些电路所需的电源电压只有1V左右,并且都能够输出1V以下具有零温度系数的参考电压,其中有些电路的输出电压可以由电阻的比值来调节,因而可以增加电路设计的灵活性.本文还对低压CMOS带隙电压源电路的低频和高频噪声特性进行了深入分析,提出了改善输出参考电压噪声特性的途径.     

A CMOS piecewise curvature-compensated voltage reference

This paper presents a novel approach to the design of a high-precision CMOS voltage reference. The proposed circuit utilizes MOS transistors instead of bipolar transistors to generate positive and negative temperature coefficient (TC) currents summed up to a resistive load to generate low TC reference voltage. A piecewise curvature-compensation technique is also used to reduce the TC of the reference voltage within a wider temperature range. The output reference voltage can be adjusted in a wide range according to different system requirements by setting different parameters such as resistors and transistor aspect ratios. The proposed circuit is designed for TSMC 0.6 μm standard CMOS process. Spectre-based simulations demonstrate that the TC of the reference voltage is 4.3 ppm/°C with compensation compared with 107 ppm/°C without compensation in the temperature ranges from −15 to 95 °C using a 1.5 V supply voltage.     

CMOS voltage reference based on threshold voltage and thermal voltage

A fully CMOS based voltage reference circuit is presented in this paper. The voltage reference circuit uses the difference between gate-to-source voltages of two MOSFETs operating in the weak-inversion region to generate the voltage with positive temperature coefficient. The reference voltage can be obtained by combining this voltage difference and the extracted threshold voltage of a saturated MOSFET which has a negative temperature coefficient. This circuit, implemented in a standard 0.35-μm CMOS process, provides a nominal reference voltage of 1.361 V at 2-V supply voltage. Experimental results show that the temperature coefficient is 36.7 ppm/°C in the range from −20 to 100°C. It occupies 0.039 mm² of active area and dissipates 82 μW at room temperature. With a 0.5-μF load capacitor, the measured noise density at 100 Hz and 100 kHz is 3.6 and 2 5 \textnV/?{\textHz} , 2 5\,{\text{nV}}/\sqrt {\text{Hz}} , respectively.     

Bandgap voltage reference sources in CMOS technology

Two configurations are proposed for the implementation of bandgap reference sources in CMOS technology. The circuits presented are capable of high temperature operation, and allow a choice of the positive supply rail, the negative supply rail, or ground as the reference point.     

CMOS带隙基准电压源的设计

许多模拟电路需要性能较好的带隙基准电压源,如ADC,DAC等.对工艺、电源电压、负载变化不敏感的带隙基准电压源在模拟电路中得到了广泛的应用.现详细分析并说明了设计这样的带隙基准电压源电路需要考虑的问题.     

无电阻低压低温漂的CMOS基准电压源

结合工作在亚阈值区、饱和区和线性区的MOS管,提出一种纯MOS结构的基准电压源,其结构能有效补偿MOS管的载流子迁移率和亚阈值斜率的温度系数.基于SMIC 0.13 μm的CMOS工艺的仿真结果表明,在温度为-55～90 ℃的范围内,输出电压的温度系数为5 ppm/℃.在室温时,整个电路能在低到0.9 V的电源电压下工作并消耗0.68 μW的功耗.     

A wide dynamic range CMOS PFM digital pixel sensor with in-pixel variable voltage reference

This paper proposes a new pulse-frequency-modulation (PFM) digital pixel sensor (DPS) with a variable reference voltage. An in-pixel variable reference voltage generator is employed to ramp the reference voltage of the comparator locally such that the comparison of photo diode current and the reference voltage can take place earlier. This expands the dynamic range of the pixel sensor when the level of illumination is low. The complexity of routing of the proposed pixel sensor are comparable to that of digital pixel sensor with a constant reference voltage. The additional hardware cost of the proposed digital pixel sensor is only a capacitor and two static inverters, resulting in a fill factor that is comparable to those of digital pixel sensors with a constant global reference voltage. Factors that are critically to the performance of the proposed pixel sensor are examined in detail. The proposed digital pixel sensor has been designed in TSMC-0.18 μm 1.8 V CMOS technology and analyzed using Spectre with BSIM3V3 device models. Simulation results demonstrate that the proposed PFM digital pixel has a dynamic range of 120 dB when the integration time is set to 60 μs, approximately 40 dB more than the corresponding PFM digital pixel sensor with a constant reference voltage. The fill factor of the proposed pixel sensor is 20%, comparable to that of pixel sensors with a constant reference voltage.     

无电阻低压低温漂的CMOS基准电压源

结合工作在亚阈值区、饱和区和线性区的MOS管,提出一种纯MOS结构的基准电压源,其结构能有效补偿MOS管的栽流子迁移率和亚闽值斜率的温度系数。基于SMIC0．13μm的CMOS工艺的仿真结果表明,在-5-90℃的范围内。输出电压的温度系数为5ppm／℃。在室温时,整个电路能在低到0．9V的电源电压下工作并消耗0．68μW的功耗。     

A low supply voltage high PSRR voltage reference in CMOS process

This paper describes a bandgap voltage reference circuit that operates with a 3 V power supply and is compatible with a digital CMOS process. The use of a simple circuit topology results in a small silicon area of 0.07 mm², a power consumption of 1 mW and a high power supply rejection over a wide frequency band. The circuit realizes a temperature coefficient of 85 ppm/°C and a standard deviation of 20 mV without trimming     

A floating CMOS bandgap voltage reference for differentialapplications

The circuit is suitable for precision mixed-mode systems using the differential approach, especially for the case of single-supply operation. An experimental prototype, realized in a 2-μm CMOS technology, generates a continuous-time low-impedance voltage of 2.48 V±24 mV before trimming. The temperature coefficient measured on 30 samples ranges from -20 to L32 p.p.m./°C in the temperature range from 0 to 100°C. Thanks to the differential approach, a high-frequency power supply rejection of -50 dB at 100 kHz was achieved. The active area of the chip is 1800 mil² and the circuit dissipates 6 mW when operated from a single 5-V supply     

High-speed divider using GaAs ECL/CML gate array

An ECL/CML gate array using GaAs/AlGaAs heterojunction bipolar transistors is reported for the first time. The gate array has up to 12 programmable inputs and outputs. A divide-by-eight circuit configured on this array has been clocked at 3.1 GHz.<>     

A CMOS voltage reference based on weighted /spl Delta/V/sub GS/ for CMOS low-dropout linear regulators

A CMOS voltage reference, which is based on the weighted difference of the gate-source voltages of an NMOST and a PMOST operating in saturation region, is presented. The voltage reference is designed for CMOS low-dropout linear regulators and has been implemented in a standard 0.6-/spl mu/m CMOS technology (V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C). The occupied chip area is 0.055 mm/sup 2/. The minimum supply voltage is 1.4 V, and the maximum supply current is 9.7 /spl mu/A. A typical mean uncalibrated temperature coefficient of 36.9 ppm//spl deg/C is achieved, and the typical mean line regulation is /spl plusmn/0.083%/V. The power-supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz are -47 and -20 dB, respectively. Moreover, the measured noise density with a 100-nF filtering capacitor at 100 Hz is 152 nV//spl radic/(Hz) and that at 100 kHz is 1.6 nV//spl radic/(Hz).     

高电源抑制比的CMOS亚阈值多输出电压基准

基于工作在亚阈值区的MOS器件,运用CMOS电流模基准时CATA和PTAT电流求和的思想,提出一种具有低温漂系数、高电源抑制比(PSRR)的CMOS电压基准源,该电路可同时提供多个输出基准电压,且输出电压可调.该基准源基于CSMC 0.5 μm标准CMOS工艺,充分利用预调节电路并改进电流模基准核心电路,使整个电路的电源抑制比在低频时达到122 dB,温度系数(TC)在0～100℃的温度范围内约7 ppm/℃.     

A sub-1 V high-precision CMOS bandgap voltage reference

A third-order, sub-1 V bandgap voltage reference design for low-power supply, high-precision applications is presented. This design uses a current-mode compensation technique and temperature-dependent resistor ratio to obtain high-order curvature compensation. The circuit was designed and fabricated by SMIC 0.18 μm CMOS technology. It produces an output reference of 713.6 mV. The temperature coefficient is 3.235 ppm/℃ in the temperature range of -40 to 120 ℃, with a line regulation of 0.199 mV/V when the supply voltage varies from 0.95 to 3 V. The average current consumption of the whole circuit is 49 μA at the supply voltage of 1 V.     

A CMOS threshold voltage reference source for very-low-voltage applications

This paper describes a CMOS voltage reference that makes use of weak inversion CMOS transistors and linear resistors, without the need for bipolar transistors. Its operation is analogous to the bandgap reference voltage, but the reference voltage is based on the threshold voltage of an nMOS transistor. The circuit implemented using 0.35 μm n-well CMOS TSMC process generates a reference of 741 mV under just 390 nW for a power supply of only 950 mV. The circuit presented a variation of 39 ppm/°C (after individual resistor trimming) for the −20 to +80 °C temperature range, and produced a line regulation of 25 mV/V for a power supply of up to 3 V.     

高电源抑制比的CMOS亚阈值多输出电压基准

基于工作在亚阈值区的MOS器件,运用CMOS电流模基准对CATA和PTAT电流求和的思想．提出一种具有低温漂系数、高电源抑制比（PSRR）的CMOS电压基准源,该电路可同时提供多个输出基准电压,且输出电压可调。该基准源基于CSMC0．5μm标准CMOS工艺,充分利用预调节电路并改进电流模基准核心电路。使整个电路的电源抑制比在低频时达到122dB,温度系数（TC）在0-100℃的温度范围内约7ppm／℃。     

Back-gated CMOS on SOIAS for dynamic threshold voltage control

The simultaneous reduction of power supply and threshold voltages for low-power design without suffering performance losses will eventually reach the limit of diminishing returns as static leakage power dissipation becomes a significant portion of the total power consumption. This is especially acute in systems that are idling most of the time. In order to meet the opposing requirements of high performance at reduced power supply voltage and low-static leakage power during idle periods, a dynamic threshold voltage control scheme is proposed. A novel Silicon-On-Insulator (SOI)-based technology called Silicon-On-Insulator-with-Active-Substrate (SOIAS) was developed whereby a back-gate is used to control the threshold voltage of the front-gate; this concept was demonstrated on a selectively scaled CMOS process implementing discrete devices and ring oscillators. For a 250 mV switch in threshold voltage, a reduction of 3-4 decades in subthreshold leakage current was measured     

一种工作在亚阈值区的低电压低功耗基准电压电路

本文提出了一种不使用三极管而只使用工作在亚阈值区的晶体管和电阻的电压基准。使用0.18um工艺进行流片以及测试的结果表明：本文所设计的电压基准可在0.8V的低电压下工作,在温度从-35˚C到85˚C的范围内,温度系数为370ppm/˚C;电源电压从0.8V到3V的条件下,电压偏差小于0.1%。而且在电源电压为0.8V的条件下,整个芯片的功耗只有1.5uA。     

一种CMOS动态闩锁电压比较器的优化设计

提出了一种应用于Pipeline ADC和Sigma-Delta ADC中改进的动态闩锁电压比较器。采用0.35μm CMOS N阱工艺设计,工作于2.5V单电源电压。通过详细的分析和优化,使比较器具有较小的输入失调电压和踢回噪声,仿真结果表明它的输入失调电压分布范围为28.6mV,最高工作频率200MHz、功耗230μW。